1)Overview of the AVR Microcontroller Family

( Alf-Egil Bogen and Vegard Wollan RISC (Reduced Instruction Set Computing))
The AVR family is a group of RISC-based 8-bit microcontrollers developed by Atmel (now part of
Microchip Technology). AVR microcontrollers are widely used in embedded systems due to their high
performance, low power consumption, and ease of programming.

1. Key Features of AVR Family

● 8-bit RISC architecture
● Harvard architecture (separate program and data memories)
● Single-cycle instruction execution
● 32 general-purpose working registers
● On-chip Flash program memory(Program ROM)
● On-chip SRAM and EEPROM
● Low power consumption with multiple sleep mode
● In-system programmable (ISP)( In-System Programmable (ISP)
In-System Programmable (ISP) means the microcontroller’s program memory (Flash) can be
programmed or reprogrammed while the chip is already mounted in the system, without removing it
from the circuit.)
● Supports C and Assembly language programming
2. AVR Architectural Characteristics
● RISC instruction set

Most instructions execute in one clock cycle

● Harvard architecture

Program memory (Flash) and data memory (SRAM) are accessed separately
● High throughput

Up to 1 MIPS per MHz

● Orthogonal instruction set

All registers can be used with most instructions

3. AVR Family Classification

AVR microcontrollers are classified into three major groups:
(a) TinyAVR Series
● Small pin count and memory
● Low cost and low power
● Used in simple control applications
Examples: ATtiny13, ATtiny25, ATtiny85

Applications: LED control, small sensors, simple automation

(b) MegaAVR Series

● Larger memory and more peripherals
● Most popular AVR family
● Used in medium to complex embedded systems
Examples: ATmega8, ATmega16, ATmega32, ATmega328

Applications: Arduino boards, industrial control, robotics

(c) XMEGA Series

● High-performance AVR devices
● Advanced peripherals and DMA
● Designed for real-time and high-speed applications
Examples: ATxmega64, ATxmega128

Applications: Data acquisition, motor control, communication systems

4. On-Chip Peripherals
AVR microcontrollers include rich peripherals such as:
● GPIO ports
● Timers/Counters
● PWM modules
● ADC (10-bit)
● USART (Universal Synchronous/Asynchronous Receiver Transmitter)
● SPI (Serial Peripheral Interface)
● I²C (TWI – Two-Wire Interface)
● Watchdog Timer
● Analog Comparator

5. Memory Organization
● Flash Memory – Program storage
● SRAM – Data and stack
● EEPROM – Non-volatile data storage

6. Power Management Features

Microcontroller enters low-power state when idle.
Mode Description
CPU stopped, peripherals
Idle running
Power-down CPU & peripherals stopped
Timer + asynchronous clock
Power-save active
Standby / Extended
standby Fast wake-up

These features make AVR suitable for battery-operated systems.

7. Advantages of AVR Family

● Simple and efficient architecture
● High performance per clock cycle
● Easy to program and debug
● Large ecosystem and tool support
● Ideal for teaching and learning embedded systems
8. Typical Applications
● Embedded control systems
● Consumer electronics
● Industrial automation
● Robotics
● Educational platforms (Arduino)

Exam Tip
“AVR is an 8-bit RISC microcontroller family with Harvard architecture, single-cycle execution, and rich
on-chip peripherals, making it suitable for high-performance and low-power embedded applications.”

2)AVR Microcontroller Architecture

The AVR microcontroller architecture is based on 8-bit RISC principles and uses Harvard architecture,
providing high performance, low power consumption, and efficient instruction execution. It is
designed to execute most instructions in a single clock cycle.
1. Architectural Overview
The AVR architecture consists of the following main blocks:
● CPU (Central Processing Unit)
● Program Memory (Flash)
● Data Memory (SRAM & EEPROM)
● I/O Ports
● On-chip Peripherals
 ● Interrupt System
● Clock and Power Management

2. AVR CPU Architecture

2.1 RISC Core
● 8-bit RISC processor
● Most instructions execute in one clock cycle
Achieves up to 1 MIPS per MHz(The processor can execute 1 million instructions per second (MIPS)
for each 1 MHz of clock frequency.)
Example
● At 8 MHz clock speed ≈ 8 MIPS
● At 16 MHz clock speed ≈ 16 MIPS

2.2 Register File

● 32 general-purpose registers: R0 – R31
● Each register is 8-bit
● Registers are directly connected to the ALU
● Allows fast data access without memory delay
Key advantage: Two registers can be accessed in one instruction

2.3 Arithmetic Logic Unit (ALU)

● Performs arithmetic and logical operations
● Directly connected to register file
● Supports operations like add, subtract, AND, OR, shift, compare

2.4 Status Register (SREG)

The Status Register contains 8 flags:

B Na
it me Flag Function

Enables/disables all
7 I Global Interrupt Enable interrupts
 Used in bit copy
6 T Bit Copy Storage instructions

5 H Half Carry Carry from bit 3 to bit 4

4 S Sign N ! V

Two’s Complement
3 V Overflow Signed overflow

2 N Negative Result MSB = 1

1 Z Zero Result is zero

0 C Carry Carry/borrow from MSB

3. Program Memory (Flash)

● Non-volatile Flash memory
● Stores program instructions
● Organized in words (16-bit)
● Supports In-System Programming (ISP)
In-System Programmable (ISP) means the microcontroller’s program memory (Flash) can be
programmed or reprogrammed while the chip is already mounted in the system, without
removing it from the circuit.

● Separate from data memory (Harvard architecture)

4. Data Memory Organization

AVR data memory consists of three parts:
4.1 Register File
● First 32 locations
● Fastest access
4.2 I/O Memory
● Controls peripherals and I/O
● Accessed using IN and OUT instructions
4.3 SRAM
● Stores variables and stack
● Stack grows downward
● Stack pointer stored in SP register
5. EEPROM
● Non-volatile data memory
● Used to store permanent data
● Separate address space
● Slower than SRAM

6. I/O Ports
● Each port has three registers:
o DDRx – Data Direction Register
o PORTx – Output register
o PINx – Input pins register

7. Interrupt System
● Vectored interrupts
● Each interrupt has a fixed vector address
● Global interrupt controlled by I-bit in SREG
● Fast response due to separate interrupt vectors

8. Clock System
● Internal RC oscillator
● External crystal/resonator
● External clock source
● Supports clock prescaling

9. Power Management
● Idle mode
● Power-down mode
● Power-save mode
● Standby modes

10. On-Chip Peripherals

● Timers/Counters
● PWM
● ADC (10-bit)
 ● USART
● SPI
● I²C (TWI)
● Watchdog Timer
● Analog Comparator

11. AVR Architectural Advantages

● High-speed execution
● Low power consumption
● Efficient interrupt handling
● Simple and clean architecture
● Ideal for real-time embedded systems

Exam-Ready Conclusion
The AVR microcontroller uses an 8-bit RISC Harvard architecture with 32 general-purpose registers,
separate program and data memories, single-cycle instruction execution, and rich on-chip peripherals,
making it highly efficient for embedded applications.

2)AVR Microcontroller Block Diagram – Point-wise Explanation

The block diagram of the AVR microcontroller represents the internal functional units and shows how high-
speed operation is achieved using RISC and Harvard architecture.

1. CPU (Central Processing Unit)

● 8-bit RISC core
● Executes most instructions in one clock cycle
● Controls all internal operations of the microcontroller

2. Register File
● 32 × 8-bit general-purpose registers (R0–R31)
● Directly connected to the ALU
● Enables fast data transfer without accessing memory

3. Arithmetic Logic Unit (ALU)

● Performs arithmetic and logical operations
● Supports add, subtract, AND, OR, shift, compare
● Works directly with register operands

4. Status Register (SREG)

 ● 8-bit flag register
● Stores result of ALU operations
● Controls global interrupt enable

5. Program Counter (PC)

● Holds address of the next instruction
● Automatically increments after instruction fetch
● Updated during branching, jumping, and interrupts

6. Program Memory (Flash)

● Non-volatile memory
● Stores program instructions
● Organized as 16-bit words
● Separate from data memory (Harvard architecture)

7. Instruction Register & Decoder

● Fetches instruction from program memory
● Decodes instruction
● Generates control signals for execution

8. Data Memory
AVR data memory consists of:

(a) Register File

● First 32 locations
● Fastest access
(b) I/O Memory
 ● Used to control peripherals
● Accessed using IN and OUT instructions
(c) SRAM
● Stores variables and stack
● Stack pointer controls stack operations

9. EEPROM
● Non-volatile data storage
● Retains data after power OFF
● Used for storing calibration and user data

10. I/O Ports

● Used for interfacing external devices
● Each port has:
o DDRx (direction control)
o PORTx (output)
o PINx (input)

11. Interrupt Unit

● Handles external and internal interrupts
● Vectored interrupts with fixed addresses
● Fast interrupt response

12. Timers/Counters
● Used for delay generation
● Event counting
● PWM generation

13. ADC (Analog to Digital Converter)

● Converts analog signals to digital values
● Typically 10-bit resolution
● Used for sensor interfacing

14. Serial Communication Interfaces

● USART – Serial communication
● SPI – High-speed data transfer
 ● I²C (TWI) – Two-wire communication

15. Watchdog Timer

Watchdog Timer is a hardware timer that resets the microcontroller when the program
fails to respond within a preset time.
● Resets system during software failure
● Improves system reliability

16. Clock & Reset Unit

● Provides clock to all blocks
● Supports internal and external clock sources
● Handles system reset

17. Power Management Unit

● Controls power-saving modes
● Reduces power consumption
● Ideal for battery-based applications

Exam-Friendly Closing Line

The AVR block diagram consists of a high-speed RISC CPU, separate program and data memories, rich peripherals,
and efficient interrupt and power management units, making it suitable for real-time embedded systems.

3)AVR Registers
In AVR microcontrollers, registers play a key role in high-speed execution. The AVR architecture
provides a large register set directly connected to the ALU, which minimizes memory access and
improves performance.
1. General Purpose Registers (GPRs)
● AVR has 32 general-purpose 8-bit registers
● Named R0 to R31
● All registers are directly connected to the ALU
● Support single-cycle execution
Key Points:
● Any two registers can be used as operands
● Result is stored in one of the registers
● Faster than memory-based architectures

2. Pointer Registers
Three 16-bit pointer registers are formed using GPR pairs:
Point Registe
er rs Purpose

R27:R2
X 6 Data memory addressing
 R29:R2
Y 8 Data memory + offset
Features:
● Used for indirect addressing
● Support pre-decrement and post-increment modes
● Z pointer is also used for program memory access (LPM( Load Program Memory) instruction)

3. Program Counter (PC)

● Holds the address of the next instruction
● Automatically increments after instruction fetch
● Size depends on Flash memory size
● Modified during jump, call, return, and interrupt operations

4. Stack Pointer (SP)

● Points to the top of the stack in SRAM
● Stack grows downward
● Used during:
o Subroutine calls
o Interrupt handling
● Implemented using two registers (SPH and SPL)

5. Status Register (SREG)

The Status Register contains 8 status flags:
B Fl
it ag Description

Global Interrupt
7 I Enable
6 T Bit Copy Storage
5 H Half Carry
4 S Sign Flag
3 V Overflow Flag
2 N Negative Flag
1 Z Zero Flag
0 C Carry Flag

6. I/O Registers
 ● Control on-chip peripherals
● Located in I/O memory space
● Accessed using IN and OUT instructions
Examples:
● PORTx, DDRx, PINx
● TCCR, TCNT, OCR
● ADMUX, ADCSRA

7. Special Function Registers (SFRs)

● Registers used to control CPU and peripherals
● Include:
o SREG
o SPH, SPL
o MCU control registers
● Provide configuration and status information
Peripher
al SFRs Function

Direction, output,
I/O Ports DDRx, PORTx, PINx input
ALU flags &
Status SREG interrupts
Timer control &
Timers TCCR, TCNT, OCR count
ADC ADMUX, ADCSRA ADC control
Serial
USART UDR, UCSRA/B/C communication
SPI SPCR, SPSR, SPDR SPI control & data
TWBR, TWSR,
TWI TWDR I²C control

Watchdo System reset

g WDTCR control

8. EEPROM Registers
● Used to control EEPROM read/write
● Include:
o EEAR (EEPROM Address Register)
 o EEDR (EEPROM Data Register)
o EECR (EEPROM Control Register)

9. Register Advantages in AVR

● Large register file reduces memory access
● Direct ALU connection improves speed
● Efficient support for high-level languages (C)

Exam-Ready Conclusion
The AVR microcontroller provides 32 general-purpose registers, pointer registers, and special function
registers directly connected to the ALU, resulting in high-speed execution and efficient program control.

4)AVR Status Register

The Status Register (SREG) is an 8-bit special function register in the AVR microcontroller. It stores the
status of ALU operations and controls interrupt handling.

Bit-wise Explanation
Bit 7 – I (Global Interrupt Enable)
● Enables/disables all interrupts
● I=1 Interrupts enabled
● I=0 Interrupts disabled

Bit 6 – T (Bit Copy Storage)

● Used by BST and BLD instructions
● Temporary storage for bit transfer operations

Bit 5 – H (Half Carry Flag)

● Set if there is a carry from bit 3 to bit 4
● Used in BCD arithmetic

Bit 4 – S (Sign Flag)

● Indicates signed result
● S = N ! V (XOR of Negative and Overflow flags)

Bit 3 – V (Overflow Flag)

● Set if signed overflow occurs
 ● Indicates incorrect signed arithmetic result

Bit 2 – N (Negative Flag)

● Set if MSB of result is 1
● Indicates negative result (signed arithmetic)

Bit 1 – Z (Zero Flag)

● Set if the result of an operation is 0
● Used for conditional branching

Bit 0 – C (Carry Flag)

● Set if carry is generated from MSB
● Used in unsigned arithmetic and shifts

Key Points (Exam-Oriented)

● Updated automatically after ALU operations
● Used in conditional branch instructions
● Controls interrupt enabling
● Essential for decision making in program.
● One-Line Exam Answer
The AVR Status Register (SREG) is an 8-bit register that stores ALU status flags and controls global
interrupt enabling.

5)ROM Space and Other Hardware Modules in AVR

In AVR microcontrollers, the on-chip ROM space (Flash memory) and hardware modules are designed to
support high-speed, low-power embedded applications. Mazidi & Naimi explain these in terms of memory
organization and on-chip peripherals.
1. ROM Space (Program Memory – Flash)
Key Features
● Non-volatile Flash memory
● Stores program instructions
● Based on Harvard architecture (separate from data memory)
● Organized in 16-bit words
● Supports In-System Programming (ISP)

Program Memory Organization

● Program memory size depends on AVR device

(e.g., ATmega32 32 KB Flash)

● Addressed by Program Counter (PC)
● Supports Read-While-Write (RWW) operation in many devices
Special Instructions
● LPM (Load Program Memory)

Used to read program memory using Z pointer

● SPM (Store Program Memory)

Used for self-programming (bootloader)

Boot Loader Section

● Upper part of Flash can be reserved as Boot Loader
● Allows:
o Program updates without external programmer
o Serial/USB programming

2. Other Hardware Modules (On-Chip Peripherals)

2.1 I/O Ports
● Used for external device interfacing
● Each port has:
o DDRx – Direction control
o PORTx – Output register
o PINx – Input register

2.2 Timers/Counters
● Used for:
o Delay generation
o Event counting
o PWM generation
● Types:
o 8-bit Timer
o 16-bit Timer

2.3 Watchdog Timer (WDT)

● Resets MCU during software malfunction
● Improves system reliability
● Can operate independently of system clock

2.4 ADC (Analog to Digital Converter)

● Typically 10-bit resolution
 ● Multiple input channels
● Used for sensor interfacing

2.5 Analog Comparator

● Compares two analog voltages
● Used in:
o Zero-cross detection
o Threshold detection

2.6 Serial Communication Modules

(a) USART
● Full-duplex serial communication
● Supports synchronous and asynchronous modes
(b) SPI
● High-speed serial communication
● Master–Slave architecture
(c) I²C (TWI)
● Two-wire interface
● Supports multi-master systems

2.7 Interrupt System

● Vectored interrupts
● Fixed interrupt addresses
● Fast interrupt response

2.8 Clock System

● Internal RC oscillator
● External crystal/resonator
● External clock source
● Prescaler for frequency division

2.9 Power Management Unit

● Multiple sleep modes:
o Idle
o Power-down
o Power-save
 ● Reduces power consumption

3. Summary Table (Exam-Friendly)

Feature Description

Flash memory for program

ROM Space storage

Boot Loader Self-programming support

Timers Delay, counting, PWM

ADC Analog signal conversion

Communicati
on USART, SPI, I²C

WDT System safety

Power Mgmt Low-power operation

Exam-Ready Conclusion
The AVR microcontroller provides on-chip Flash ROM for program storage and a rich set of hardware modules such
as timers, ADC, communication interfaces, watchdog timer, and power management units, making it highly suitable
for embedded system applications.

6)ATmega32 Pin Configuration & Functions

(As per Mazidi & Naimi – AVR Microcontroller and Embedded Systems)
The ATmega32 is a 40-pin, 8-bit AVR microcontroller. Its pins are grouped into four 8-bit ports along
with power, clock, reset, and special function pins.
1. ATmega32 Pin Groups (40-Pin DIP)
Catego
ry Pins

Port A PA0 – PA7

Port B PB0 – PB7
Port C PC0 – PC7
Port D PD0 – PD7
Power VCC, GND, AVCC
Clock XTAL1, XTAL2
Control RESET
Referen
ce AREF

2. Port-wise Pin Functions

 PORT A (PA0 – PA7)
Dual Function: Digital I/O + ADC Inputs
Pi
n Function

PA ADC0 / Digital
0 I/O
PA ADC1 / Digital
1 I/O
PA ADC2 / Digital
2 I/O
PA ADC3 / Digital
3 I/O
PA ADC4 / Digital
4 I/O
PA ADC5 / Digital
5 I/O
PA ADC6 / Digital
6 I/O
PA ADC7 / Digital
7 I/O
Key Point:
● Connected to 10-bit ADC
● Used for analog sensor interfacing

PORT B (PB0 – PB7)

Digital I/O + Timer & SPI Functions
Pi
n Alternate Function

P
B T0 (Timer0 External
0 Input)

P
B T1 (Timer1 External
1 Input)

P
B INT2 (External
2 Interrupt)

P
B OC0 / MOSI
3
P
B
4 SS (SPI Slave Select)
P
B MOSI (SPI)
5
P
B MISO (SPI)
6
P
B SCK (SPI Clock)
7
Key Point:
● Used for SPI communication
● Timer and interrupt support

PORT C (PC0 – PC7)

Digital I/O + JTAG Interface
Pin Function
PC0 –
PC5 Digital I/O

PC2 –
PC5 JTAG Interface

TOSC1 (Timer
PC6 Oscillator)
TOSC2 (Timer
PC7 Oscillator)
Key Point:
● JTAG used for debugging and programming(JTAG is a hardware interface used for testing,
debugging, and programming microcontrollers without removing them from the circuit.)
● Timer oscillator support

PORT D (PD0 – PD7)

Digital I/O + Communication & Interrupts
Pi
n Alternate Function

P
D RXD (USART Receive)
0
P TXD (USART
D
1 Transmit)
P
D INT0 (External
2 Interrupt)

P
D INT1 (External
3 Interrupt)

P
D OC1B
4
P
D OC1A
5
P
D ICP1
6
P
D OC2
7
Key Point:
● Used for USART serial communication
● Supports external interrupts

3. Power & Control Pins

VCC
● Main digital supply voltage
GND
● Ground reference
AVCC
● Supply for ADC and Port A
● Must be connected even if ADC not used
AREF
● Analog reference voltage for ADC

4. Clock Pins
Pin Function
XTAL External oscillator
1 input
XTAL
2 Oscillator output
Used for:
● External crystal
● Resonator
● External clock source

5. RESET Pin
● Active-LOW reset
● Resets MCU and "starts execution from address 0"
● Used during programming and fault recovery

6. Special Features Summary

● 40 programmable I/O pins
● 10-bit ADC (8 channels)
● SPI, USART communication
● External interrupts
● Timers & PWM
● JTAG support

Exam-Ready Conclusion
ATmega32 is a 40-pin AVR microcontroller with four 8-bit I/O ports, ADC channels, serial
communication interfaces, timers, interrupts, and dedicated clock and control pins, making it suitable
for embedded control applications.
AVR Architecture – One-Page Exam-Ready Note(exam)
Introduction
The AVR microcontroller is an 8-bit RISC-based microcontroller developed by Atmel. It follows Harvard
architecture, where program memory and data memory are separate, allowing faster instruction execution.
AVR controllers are widely used in embedded and real-time applications.

Salient Features
● 8-bit RISC architecture
● Harvard architecture
● 32 × 8-bit general-purpose registers
● 1 MIPS per MHz throughput
● Two-stage instruction pipeline (Fetch + Execute)
● Most instructions execute in single clock cycle
● Low power consumption
AVR Architecture – Block Description

1. CPU Core
The CPU core consists of the Arithmetic Logic Unit (ALU), Instruction Decoder, and Control Unit. Due to
pipelining, one instruction is executed while the next is fetched, improving speed.
2. Register File
AVR has 32 general-purpose working registers (R0–R31) directly connected to the ALU. This reduces
memory access time and enables fast instruction execution.

Registers X (R26–R27), Y (R28–R29), and Z (R30–R31) act as 16-bit pointer registers.

3. Program Memory
Program instructions are stored in Flash memory. AVR supports In-System Programming (ISP), allowing
program updates without removing the chip.
4. Data Memory
Data memory consists of:
● Register file
● I/O registers
● Internal SRAM

Additionally, EEPROM is used for non-volatile data storage.

5. AVR Status Register (SREG)
SREG is an 8-bit register used to store the status of ALU operations.

Flags: C, Z, N, V, S, H, T, I.

It is used for conditional branching and interrupt control.

6. I/O Ports
AVR provides programmable I/O ports (PORTA–PORTD). Each port uses DDR, PORT, and PIN registers for
direction control and data transfer.
7. Interrupt System
AVR supports vectored interrupts, providing fast and efficient interrupt handling.

Conclusion
Due to its RISC design, pipelining, and Harvard architecture, the AVR microcontroller achieves high
performance (1 MIPS/MHz) with low power consumption, making it suitable for embedded control
applications.

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