Microprocessor and It’s Applications 1

Microprocessor and It’s Applications – RCCS10CS7

Unit I

Evolution of Microprocessors-Single chip Microcomputers-Memory-Buses-

Memory Address capacity of CPU-Microcomputer-Processing Architecture-Intel

8085-Instruction Cycle

Unit II

Instruction set of Intel 8085-Instruction and Data Formats-Addressing

Modes-Status Flags-Intel 8085 Instructions-Programming of Microprocessors-

Assembles-Stacks and Subroutines-Macros and Micro Programming.

Unit III

Assembly Language programming-Simple Examples-Addition and

Subtraction of Binary and Decimal Numbers-Complements-Shift-Masking-Finding

max and Min number in an array-Arranging a series of numbers-Multiplication-

Division-Multiyear addition and subtraction.

Unit IV

Peripheral devices and interfacing-Address space partitioning-Memory and

I/O interfacing-Data Transfer schemes-Interrupts of Intel 8085-Interfacing Devices

and I/O Devices-I/O ports-Programming peripheral interfaces.

Unit V

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 2

Microprocessor Applications-Delay subroutine-Interfacing of 7 segment LED

Displays-Frequently measurement-Temperature and control-Water level indicator-

Microprocessor based traffic control.

Text Book:

Fundamentals of Microprocessors and Microcomputers- Badri Ram- Fifth revised

and enlarged Edition- Dhanpat Rai Publications-2001.

Reference Book:

Microprocessor Architecture programming and applications with the 8085/8080A-

Romesh [Link]- Penram international Publishers India 1997.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 3

INTRODUCTION

Introduction:

The Term LSI refers to IC’s containing components usually transistors in the range of 1000–

10,000. A VLSI chip contains more than 10,000 transistors. A CPU built into a single LSI or VLSI

chip is called a Microprocessor. A microprocessor combined with memory and input/output devices

forms a microcomputer.

A digital computer understands information’s composed of only zeros and ones. It uses binary

numbers for its operation. There are only two digits 0 and 1 in the binary number system. therefore,

instructions and data fed to the CPU of a digital computer must be in terms of 0s and 1s. a binary digit

is known as a bit. The word ‘bit’ is the short form of the term ‘binary bit’. A group of 8 bit is called a

byte.

1.1 Evolution of Microprocessor:

The first microprocessor was introduced in 1971 by Intel corporation, U.S.A. it was a 4-bit

microprocessor, in Intel 4004. in 1972 Intel introduced the 1 st 8-bit microprocessor, the Intel 8008. the

Intel 4004 and 8008 both used PMOS technology. In 1973 a more powerful and faster 8-bit

microprocessor, the Intel 8080 was introduced. It employed NMOS technology.

A 4-bit microprocessor means that the processor makes processing of 4 bits in parallel at a

time. If there are data containing more than 4 bits, the microprocessor will take up 4 bits of the data for

processing first, then the next group of 4 bits and so on. Similarly an 8-bit microprocessor handles 8

bits of data in parallel at a time.

Example of 8-bit microprocessors are Intel 8085, Motorola’s MC6809,Zilog’s Z80 and Z800.

16-bit microprocessor are Intel’s 8086, 80816 and 80286, Motorola’s MC 68000, Zilog’s Z8000 series.

32 bit microprocessor are Intel’s 80386, 80486, Motorola’s 68030 and 68040.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 4

The number of bits that a digital computer can process in parallel at a time is called its word

length. It is a measure of computing power of a computer. A 4-bit microcomputer has a word length of

4 bits. Microcomputer have word lengths of 4 – 32 bits whereas large computer 32-64 bits.

4-bit microprocessors are used for simple applications such as domestic appliance control,

calculators, video games, toys etc. 16-bit microprocessor have more powerful instructions set than that

of 8-bit microprocessor. They use VLSI technology. They can directly address memory in the range of

1M bytes to 16M bytes. 16-bit microprocessor are designed to work in multiprocessor environment

and use high-level language. Some 16-bit microprocessors, contain additional circuits besides CPU.

Intel 80386 is a 32-bit microprocessor introduced in 1985. it can directly address up to 4 GB of

memory. Intel 80486 is the latest 32-bit advanced microprocessor. It is more powerful than 80386. it

contain a CPU, a floating point coprocessor, memory management unit and 8 KB cache memory on

the chip itself.

Motorola’s 68030 is a 32-bit microprocessor introduced in 1987. it can directly address up to 4

GB memory. It contain a CPU, memory management unit, a 256 bytes of instruction cache and a 256

bytes of data cache. Motorola 68040 is more powerful 32-bit microprocessor. It contains a CPU,

memory management unit, a powerful floating point coprocessor. Motorola MC88100 is a 32-bit RISC

processor.

1.2 Evolution of Digital Computer:

First mechanical machine capable of automatically performing arithmetic operations appeared

in 1623 but it was not popular. In 1642 Blaise Pascal made a mechanical adding machine. It performed

addition and subtraction automatically. In 1671 Gottfried Leibriz made a machine which was able to

perform multiplication and division automatically. These machines performed computation in single

steps. In 1823, Charles Babbage made a multi-step mechanical computer.

The first electronic digital computer ENIAC was built in 1946. it used electronic valves as its

main components. The digital computers using electronic valves are known as first generation

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 5

computers. Examples of first generation computers are: ADVAC, IBM 701, IBM 704, IBM 709,

UNIVAC I etc.

The Second Generation computers (1955-1964) used transistors instead of vacuum tubes as

CPU components and ferrite cores of main memory. Examples of second generation computers are:

IBM 1620, IBM 7090, IBM 7094, CDC 1604, PDP 5 etc. Second generation computers used high-

level languages like FORTRAN, ALGOL, COBOL, etc.

Third generation computers used IC’s instead of transistors. ICs were also used for main

memory. Multiprocessing, multiprogramming, pipelining technique were used in these computers.

Examples of third generation computers are: IBM 370, CDC 7600, PDP-11 series, Cyber-175, STAR

100, etc.

Fourth generation computers used Microprocessor. Computers available today are fourth

generation computers. Example are CRAY Y-MPC(1992), CRAY Y-MP(1988), CRAY 2(1985), IBM

ES(1900), IBM 3090/600(1988), VAX 9000/420, VAX 8842 (1988), IBM AS/400/B60 (1988), IBM

PS/2/50 (1987), IBM PS/2 model 80, WIPRO LANDMARK 860, HCL-Magnum 040 series, HP 9000,

HP 9000 model 870S/400, HP 9000 model 870/300, etc.

Fifth generation computers are in research and development stage. U.S.A. and Japan have

projects to develop fifth generation computers. These computers will use ULSI chips which contain

millions of computers on a single chip.

1.3 Single Chip Microcomputer:

Microcomputer containing CPU, RAM, ROM and I/O ports on a single chip have been

developed. Such microcomputers are also known as Microcontrollers.

Examples of single chip microcomputers are the Intel 8048 and 8051 series, Motorola’s M6801

series, Texas instruments TMS 1000 and Zilog’s Z8.

Most of the microcomputers are 8-bit microcomputers. The Intel 8051 is the latest single chip

8-bit microcomputer which has very powerful instruction set and operates with 12 MHz clock.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 6

Intel 8096 series of microcomputers are 16-bit single chip microcomputers. The 8096 contains

a 16-bit CPU, 8K ROM, 232 bytes RAM, Timer/counter, 10-bit A/D converter, I/O ports etc.

1.4 Digital Computer:

A digital computer is a programmable machine specially designed for making computation. It

main components are: CPU (central Processing Unit), memory, input device and output device as

shown in figure 1.1. a microcomputer is a small digital computer.

The CPU of microcomputer is a microprocessor. The organization of a microcomputer is

shown in figure 1.2. The physical and circuitry of a computer are called Hardware. A physical device

may be electronic, magnetic, mechanical or optical device etc.

A sequence of instructions to perform a particular task is called a Program. A set of programs

written for a particular computer known as Software for that computer. The input and output devices

are known as peripherals. Peripheral includes memory, ROM, PROM, EPROM EEPROM’s are

known as firmware.

a) CPU: The Central processing Unit(CPU) fetches from the memory and performs specified tasks. It

store results in the memory or sends results to the output device. The CPU controls and communicate s

with memory and input/output device.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 7

Major sections of a CPU are:

i. ALU(Arithmetic Logic Unit): The function of an ALU is to perform arithmetic operations

such as addition and subtraction; and logical operations such as AND, OR and

EXCLUSIVE-OR.

ii. Timing & Control Unit: This unit controls the entire operation of a computer. It act as a

brain. it also controls all other devices connected to CPU. It generates timing signals

necessary for input and output devices.

iii. Accumulator & General purpose Register: the accumulator is a register which contains one

of the operands and store results of most arithmetic & logic operations.

iv. General purpose register are used for temporary storage of data and intermediate results

while computer is making execution of a program.

b) Microprocessor: The LSI and VLSI technology it became possible to build the entire CPU on a

single chip IC. A CPU built into a single LSI/VLSI chip is called a microprocessor. The main section

of a microprocessor are: ALU, timing & control unit, accumulator, general purpose and special

purpose register.

c) Memory: The memory is a storage device. It store program, data, results etc.

d) Input device: The computer receives data and instructions through input devices. An input devices

converts the instructions, input data and signal into proper binary form suitable for a digital computer.

A key board and simple switches are used as input devices.

e) Output device: The computer sends results to output devices. An output device may store, print,

display or send electrical signal to control. The example of simple output devices are printers, CRT,

LED’s, D/A converter, controllers, actuator etc.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 8

1.5 Memory:

The function of memories is to store program, data and results. There are two kinds of

memories: semiconductor memories and magnetic memories. Semiconductor memories are faster,

smaller, lighter and consume less power. Semiconductor memories are used as the main memory of a

computer. Magnetic memories are slow but they are cheaper than semiconductor memories. Magnetic

memories are used as the secondary memories of a computer for bulk of data and information’s.

a) Semiconductor memories: there are two important types of semiconductor memories: RAM

(Random Access Memory) and ROM (Read Only Memory). There are various types of RAM

and ROM.

b) RAM: The read and write memory of a computer is popularly known as RAM. It is also called

R/W memory. Information can be read from and written into it during normal operation. It has

random access property. The abbreviation RAM stands for random access memory. In a

random access memory any memory location can be accessed in a random fashion without

regard to any other location..

c) iRAM: iRAM stands for integrated RAM. iRAM integrates dynamic RAM and it’s control and

refresh circuitry into a single IC.

d) ROM: A ROM is a read only memory. It is non-volatile. It is used for permanent storage. It

has also a random access property. It contain assembler, compiler, monitor, debugging program

or any other permanent program. ROMs are widely used for function tables (sine, cosine,

square root, logarithm, exponentials etc)

e) PROM: A PROM is a programmable ROM. The content of a PROM is decided by the user.

The user can write permanent program in a PROM. A special equipment for PROM

programming is called PROM programmer

f) EPROM: An EPROM is an erasable PROM. The contents are erased by exposing EPROM to

high intensity intensity short wave ultraviolet light for 10 to 20 minutes. EPROMs are cheap,

reliable and widely available.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 9

g) EEPROM: EEPROMs are electrically erasable PROM, they need not be removed from a

microcomputer board erasing. The change in contents is made in milliseconds which is much

less than the erasing time of an EPROM. A single byte of data or the entire device can be

erased in about 10ms.

h) Magnetic Memories: Magnetic memories are slower, they are used in computer system for

bulk storage. The important memories are: magnetic tape, floppy disk, hard disk and magnetic

bubble type memories. All of these memories except magnetic bubble type memory have

rotating mechanical parts. Magnetic tapes, floppy disks and hard disks are used as mass

storage(bulk memory). Mass storage devices are used to store information at a lower cost per

bit.

i) Magnetic Tape Storage: Magnetic tapes are used for bulk storage. Tapes are cheaper than

other magnetic storage devices. The tape is usually made of Mylar with a thin coating of

magnetic iron oxide. It’s width varies from ¼ inch to ½ inch. Narrow tapes contain one or more

tracks and data words are stored in serial from on a single track. Large commercial recorders

use wide tapes.

On wide tapes data words are stored in parallel form on parallel tracks. Tape is a surface

device. It is slow being serial access type memory. Sometime locating a file takes several

seconds. Once a file is located some parallel track recorders can read about 2,50,000 character

per second. Magnetic tapes are used as backup storage. Floppy disks are used as backup

storage. The difficulty with floppy disk is that a large number of floppy disks is required.

j) Floppy Disks: Floppy disk is Mylar disk coated with magnetic material iron oxide. 0 and 1 are

stored in the magnetic material in the form of magnetic directions. Floppy disks have shorter

access time than magnetic tapes. Disk is rotated at a constant speed of 360 r.p.m. the floppy

disk surface is divided into a number of tracks. Each tracks is further divided into a number of

sectors. There is a hole at the centre for driving the disk. A write protect notch is provided to

protect stored information. Each track and sector has a binary address using which the

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 10

processor can read/write information. The transfer of data from or to a track is done in serial

mode. Access of a track is done in a random fashion. The transfer of data or to a

k) Hard Disks: A hard disk uses a rigid aluminium base with a thin coating magnetic material.

The disk is enclosed in a sealed container. To increase the storage capacity per drive several

disks can be attached to a common spindle to form a disk pack. An individual read/write head

for each disk is used. Standard hard disk sizes are:3 1/2 and 51/4 inch diameter. The speed of a

hard disk is in range of 1000 to 3600 r.p.m. the disk drive for a hard disk is known as

Winchester drive.

l) Optical Disk: Optical disks are used to store huge amount of data for computers. 1 Gbytes of

data can be stored on one side of a 12 inch optical disk, this storing capacity corresponds to

about 400,000 pages of text. There are three types of optical disks: read only, write once/read,

and read/write.

1.6 Buses:

Various input/output devices and memories are connected to the CPU by a group of lines called

a Bus. There are three types of buses: Address bus, Data bus and Control bus. The bus architecture of a

microcomputer has been shown in [Link] Address bus carries the address of a memory location

or I/O device that a CPU has to access. The address bus is unidirectional. Data and control buses are

bidirectional. A Data bus is used for the transfer of data between the processor and memory or I/O

devices. The Control bus is used to carry control signals between CPU and various devices connected

to it.

The address bus of an 8-bit microprocessor is usually 16-bit wide. A 16-bit wide address bus

can directly access 64K bytes of memory.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 11

1.7 Memory Address Capacity of CPU:

The memory addressing capacity of a CPU depends on the width of it’s address bus. If a CPU

has n-bit wide address bus, it can directly address 2n memory locations. For example, a CPU having a

16-bit wide address bus can directly address up to 2 16=64K memory locations. One memory location

store 1 byte of information. Therefore, a CPU having a 16-bit wide address can directly address 64K

bytes of memory.

Suppose, There are only 2 lines in an address bus. The only possible addresses for memory

locations are: 00,01,10,11. these are equal to 4=2 2. if an address bus has 3 lines, it can address memory

locations having address: 000,001,010,011,100,101,110,111. these are 8=23 address.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 12

1.8 Large & Small Computers:

Digital Computers are classified into four categories:

i. Microcomputer, ii. Minicomputer, iii. Mainframe computer, [Link].

i) Microcomputer: Low-cost small digital computers are known as microcomputers. The two word

length of a microcomputer may be 8-bit, 16-bit or 32-bit. Microcomputers are widely used in industrial

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 13

control, instrumentation, general purpose computation, home appliances, commercial appliances,

office automation, automobiles and so on.

Personal Computers: Microcomputers designed for general purpose computation and

manipulation work are called personal computer. Personal computer are classified into PC, PC/XT,

PC/AT and super AT. All categories of personal computers contain a CPU, memory(RAM and ROM),

secondary memory (hard disk/floppy disk), CRT display, and a keyboard, printer is optional.

PC (Personal computer). These are simplest and cheapest personal computers. They are use

Intel 8088 CPU, 640 KB memory, floppy disk drives, CRT display and keyboard. The operating

system is MS-DOS. PCs do not contain hard disks. They contain two floppy disk drives, the capacity

of ROM is 8 KB. Clock speed is 10 MHZ.

PC/XT (Personal Computer Extended Technology). It is similar to PC except that it contain

hard disks. It’s ROM capacity is of 8 KB, expandable up to 48 KB. Clock speed is 10 MHZ. the hard

disk capacity is usually 20 MB/ 40 MB. Operating system is MS-DOS. The CPU 8088 can directly

address up to 1 MB memory.

PC/AT (Personal Computer Advanced Technology). It’s CPU is more powerful, Intel

80286. it can directly address up to 16 MB memory. It is a 16-bit CPU. It data bit is 1-bit wide. It has

been designed for multiuser and multitasking environment. It can support 4 terminals. It’s clock is

12MHZ. the memory capacity of PC/AT is 640 KB or 1 MB expandable to 9 MB. The hard disk

capacity is 20MB/40MB/80MB.

Super AT. Super ATs use 32-bit CPU Intel 80386 or Intel 80486. their clock speed may be 20

MHZ, 25 MHZ. the memory capacity is 2 MB expandable to 16 MB. The hard disk capacity is 80

MB/200 MB. Operating system is MS-DOS and UNIX.

Video monitor(display) units have 14 inch screen size. The display may be MGA/CGA, CGA

or VGA high resolution type. MGA is monochrome(single color) graphics adaptor, CGA is color

graphics adaptor and VGA is video graphics adaptor.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 14

Home Computers: These are very small computers, they are used in home appliances, simple

computation, entertainment, basic education and home management, etc.

ii) Minicomputers: Minicomputers are more powerful, faster and costlier than microcomputer. Their

word length is 32-bit. Motorola 68030 and Intel 80486 are used as CPU. Their processing speed may

lie in the range of 10-30 MIPs. Their RAM capacity lies in the range of 8MB-96MB. The hard

capacity is 380 MB- 3 GB. They are used in industry, government organizations, universities, research

organizations etc.

Examples of minicomputers are: IBM AS/400/B60; VAX 8842, WIPRO S-68030, Motorola

68030 CPU, WIPRO GENIUS, WIPRO LANDMARK 860, HP 9000 series,

iii) Mainframe Computers(or Large Computers): Mainframe computers are more powerful, faster

and costlier than minicomputers. Their processing speed lies in the range of 30 – 100 MIPS. Their

word length may be 48, 60 or 64 bit. Their RAM capacity lies in the range of 64 MB - 256 MB, hard

disk capacity 1000 MB – 10 GB. Mainframe computers are used in complex computation, to process

large amount of data. They are used in large industries, large business and government organizations,

research organizations, banks, airlines, places where large database is required and so on. Hundreds of

terminals(monitor) can be connected to a mainframe computer.

Example of mainframe computers are : IBM enterprise System/900 series, HP 9000 Model

870S/400, HP 9000 model 870S/300, IBM 4300 series, IBM 308X series, IBM 3090 series etc.

iv) Supercomputers: Supercomputers are more powerful, much faster and costlier than mainframe

computer. Their word length may be 64-bit or 96-bit, memory capacity 256 MB or more, hard disk

capacity 1000 MB or more, processing speed 400 MIPS – 10,000 MIPS. Supercomputers are used for

solving very sophisticated problems. They are used for weather forecasting, aerodynamics,

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 15

seismology, atomic, nuclear, plasma physics, for weapons research and development, sending rockets

into space, and so on.

Examples of supercomputers are : CRAY X-MP/14, X-MP/24 and X-MP/48, CRAY Y-MP.

CRAY Y-MPC, CRAY-3, ETA-10, SX-2 etc. CRAY-MPC contains 16 CPUs.

1.9 Intel 8085 Microprocessor Architecture:

Intel 8085 is an 8-bit microprocessor. It is a 40 pin I.C. package fabricated on a single LSI chip.

The Intel 8085 uses a single +5Vd.c. supply for it’s operation. Its clock speed is about 3 MHz. it has 80

basic instructions and 246 opcodes. Fig 3.1 shows the block diagram of Intel 8085. It consists of three

main sections, an Arithmetic and Logic unit, a Timing and Control unit and several registers.

ALU: The arithmetic and logic unit, ALU, perform the following arithmetic and logical operations.

i. Addition

ii. Subtraction

iii. Logical AND

iv. Logical OR

v. Logical EXCLUSIVE OR

vi. Complement ( logical NOT)

vii. Increment (add 1)

viii. Decrement (subtract 1)

ix. Left shift (add input to itself)

x. Clear

Timing & Control Unit: The Timing and control unit is a section of CPU. It generates timing and

control signals which are necessary for the execution of instructions. It control data flow between CPU

and peripherals. It control the entire operations of the microprocessor and peripheral connected to it.

Control unit of the CPU acts as the brain of the computer system.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 16

Registers: Fig. 3.1 shows the various registers of Intel 8085. registers are used by the microprocessor

for temporary storage and manipulation of data and instructions. In a large computer the number of

registers is more. In a small computer the number of registers is small due to limited size of the chip.

Intel 8085 microprocessor has the following registers.

i. One 8-bit Accumulator (ACC) i.e register A

ii. Six 8-bit general purpose registers. These are B,C,D,E,H and L.

iii. One 16-bit stack pointer, SP

iv. One 16-bit program counter, PC

v. Instruction register

vi. Status register

vii. Temporary register

Fig 3.1 shows the block diagram of Intel 8085. the program counter PC, contains the address of the

next instruction. The CPU fetches an instruction from the memory, execute it and increments the

content of the program counter. Next instruction cycle it will fetch the next instruction of the program.

The instruction register holds the instruction until it is decoded.

The stack pointer SP, holds the address of the stacktop. The stack is a sequence of memory

locations defined by the programmer. The stack is used to save the content of a register during the

execution of a program. The last memory location of the occupied portion of the stack is called

stacktop.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 17

There are six 8-bit registers which are used for general purpose as desired by the programmer.

These 8-bit registers are: A,B,C,D,E,H and L. to handle 16-bit data two 8-bit registers can be

combined. The combination of two 8-bit register is called register pair. The register pair of Intel 8085

are B-C, D-E and H-L. the H-L pair is used to address memories. The register A is accumulator in Intel

8080/8085. this is used during the execution of a program for temporary storage. The final result of an

arithmetic or logical operation is placed in the accumulator.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 18

There is a set of flip-flops which act as flags. Each of these flip-flops holds 1-bit flag that

indicates certain condition which arises during arithmetic and logic operations. The following status

flags have been provided in Intel 8085.

i) CAARY (CS) ii) ZERO (Z) iii) SIGN (S)

iv) PARITY (P) v) AUXILIARY CARRY (AC)

Carry (CS): The carry status flag holds carry out of the most significant bit resulting from the

execution of the an arithmetic operation. If there is a carry from addition or a borrow from the

subtraction or comparison, the carry flag CS is set to 1; otherwise 0.

Zero (Z): The Zero status flag is set to 1 if the result of the arithmetic or logical operation is zero. For

non-zero result it is set to 0.

Sign (S): The sign status flag is set to 1 if the most significant bit of the result of an arithmetic or

logical operation is 1, otherwise 0.

Parity (P): The parity status flag is set to 1 when the result of the operation contain even number of

1s. it is set to zero when there is odd number of 1’s.

Auxiliary carry (AC): The auxiliary carry status flag holds the carry out of bit 3 to 4 resulting from

the execution of an arithmetic operation.

Fig. 3.2 (a) shows the position of various status flags of Intel 8085.

Fig. 3.2 (b) shows the status flags for ADD operation.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 19

Example, the instruction ADD B. the execution of the instruction ADD B will add the content of the

register B to the content of the accumulator. The contents of the accumulator and register B are CB

and E9 respectively. Now CB and E9 are added and the result is 01, B4. As the accumulator is an 8-bit

register B4 remains in the accumulator and there is a carry. The various status flags are shown in fig.

3.2 (b).

PSW: In fig. 3.2 (a), five bits indicate the five status flags and three bits are undefined. The

combination of these 8-bit is called Program Status Word (PSW).

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 20

Data & Address Bus: The Intel 8085 is an 8-bit microprocessor. It data bus is 8-bit wide, 8 bit of data

can be transmitted in parallel form or to the microprocessor. The Intel 8085 requires a 16-bit wide

address but as the memory address are of 16 bits. The 8 most significant bits of the address are

transmitted by the address bus, A-bus (pins A8-A15). The 8 least significant bits of the address are

transmitted by address/data bus, AD-bus (pins AD 0 – AD7). The address/data bus transmits data and

address at different moments. At a particular moment it transmit either data or address. Thus the AD-

bus operates in time shared mode. This technique is known as multiplexing.

First of all 16-bit memory address is transmitted by the microprocessor; the 8MSBs of the

address on the A-bus and 8 LSBs of the address on AD-bus. Thus, the effective width of the address

bus becomes 16-bit wide. Each memory location contains 1 byte of data.

Pin Configuration:

Fig 3.3 shows the schematic diagram of Intel 8085. The description of various pins are as

follows:

A8-A15 (output): These are address bus and are used for the most significant bits of the memory

address or 8-bits of I/O address.

AD0-AD7 (input/output): These are time multiplexed address/data bus i.e. they serve dual purpose.

They are used for the least significant 8 bits of the memory address or I/O address during the first

clock cycle of a machine cycle. Again they are used for data during second and third clock cycles.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 21

ALE (output): It is an address latch enable signal. It goes high during first clock cycle of a machine

cycle and enables the lower 8 bits of the address to be latched either into the memory or external latch.

IO/M (output): It is a status signal which distinguishes whether the address is for memory or I/O.

when it goes high the address on the address bus is for I/O devices. When it goes low the address on

the address bus is for the memory.

S0, S1 (output): These are status signals sent by the microprocessor to distinguish the various types of

operation given in table 3.1

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 22

RD (output): It is a signal to control READ operation. When it goes low the selected memory or I/O

device is read.

WR (output): It is a signal to control WRITE operation. When it goes low the data on the data bus is

written into the selected memory or I/O location.

READY (input): It is used by the microprocessor to sense whether a peripheral is ready to transfer

data or not. If READY is high the peripheral is ready. If it is low the microprocessor waits till it goes

high.

HOLD (input): It indicates that another device is requesting the use of the address and data bus.

Having received a HOLD request the microprocessor relinquishes the use of the buses as soon as the

current machine cycle is completed. The processor regains the bus after the removal of the HOLD

signal. When a HOLD is acknowledged, address bus, data bus, RD, WR, and IO/M are tri-stated.

HLDA (output): It is a signal for acknowledgement. It indicates that the HOLD request has been

received. After the removal of the HOLD request the HLDA goes low. The CPU takes over the buses

half clock cycle after the HLDA goes low.

INTR (input): It is an interrupt request signal. Among interrupts it has the lowest priority. When it

goes high the program counter does not increment it’s content. After completing the instruction at hand

it goes to the CALL instruction. The microprocessor acknowledges the interrupt signal and issues an

INTA signal. The INTR is enabled or disabled by software. An interrupt is used by I/O devices to

transfer data to the microprocessor without wasting its time.

INTA (output): It is an interrupt acknowledgement sent by the microprocessor after INTR is received.

RST 5.5,6.5,7.5 & TRAP (input): These are interrupts. When an interrupt is recognized the next

instruction is executed from a fixed location in the memory as given below:

Line Location from next instruction is picked

TRAP 0024

RST 5.5 002C

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 23

RST 6.5 0034

RST 7.7 003C

RST 7.5, RST 6.5,RST 5.5 are the restart interrupts. They cause an internal restart to be automatically

inserted. Each of them programmable mask. The TRAP has the highest priority among Interrupts. The

order of priority of interrupts is as follows:

TRAP (highest priority)

RST 7.5

RST 6.5

RST 5.5

INTR (lowest priority)

RESET IN (input): It resets the program counter to zero. It also resets interrupt enable and HLDA

flip-flops. It does not affect nay other flag or register except the instruction register.

RESET OUT (output): It indicates that the CPU is being reset.

X1,X2 (input): These are terminals to be connected to an external crystal oscillator which drives an

internal circuitry of the microprocessor to produce a suitable clock for the operation of microprocessor.

CLK(output): It is a clock output for user, which can be used for other digital ICs. Its frequency is

same at which processor operates.

SID (input): It is data for serial input. The data on this line is loaded into the 7 th bit of the accumulator

when RIM instruction is executed.

SOD (output): It is a data line for serial output. The 7th bit of the accumulator is outputted on SOD

line when SIM instruction is executed.

Vcc - +5 Volts supply, Vss - ground reference

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 24

Intel 8085 Instruction:

A computer receives data from user, processes data and sends the result back to the user. An

instruction is a command given to the computer to perform a specified operation on given data.

MOV r1,r2 : The content of register r2 is moved to register r1.

Example, MOV A, B moves the content of register B to register A.

MOV M,r : The content of register r is moved to the memory location whose address is in H-L pair.

Example, MOV M, A will transfer the content of accumulator to the memory location specified by H-

L pair.

MVI r, data : The given just after an instruction are moved to the register r.

Example, MVI A, 05 moves 05 to register A.

LXI rp, data 16-bit : 16-bit immediate data are moved to the register pair rp.

Example, LXI H, 2400H moves 2400 to H-L pair

LDA addr : The content of memory location whose address is specified within the instruction itself is

moved to the accumulator.

Example, LDA 2400H moves the content of the memory location 2400H to the accumulator.

STA addr : The content of accumulator is moved to the memory location whose address is specified

within the instruction itself.

Example, STA 2500H moves the content of the accumulator to memory location 2500H.

ADD r : The content of the register r is added to the content of accumulator.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 25

Example, ADD B adds the content of B to the content of the accumulator and places the sum in the

accumulator.

SUB r : The content of the register r is subtracted from the content of accumulator and the result is

placed in the accumulator..

Example, SUB C subtract the content of register C from the content of the accumulator and places

the result in the accumulator.

RAL : The content of the accumulator is rotated left one bit through carry.

INR r: The content of register r is incremented by one.

IN Port-address : This instruction transfer data from input devices. The data available at the input

port is moved to the accumulator.

OUT Port-address: This instruction transfer data from processor to the output device. The content of

the accumulator is transferred to the output port.

Opcode and Operands:

Each instruction contains two parts: operation code (opcode) and operand. The first part of an

instruction which specifies the task to be performed by the computer is called opcode. The second part

of the instruction is the data to be operated on, and it is called operand.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 26

Instruction Word Size:

The machined code of all instructions are not of the same length, according to the word size the

Intel 8085 instructions are classified into the following three types.

i. One word or 1-byte instruction

ii. Two-word or 2-byte instruction

iii. Three-word or 3-byte instruction

One word or 1-byte instruction:

a. MOV A, B: Move the content of register B to register A. 78H is the opcode for MOV

A, B. the opcode 78H written in the binary form as 01111000. the 1 st two bits, i.e. 01 are

for MOV operation; next three bits 111 are the binary code for register A and last three bits

000 are the binary code for the register B.

b. ADD B: Add the content of register B to the content of the accumulator.80H is the opcode

for the instruction ADD B. the opcode 80H in the binary form is 10000000. the first five

bits, i.e, 10000 specify the operation to be performed i.e. ADD operation. The last three bits

000 are the code for register B.

c. RAL : Rotate the content of the accumulator left by one bit. The opcode for the RAL is

17H.

Two word or 2-byte instruction: In a two byte instruction the 1st byte of the instruction is it’s opcode

and 2nd byte is either data or address

a. MVI B, 05 : Move 05 to register B.

06, 05 ; MOV B, 05 in the code form

The 1st byte 06 is opcode for MVI B and 2nd byte 05 is the data which is to be moved to

register B.

b. IN 01: Read data at port B.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 27

DB, 01 ; IN 01 in the code form.

DB is the opcode for the instruction IN and 01 is the address of a port.

Three word or 3-byte instruction: In a three byte instruction the 1st byte of the instruction is its

opcode and the 2nd and 3rd bytes are either 16-bit data or 16-bit address.

a. LXI H, 2400H : Load H-L pair with 2400H

21, 00, 24 : LXI H, 2400H in the code form

The 1st byte 21 is the opcode for the instruction LXI H. the 2 nd byte 00 is 8 LSB’s of the data

(2400H), which is loaded into register L. the 3 rd byte 24 is 8 MSB’s of the data (2400H), which is

loaded into register H.

b. LDA 2500 H : the content of the memory location 2500H into accumulator.

3A, 00, 25 ; LDA 2500H in the code form.

The 1st byte 3A is opcode for the instruction LDA. The 2 nd byte 00 is 8 LSB’s of the address

of the memory location 2500H. the 3 rd byte 25 is 8 MSB’s of the address of the memory location

2500H. the data is the content of the memory location 2500H. the data is to be loaded into the

accumulator.

1.10 Instruction Cycle:

An instruction is a command given to the computer to perform a specified operation on given

data. To perform a particular task a programmer writes a sequence of instructions, called a program. A

program an data are stored in memory. The CPU fetches one instruction from memory at a time and

execute it. It execute all the instructions of a program one by one to produce the final result.

CPU carries out to fetch an instruction and necessary data from the memory, and execute it

constitute an instruction cycle. An instruction cycle consists of a fetch cycle and execute cycle. In

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 28

fetch cycle a CPU fetches opcode from the memory. The carried data from memory and to perform the

specific operation specified in an instruction, constitute an execute cycle.

The total time required to execute an instruction is given by

IC = FC + EC

Fetch operation:

The 1st byte of an instruction is its opcode. An instruction may be more than one byte long. The

other bytes are data or operand. The program counter (PC) keeps the memory address of next

instruction to be executed. The entire operation of fetching an opcode tasks three clock cycles. The

clock cycle for which the CPU waits is called wait cycle.

Execute Operation:

The opcode fetched from the memory goes to the data register, DR and then to instruction

register, IR. The CPU has to perform some read operation to get the desired data. After receiving the

data it performs execute operation. A read cycle is similar to fetch cycle. In write cycle data are sent

from the CPU to the memory or an output device. Fig. 3.4,3.5 shows an instruction and fetch cycle

respectively.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 29

Machine Cycle & State:

The necessary steps carried out to perform the operation of accessing either memory or I/O

device, constitute a machine cycle. The steps carried out to perform fetch, a read or a write operation

constitute a machine cycle.

In a machine cycle one basic operation such as opcode fetch, memory read, memory write I/O

read and I/O write is performed. An instruction cycle consist of several machine cycle. two-byte and

three-byte instruction require more than one machine cycle.

Fig.3.6 shows instruction cycle for MVI r, data. It has two machine cycles: one for fetching

opcode and the other for reading data from the memory and execution. One subdivision of an

operation performed in one clock cycle is called state or T-state.

Instruction and Data Flow:

A computer receives instructions and data both in binary form. A group of 8 bit is called a byte.

Data and instructions for computers are specified in the byte form. The word length of a computer is

the number of bits it handles at a time. Two kinds of word, namely instruction word (instruction code

or opcode) and data word are processed during an instruction cycle. At the beginning of a fetch cycle

the content of the program counter is transferred to a special register known as memory address

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 30

register, MAR or address register, AR; the content of MAR is transferred to the memory through the

address bus. The decoder circuitry in the memory is activated. The opcode first comes in memory data

register (MDR) or data register (DR) as shown in fig. 3.7.

The execution of an instruction requires the flow of data word in the most of the instructions.

The flow of data word is shown in fig.3.8. a data word is received either from the memory or input

device. The data word flows to the processor through the data bus and is placed in the accumulator or

any other general purpose register depending upon the instruction. After the execution of instruction

the data in a placed in a register or memory location. After the execution of a program the result(data)

is placed in the memory or sent to an output device.

1.11 Timing Diagram:

The necessary steps which are carried out in a machine cycle can be represented graphically,

such a graphical represented is called timing diagram. The timing diagram for opcode fetch, memory

read, memory write I/O read and I/O write will be discussed below.

Timing Diagram for Opcode Fetch Cycle:

In a fetch cycle the microprocessor fetches the opcode of an instruction from the memory. Fig. 3.9

shows the timing diagram for an opcode fetch cycle. T 1, T2, T3 and T4 are consecutive four clock

cycles. The microprocessor issues a low IO/M’ signal to indicate that it wants to make communication

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 31

with the memory. Again the microprocessor sends out high S 0 and S1 signals to indicate that it is going

to perform fetch operation.

During the first clock cycle, T 1, the microprocessor sends out the address of the memory location

where the opcode is available. The 16-bit memory are sent through the address bus A and

address/data bus AD. The 8 MSBs of the memory address are sent over the A bus, and 8 LSBs of the

memory address over AD bus. Since the AD bus is needed to transfer data and subsequent clock

cycles, it is used in time-multiplexed mode. Therefore, it has to be made available to carry data during

T2 and T3. To accomplish this the microprocessor sends an address latch enable signal ALE to latch

the 8 LSBs of the memory address either in the memory or an external latch so that the complete 16-bit

memory address may be available in the subsequent clock cycles.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 32

16-bit memory address is needed by the memory to obtain the opcode from the given memory

address. During T2, AD bus become ready to carry data. In T2 the microprocessor makes RD’ low.

Now memory gets the opcode from the specified memory location and places it on the data bus.

During T3 the opcode is placed in the instruction register, IR which is within the microprocessor. The

memory is disabled when RD’ goes high during T 3. the fetch cycle is completed T3. The opcode is

decoded in T4. The microprocessor examines READY signal in T 2. If it is high, the microprocessor

enters into T3 state. If it is low, the microprocessor inserts a wait state in between T2 and T3.

If an instruction is one byte long, only one machine cycle as shown in Fig.3.9 is required toe fetch

and execute the instruction. Examples of one long instructions are MOV, SUB, ADD, RAL, etc. As

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 33

the operands are in the general purpose registers. The decoding of the operation code and its execution

takes only one clock cycle, T4. if an instruction is two or three bytes long, it requires more machine

cycles. The first machine cycle M 1 is for fetching the opcode from the memory. Subsequent machine

cycle M2, M3 etc. are required either to read data or address from the memory or I/O device or to write

data into the memory or I/O device. Fig M1 shows fetch cycle, and M2 a data read cycle.

Memory Read:

In a memory read cycle the microprocessor reads cycle the microprocessor reads the content of a

memory location. The content is then placed either in the accumulator or any other register of the

CPU. Now let us take an example of two byte long instruction.

MVI A,05

In the coded form it is written as

3E, 05

Where 3E is opcode for MVI A instruction and 05 is data.

This instruction requires two machine cycle, M 1 and M2. The first machine cycle M1 is to fetch the

operation code 3E from the memory. The timing diagram for opcode fetch operation has already been

shown in Fig.3.9. The second machine cycle M2 is for reading the data (05) from the memory as

shown in Fig.3.11. It is a memory read cycle. IO/M’ goes low indicating that the address is for

memory. S1 and S0 are set to 1 and 0 respectively for the read operation. See table 3.1. on the address

lines A8-A15, the 8 MSBs of the memory address of the data(05) are sent. During T 1., 8 LSBs of the

memory address of the data sent on AD 0-AD7. during T2, 8 LSB of the address is latched and AD 0-

AD7 are made free for data transmission. RD’ goes low in T2 to enable the memory for read operation.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 34

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 35

I/O Read:

In an I/O read cycle the microprocessor reads the data available at an input port or input device.

The data is placed in accumulator. An I/O read cycle is similar to memory read cycle. The only

difference between a memory read cycle and I/O ready is that that signal IO/M’ goes high in case of

I/O read. It indicates that the address on the A-bus is for an output device. In timing diagram all other

signals will remain same as shown in fig. 3.11.

Memory Write:

In a memory write cycle the CPU sends data from the accumulator or any other register to the

memory. The timing diagram for a memory write cycle is shown in fig 3.12. the status signals S 0 and

S1 are 1 and 0 respectively for write operation. WR’ goes low in T 2 indicating that the write operation

is to be performed. During T2 the AD bus is not disabled as it is done in case of memory or I/O read

operation. But the data to be sent out to the memory is placed on the AD-bus. WR’ goes high in T 3.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 36

I/O Write:

In an I/O write cycle the CPU sends data to an I/O port or I/O device from the accumulator.

An I/O write cycle is similar to a memory write cycle. In case of I/O write cycle IO/M’ goes high

indicating that the address sent out by the CPU is for I/O device or I/O port. The address of I/O port or

device is duplicated on both A and AD buses. It require three machine cycles. The first machine cycle

is for opcode fetch operation, the second machine cycle is a memory read cycle, third machine cycle is

an I/O write cycle.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 37

2.1 Instruction Set of Intel 8085:

An instruction is a command given to the computer to perform a specified operation on given

data. The instruction set of a microprocessor is the collection of the instructions that the

microprocessor is designed to execute. The instructions have been classified into the following groups:

i. Data Transfer Group ii. Arithmetic Group iii. Logical Group

ii. Branch Control Group iv. I/O and Machine Control Group

i. Data Transfer Group:

Instruction which are used to transfer data from one register to another register, from memory

to register or register to memory, examples are MOV MVI, KXI, LDA, STA etc. when an instruction

of data transfer group is executed, data is transferred from source to destination without altering the

contents of the source.

For example, MOV A, B is executed the content of register B is copied into the register A, the

content of register B unaltered.

ii. Arithmetic Group:

The instruction of this group perform arithmetic operation such as addition, subtraction,

increment or decrement of the content of a register or memory. Examples are: ADD, SUB, INR, DAD

etc.

iii. Logical Group:

The instructions of this group perform logical operation such as AND, OR; compare, rotate etc.

Examples are: ANA, XRA, ORA, CMP, RAL etc.

vi. Branch Control Transfer Group:

This group includes the instructions for conditional and unconditional jump, subroutine call

and return, and restart. Examples are: JMP, JC, JZ, CALL, CZ, RST etc.

v. I/O and Machine Control Group:

This group includes the instructions for input/output ports, stack and machine control.

Examples are: IN, OUT, PUSH, POP HLT etc.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 38

2.2 Instruction and Data Formats:

Intel 8085 is an 8-bit microprocessor, it handles 8-bit data at a time. One byte consist of 8-bits.

A memory location for Intel 8085 microprocessor is designed to accommodate 8-bit data. If 16-bit data

are to be stored, they are stored in consecutive memory locations. The address of a memory location is

of 16-bits i.e. 2 bytes.

The machined code of all instructions are not of the same length, according to the word size the

Intel 8085 instructions are classified into the following three types.

i. One word or 1-byte instruction

ii. Two-word or 2-byte instruction

iii. Three-word or 3-byte instruction

One word or 1-byte instruction:

d. MOV A, B: Move the content of register B to register A. 78H is the opcode for MOV

A, B. the opcode 78H written in the binary form as 01111000. the 1 st two bits, i.e. 01 are

for MOV operation; next three bits 111 are the binary code for register A and last three bits

000 are the binary code for the register B.

e. ADD B: Add the content of register B to the content of the accumulator.80H is the opcode

for the instruction ADD B. the opcode 80H in the binary form is 10000000. the first five

bits, i.e, 10000 specify the operation to be performed i.e. ADD operation. The last three bits

000 are the code for register B.

f. RAL : Rotate the content of the accumulator left by one bit. The opcode for the RAL is

17H.

Two word or 2-byte instruction: In a two byte instruction the 1st byte of the instruction is it’s

opcode and 2nd byte is either data or address

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 39

a. MVI B, 05 : Move 05 to register B.

06, 05 ; MOV B, 05 in the code form

The 1st byte 06 is opcode for MVI B and 2 nd byte 05 is the data which is to be

moved to register B.

b. IN 01: Read data at port B.

DB, 01 ; IN 01 in the code form.

DB is the opcode for the instruction IN and 01 is the address of a port.

Three word or 3-byte instruction: In a three byte instruction the 1st byte of the instruction is its

opcode and the 2nd and 3rd bytes are either 16-bit data or 16-bit address.

a. LXI H, 2400H : Load H-L pair with 2400H

21, 00, 24 : LXI H, 2400H in the code form

The 1st byte 21 is the opcode for the instruction LXI H. the 2 nd byte 00 is 8 LSB’s of the data

(2400H), which is loaded into register L. the 3 rd byte 24 is 8 MSB’s of the data (2400H), which is

loaded into register H.

b. LDA 2500 H : the content of the memory location 2500H into accumulator.

3A, 00, 25 ; LDA 2500H in the code form.

The 1st byte 3A is opcode for the instruction LDA. The 2 nd byte 00 is 8 LSB’s of the address

of the memory location 2500H. the 3 rd byte 25 is 8 MSB’s of the address of the memory location

2500H. the data is the content of the memory location 2500H. the data is to be loaded into the

accumulator.

2.3 Addressing Modes:

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 40

Each instruction require certain data on which it has to operate. There are various techniques to

specify data for instructions. These techniques are called Addressing Modes. Intel 8085 uses the

following addressing modes:

1. Direct Addressing

2. Register Addressing

3. Register Indirect Addressing

4. Immediate Addressing

5. Implicit Addressing

1. Direct Addressing:

In this mode of addressing the address of the operand (data) is given in the instruction itself.

Examples are:

STA 2400 H Store the content of the accumulator in the memory location 2400 H.

32, 00, 24 The above instruction in the code form.

In this instruction 2400H is the memory address where data is to be stored. The 2 nd and 3rd bytes of the

instruction specify the address of the memory location. Here, the source of the data is accumulator.

2. Register Addressing:

In register addressing mode the operands are in the general purpose register. The opcode

specifies the address of the registers in addition to the operation to be performed.

Examples are:

MOV A, B Move the content of register B to register A.

78 The instruction in the code form.

The opcode for MOV A, B is 78H. the operation to be performed the opcode also specifies the register

which contain data. The opcode 78H can be written in binary form as 01111000. the first two bits, i.e.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 41

01 are for MOV operation, next three bits 111 are the binary code for register A, and the last three bits

000 are the binary code for register B.

3. Register Indirect Addressing:

In this mode of addressing the address of the operand is specified by a register pair.

Examples are:

LXI H, 2500H Load H-L pair with 2500H

MOV A, M Move the content of the memory location, whose address is in H-L pair (i.e.,

2500H), to the accumulator.

HLT Halt.

In the above program the instruction MOV A, M is an example of register

indirect addressing. For this instruction the operand is in the memory.

The address of the memory is not directly given in the instruction.

The address of the memory resides in H-L pair and this has already been

specified by an earlier instruction in the program, i.e., as LXI H, 2500H.

4. Immediate Addressing:

In immediate addressing mode the operand is specified within the instruction itself.

Examples are:

MVI A, 05 Move 05 in register A.

3E , 05 The instruction in the code form.

LXI H, 2500 is an example of immediate addressing. 2500 is 16-bit data which is given in the

instruction itself. It is to be loaded into H-L pair.

5. Implicit Addressing:

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 42

There are certain instructions which operate on the content of the accumulator. Such instruction

do not require the address of the operand. Examples are: CMA, RAL, RAR etc.

2.4 Intel 8085 Instruction:

Some of Intel 8085 instructions are frequently, some occasionally and some seldom used by the

programmer. The beginner can learn about 15 to 20 important instructions such as

MOV, MVI, LXI , LDA, LHLD, STA, SHLD, ADD, ADC SUB, JMP, JC, JNC, JZ, JNZ, INX, DCR,

CMP etc.

i. Data Transfer Group:

MOV r1, r2. (Move data: Move the content of one register to another)

[r1]  [r2].

The content of register r2 is moved to register r1. For example, the instruction MOV A, B move

the content of register B to register A. The instruction MOV B, A moves the content of register A to

register B.

MOV r, M. (Move the content of memory to register).

[r][[H-L]].

The content of the memory location, whose address is in H-L pair, is moved to register r.

Example:

LXI H, 2000H Load H-L pair by 2000H

MOV B, M Move the content of the memory location 2000H to register B.

HLT Halt.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 43

MOV M, r (Move the content of register to memory).

[[H-L]]  [r]

The content of register r is moved to the memory location addressed by H-L pair. For example,

MOV M, C moves the content of register C to the memory location whose address is in 'H-L pair.

MVI r, data. (Move immediate data to register).

[r]  data

the 1st byte of the instruction is its opcode. The 2nd byte of the instruction is the data which is

moved to register r. For example, the instruction MVI A, 05 moves 05 to register A. in the code form

it is written as 3E, 05. The opcode for MVI A is 3E and 05 is the data which is to be moved to register

A.

MVI M, data. (Move immediate data to memory).

[[H-L]]  data.

The data is moved to the memory location whose address is in H-L pair.

Example

LXI H, 2400H Load H-L pair with 2400H.

MVI M, 08 Move 08 to the memory location 2400H.

HLT Halt.

In the above example the instruction LXI H, 2400H loads H-L pair with 2400H which is

address of a memory location. Then the instruction MVI M, 08 will move 08 to memory location

2400H. In the code from it is written as 36, 08. The opcode for MVI M is 36 and 08 is the data which

is to be moved to the memory location 2400H.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 44

LXI rp, data 16. (Load register pair immediate).

[rp]  data 16 bits, [rh]  8 MSBs, [rl]  8 LSBs of data.

This instruction loads 16-bit immediate data into register pair rp. This instruction is register pair; only

high-order register is mentioned after the instruction. For example, H in instruction LXI H stands for

H-L pair. Similarly, LXI B is for B-C pair. LXI H, 2500H I 2500H into H-L pair. H with 2500H

denotes that the data 2500 is in hexadecimal. In the code form it is written as 21, 00, 25. The 1st byte

of the instruction 21 is the opcode for LXI H. 2nd byte 00 is 8 LSBs of the data and it is loaded into

register L. The 3rd byte 25 is 8 MS of the data and it is loaded into register H.

LDA addr. (Load accumulator direct).

[A] [addr].

The content of the memory location, whose address is specified by the 2nd and 3rd byte of the

instruction; is loaded into the accumulator. The instruction LDA 2400H win load the content of the

memory location 2400H into the accumulator. In the code form it is written 3A, 00, 24. The 1st byte

3A is the opcode of the instruction. The 2nd byte 00 of is 8 LSBs the memory address. The 3rd byte 24

is 8 MSBs of the memory address.

STA addr. (Store accumulator direct).

[addr] [A]

The content of the accumulator is stored in the memory location whose address is specified by

the 2nd and 3rd bytes of the instruction. STA 2000H will store the content of the accumulator in the

memory location 2000H.

LHLD addr (Load H-L pair direct).

[L][addr], [H][adder+1].

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 45

The content of the memory location, whose address is specified by the 2nd and 3rd bytes of the

instruction, is loaded into register L. The content of the next memory location is loaded into register H.

For example, LHLD 2500H will load the content of the memory location 2500H into register L. The

content of the memory location 2501H is loaded into register H.

SHLD addr. (Store H-L pair direct)

[addr][L], [addr+1]  [H]

The content of register L is stored in the memory location whose address is specified by the

2nd and 3rd bytes of the instruction. The content of register H is stored in the next memory location.

For example, SHLD 2500H win store the content of register L in the memory location 2500H. The

content of register H is stored in the memory location 2501 H.

LDAX rp (Load accumulator indirect)

[A] [[rp]]

The content of the memory location, whose address is in the register pair rp, is loaded into the

accumulator. For example, LDAX B will load the content of the memory location, whose address is in

B-C pair, into the accumulator. This instruction is used only for B-C and D-E register pairs.

STAX rp. (Store accumulator indirect)

[[rp]][A]

The content of the accumulator is stored in the memory location whose address is in the

register pair rp. For example, ST AX D will store the content of the accumulator in the memory

location whose address is in D-E pair. This instruction is true only for register B-C and D-E.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 46

XCHG (Exchange the contents of H-L with D-E pair)

[H-L]   [D-E].

The content of H-L pair are exchanged with contents of D-E pair.

ii. Arithmetic Group:

ADD r (Add register to accumulator)

[A][A]+[r].

The content of register r is added to the content of accumulator, and the sum is placed in the

accumulator.

ADD M (Add memory to accumulator)

[A][A]+[[H-L]].

The content of the memory location is addressed by H-L pair is added to the content of the

accumulator. The sum is placed in accumulator.

ADC r (Add register with carry to accumulator)

[A][A]+[r]+[CS]

The content of the register r and carry status are added to the content of the accumulator. The

sum is placed in the accumulator.

ADC M (Add memory with carry to accumulator)

[A][A]+[[H-L]]+[CS]

The content of the memory location addressed by H-L pair and carry status are added to the

content of the accumulator. The sum is placed in the accumulator.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 47

ADI data (Add immediate data to accumulator)

[A][A]+data

The immediate data is added to the content of the accumulator. The 1 st byte of the instruction is

opcode. The 2nd byte of the instruction is data, and it is added to the content of the accumulator. The

sum is placed in the accumulator.

ACI data (Add with carry immediate data to accumulator)

[A][A] +data+[CS]

The 2nd byte of instruction (which is data) and the carry status are added to the content of the

accumulator. The sum is placed in the accumulator.

DAD rp (Add register pair to H-L pair)

[H-L] [H-L]+[rp]

The content of register pair rp are added to the contents of H-L pair and the result is placed in

H-L pair. Only carry flag is affected.

SUB r (Subtract register from accumulator)

[A] [A]-[r]

The content of register r is subtracted from the content of the accumulator, and the result is

placed in the accumulator.

SUB M (Subtract memory from accumulator)

[A] [A]-[[H-L]]

The content of memory location addressed by the H-L pair is subtracted from the content of the

accumulator, and the result is placed in the accumulator.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 48

SBB r (Subtract register with accumulator with borrow)

[A] [A]-[r]-[CS]

The content of register r and carry status are subtracted from the content of the accumulator,

and the result is placed in the accumulator.

SBB M (Subtract memory from accumulator with borrow)

[A] [A]-[[H-L]]-[CS]

The content of memory location addressed by the H-L pair and carry status are subtracted from

the content of the accumulator, and the result is placed in the accumulator.

SUI data (Subtract immediate data from accumulator)

[A][A]-data

The 2nd byte of instruction is data. It is subtracted from the content of the accumulator. The

result is placed in the accumulator.

SBI data (Subtract immediate data from accumulator with borrow)

[A][A]-data-[CS]

The data and carry status are subtracted from the content of accumulator. The result is placed in

the accumulator.

INR r (Increment memory content)

[r][r]+1

The content of register r is incremented by one. All flags except CS are affected.

INR M (Increment memory content)

[[H-L]][[H-L]]+1

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 49

The content of memory location addressed by H-L pair is incremented by one. Flags except CS

are affected.

DCR r (Decrement register content)

[r][r]-1

The content of register r is decremented by one. All flags except CS are affected.

DCR M (Decrement memory content)

[[H-L]][[H-L]]-1

The content of the memory location addressed by H-L pair is decremented by one. All flags

except CS are affected.

INX rp (Increment register pair)

[rp][rp]+1

The content of the register pair rp is incremented by one. No flag is affected.

DCX rp (Decrement register pair)

[rp][rp]-1

The content of the register pair rp is decremented by one. No flag is affected.

DAA (Decimal Adjust Accumulator)

The instruction DAA is used in the program after ADD, ADI, ACI, ADC instruction. After the

execution of ADD or ADC instruction the result is hexadecimal and it is placed in the accumulator.

The DAA instruction operates on this result and gives the final result in the decimal system. It uses

carry and auxiliary carry for decimal adjustment. 6 is added to 4 LSBs of the content of the

accumulator if their values lies between A and F or the AC flag is set to 1. similarly, 6 is also added to

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 50

4 MSBs of the content of the accumulator if their value lies in between A and F or the CS flag is set to

1.

iii. Logical Group:

The instructions of this group perform AND, OR, EXCLUSIVE OR operations; compare,

rotate or take complement of data in register or memory.

ANA r ( AND register with accumulator)

[A][A]^[r]

The content of register r is ANDed with the content of the accumulator, and the result is placed

in accumulator. All status flags are affected. The flag is CS is cleared. i.e. it is set to 0. auxiliary carry

flag is AC is set to 1.

ANA M (AND memory with accumulator)

[A][A]^[[H-L]]

The content of the memory location addressed by H-L pair is ANDed with the accumulator.

The result is placed in the accumulator. All flags are affected. The CS flag is set to 0 and AC to 1.

ANI data ( AND immediate data with accumulator)

[A][A]^data

The 2nd byte of the instruction is data, and it is ANDed with the content of the accumulator. The

result is placed in the accumulator. The CS flag is set to 0 and AC to 1.

ORA r (OR register with accumulator)

[A][A]V[r]

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 51

The content of register r is ORed with the content of accumulator. The result is placed in the

accumulator. All status flags are affected. Carry and auxiliary carry are cleared. i.e. the CS and AC

flags are set to 0.

ORA M (OR memory with accumulator)

[A][A]V[[H-L]]

The content of the memory location addressed by H-L pair is ORed with the content of

accumulator. The result is placed in the accumulator. The CS and AC flags are set to 0.

ORI data (OR immediate data with accumulator)

[A][A] V data

The 2nd byte of the instruction is data and it is ORed with the content of the accumulator. The

result is placed in the accumulator. All status flags are affected. The CS and AC flags are set to 0.

XRA r (EXCLUSIVE –OR register with accumulator)

[A][A]V[r]

The content of register r is EXCLUSIVE ORed with the content of the accumulator. The result

is placed in accumulator. All status flags are affected. The CS and AC flags are set to 0.

XRA M (EXCLUSIVE – OR memory with accumulator)

[A]  [A] V [[H-L

The content of the memory location addressed by H-L pair is EXCLUSIVE ORed with the

content of the accumulator. The result is placed in the accumulator. All status flags affected. The CS

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 52

and AC flags are set to 0.

XRI data. (EXCLUSIVE OR immediate data with accumulator)

[A] [A] V data.

The 2nd byte of the instruction is data, and it is EXCLUSIVE ORed with the content of the

accumulator. The result is placed in the accumulator. All flags are affected. The CS and AC flags are

set to O.

CMA. (Complement the accumulator).

[A]  [A’]

l's complement of the content of the accumulator is obtained, and the result is placed in the

accumulator. To obtain the l's complement of a binary number 0 is replaced by 1, and 1 by O. For

example one's complement of 1100 is 0011.

CMC. (Complement the carry status).

[CS]  [CS’].

The CS flag is complemented. Other flags are not affected.

STC. (Set carry status). -

[CS]  1.

The status flag CS is set to 1. Other flags are not affected.

CMP r. (Compare register with accumulator).

[A] - [r].

The content of register r is subtracted from the content of the accumulator and status flags are set

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 53

according to the result of the subtraction. But the result is discarded. The content of the accumulator

remains unchanged.

CMP M. (Compare memory with accumulator).

[A] - [[H-L]].

The content of the memory location addressed by H-L pair is subtracted from the content of the

accumulator, and status flags are set according to the result of the subtraction. But the result is

discarded. The content of the accumulator remains unchanged.

CPI data. (Compare immediate data with accumulator).

[A] - data.

The 2nd byte of the instruction is data, and it is subtracted from the content of accumulator. The

status flags are set according to the result of subtraction. But the result is discarded. The content of the

accumulator remains unchanged.

RLC. (Rotate accumulator left).

[An+l]  [An], [A0] +- [A7], [CS]  [A7].

The content of the accumulator is rotated left by one bit. The seventh bit of the accumulator is

moved to carry bit as well as to the zero bit of the accumulator. Only CS flag is affected see

Fig. 4.1.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 54

RRC (Rotate accumulator right)

[A7][A0]. [CS][A0], [An][An+1]

The content of the accumulator is rotated right by one it. The zero bit of the accumulator is

moved to the seventh bit as well as to carry bit. Only CS flag is affected. See fig. 4.2

RAL (Rotate accumulator left through carry)

[An+1]  [An], [CS] [A7], [A0]  [CS]

The content of the accumulator is rotated left one bit through carry. The seventh bit of the

accumulator is moved to the carry, and the carry bit is moved to the zero bit of the accumulator. Only

carry flag is affected. See fig.4.3

RAR Rotate accumulator right through carry)

[An]  [An+1], [CS] [A0], [A7],  [CS]

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 55

The content of the accumulator is rotated right one bit through carry. The zero bit of the

accumulator is moved to the carry, and the carry bit is moved to the seventh bit of the accumulator.

Only carry flag is affected. See fig.4.4.

iv. Branch Group:

The instructions of this group change the normal sequence of the program. There are two types

of branch instructions: conditional and unconditional. The conditional branch instructions transfer the

program to the specified label when certain condition is satisfied. The unconditional branch

instructions transfer the program to the specified label unconditionally.

JMP addr (label). (Unconditional jump: jump to the instruction specified by the operand)

[PC] Label

Byte 2nd and byte 3rd of the instruction give the address of the label where the program jumps. The

address of the label is the address of memory location for next instruction to be executed. The program

jumps to the instruction specified by the address (label) unconditionally .

Conditional Jump addr (label).

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 56

After the execution of a conditional jump instruction the program jumps to the instruction

specified by the address (label) if the specified condition is fulfilled. The program proceeds further in

the normal sequence if the specified condition is not fulfilled. If the condition is true and program

jumps to the specified label.

a. JZ addr (label). (Jump if the result is zero)

[PC]address(label), jump if Z=1.

The program jump to the instruction specified by the address(label) if the result is zero (i.e.

zero status Z=1). Here the result after the execution of the preceding instruction is under the

consideration.

b. JNZ addr (label). (Jump if the result is not zero)

[PC]address(label), jump if Z=0.

The program jump to the instruction specified by the address(label) if the result is non-zero

(i.e. the zero status Z=0).

c. JC addr(label). (Jump if there is a carry)

[PC]address(label), jump if CS=1.

The program jumps to the instruction specified by the address (label) if there is a carry (i.e. the

carry status: CS = 1). Here the carry after the execution of the preceding instruction is under the

consideration.

d. JNC addr(label). (Jump if there is a no carry)

[PC] address(label), jump if CS=0.

The program jump to the instruction specified by the address(label) if there is no carry 9i.e. the

carry states CS=0).

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 57

e. JP addr (label) (Jump if the result is plus)

[PC]address (label), jump if S=0.

The program jumps to the instruction specified by the address (label) if the result is plus.

f. JM addr (label) (Jump if the result is minus)

[PC]address (label), jump if S=1.

If the result is minus the program jumps to the instruction specified by the address (label).

g. JPE addr (label) (Jump if even parity)

[PC]address (label), jump if even parity: the parity status P=1.

If the result contains even number of 1’s, the program jump to the instruction specified by the

address (label).

h. JPO addr (label) (Jump if odd parity)

[PC]address (label), jump if odd parity; the parity status P=0.

If the result contains odd number of 1’s, the program jump to the instruction specified by the

address (label).

CALL addr (label): (Unconditional call: call the subroutine identified by the operand)

[[SP]-1]  [PCH]

[[SP]-2]  [PCL]

[SP]  [SP]-2

[PC]addr (label)

CALL instruction is used to call a subroutine. Before the control is transferred to the

subroutine, the address of the next instruction of the main program is saved in the stack. The content of

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 58

the stack pointer is decremented by two to indicate the new stacktop. Then the program jumps to

subroutine starting at address specified by the label.

Conditional CALL addr (label)

[[SP]-1[PCH],[[SP]-2][PCL]

[PC]addr (label), [SP][SP]-2

If the condition is true and program calls the specified subroutine, the execution of a conditional call

instruction take 5 machine cycles. If condition is not true only 2 machine cycles.

Conditional Return

[PCL][[SP]],[PCH][[SP]+1]

[SP][SP]+2

If the condition is true and program returns from the subroutine, the execution of a conditional return

instruction takes 3 machine cycle. If condition is not true only one machine cycle.

RST n (Restart)

[[SP]-1][PCH], [[SP]-2][PCL]

[SP][SP]-2, [PC] 8 times n.

Restart is a one-word CALL instruction. The content of the program counter is saved in the

stack. The program jumps to the instruction starting a restart location. The address of the restart

location is 8 times n.

v. Stack, I/O and machine control group:

IN port-address (Input to accumulator from I/O port)

[A][Port]

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 59

The data available on the port is moved to the accumulator. After the instruction IN, the

address of the port is specified. The 2 nd byte of the instruction contains the address of the port. The

address of a port is an 8-bit address.

OUT port-address (Output from accumulator to I/O port)

[Port] [A]

The content of accumulator is moved to the port specified by its address. After the OUT

instruction IN, the port address is specified. The 2 nd byte of the instruction contains the address of the

port.

PUSH. (Push the content of register pair to stack)

[[SP]-1][rh],

[[SP]-2][rl],

[SP][SP]-2

The content of the register pair rp is pushed into the stack.

PUSH PSW (Push processor Status Word)

[[SP]-1][A],

[[SP]-2]PSW (Program Status Word)

[SP][SP]-2

The content of the accumulator is pushed into the stack. The content of the status flags are also

pushed into the stack. The content of the register SP is decremented by 2 to indicate new stacktop.

POP. (Pop the content of register pair from the stack)

[rl],  [[SP]]

[rh],  [[SP]+1]

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 60

[SP][SP]+2

The content of the register pair which was saved earlier is moved from the stack to the register

pair.

POP PSW (Pop processor Status Word)

PSW [[SP]]

[A][[SP]+1]

[SP][SP]+2

The processor status word which was saved earlier during the execution of the program is

moved from the stack to PSW. The content of the accumulator which was also saved is moved from

the stack to the accumulator.

HLT (Halt)

The execution of the instruction HLT stops the microprocessor.

SPHL (Move the contents of H-L pair to stack pointer)

[H-L][SP]

The contents of H-L pair are transferred to the SP register.

EI (Enable Interrupt)

When this instruction is executed the interrupt system is enabled.

DI (Disable Interrupt)

When this instruction is executed the interrupts are disabled.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 61

SIM (Set Interrupt Masks)

When this instruction is executed bits 0-5 of the accumulator are used in programming the

restart interrupt masks. Bits 6-7 of the accumulator are used in making serial output on SOD line.

RIM ( Read Interrupt Mask)

When this instruction is executed, the accumulator is loaded with pending interrupts, the restart

interrupt masks and the contents of SID.

NOP (No operation)

No operation is performed when this instruction is executed. The registers and flags remain

unaffected.

2.5 Programming of Microprocessors

A computer can only do what the programmer asks to do. To perform a particular task the

programmer prepares a sequence of instruction, called a Program. A set of programs written for a

particular computer known as Software for that computer. The program is stored in RAM. The CPU

takes one instruction of the program at a time from RAM and execute it. It executes all instruction of

the program one by one to produce result.

The instructions are coded and stored in the memory in the form of 0’s and 1’s. A program

written in the form of 0s and 1s is called a machine language program.

The Demerits of Machine Language programs are :

a. It is very difficult to understand or debug the program.

b. Each bit has to be entered individually the entry of a program is very slow.

c. Programs are long.

d. Program writing is difficult and tiresome.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 62

e. Chances of careless errors in writing the program.

2.6 Assembly Language:

The writing of program in machine language is very difficult, tiresome, boring and error. To

facilitate programmers easily understandable language have been developed. Assembly language is

one of them. A programmer can easily write a program in alphanumeric symbols instead of 0s and 1s.

meaningful and easily rememberable symbols are chosen for the purpose. Examples are : ADD for

addition, SUB for subtraction, CMP for comparison. Such symbols are called Mnemonics. A program

written in mnemonics is known as Assembly language program. The writing of a program in assembly

language is much easier and faster as compared to the writing of a program in machine language.

A program which translates an assembly language program into a machine language program is

called an Assembler.

ONE-PASS & TWO-PASS ASSEMBLER:

An assembler which goes through an assembly language program only once is known as one-

pass assembler. An assembler which goes through an assembly language program twice is called two-

pass assembler.

An assembly language program for the addition of two numbers placed in two consecutive

memory locations 251H and 2502H. the sum is stored in the memory location 2503H.

Example

Mnemonics Operands Comments

LXI H, 2501 Get the address of the 1st number in H-L Pair

MOV A,M Get the 1st number in accumulator

INX H Increment content of H-L pair

ADD M Add the 1st and 2nd number

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 63

STA 2503 Store sum in 2503

HLT Stop

Data

2501 – 49H

2502 – 56H

Result

2503 – 9F

The programmer first of all writes program in assembly language and then he fills up the

machine code corresponding to each mnemonics. This is called hand assembly. The codes are written

in hexadecimal systems. In microprocessor kit there is an arrangement for converting hexadecimal into

binary codes.

The program for the addition of two numbers in assembly language with hexadecimal codes is

given below.

Mnemonics Operands Comments

LXI H, 2501 H Get the address of the 1st number in H-L Pair

MOV A,M The 1st number in accumulator

INX H Increment content of H-L pair

ADD M Add the 1st and 2nd number

STA 2503 Store sum in 2503

HLT Stop

Data

2501 – 49H

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 64

2502 – 56H

Result

2503 – 9F

The Disadvantages of assembly language as compared to high level language

1. Programming is difficult and time consuming.

2. The assembly language is computer oriented. The programmer require to have the detailed

knowledge of the particular computer.

3. Assembly language program is not portable. i.e. the program written for one microcomputer

can not be used for any other because each microcomputer has its own assembly language.

4. Assembly language program is longer as compared to a high level language.

2.7 High-Level Language:

The difficulties associated with assembly language can be overcome using High-level

languages. Instructions written in high-level languages are called statements.. In a high-level language

statements more clearly resemble English and Mathematics. Examples of high-level languages are:

FORTRAN, COBOL, BASIC, PASAL, ALGOL, PL/M etc. These languages are procedure-oriented.

The program writing in these languages is easier and faster because one statement of a high-level

language corresponds to many instructions of assembly language. A compiler is needed to translate

high-level language to machine codes for the operation of a computer.

COMPILER. A program that translates a high-level language program into a machine

language program is called a compiler. A compiler is more powerful than assembler. It check all kinds

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 65

of limits, ranges, errors etc. If a compiler runs on the computer for which it produces object codes, is

called a self-compiler or resident compiler. If it runs on a computer other than that for which it

produce object codes, is called a cross-compiler.

INTERPRETER. It is also a translator. It translates a high-level language program object

codes, statement wise. It does not translate the entire program at a time. It takes up one statement of a

high-level language program at a time, translates it and then executes it.

FORTRAN is an abbreviation of Formula Translation. It was developed in the early 1950s by

IBM. It is an ideal language for scientific and engineering computation as it contains functions for

complex mathematical operations. There are several versions of this Language. Earlier, FORTRAN IV

was very popular. In 1977 the American National Standards Institute (ANSI) published a standard for

FORTRAN with an idea that all manufacturers should same form of the language. This standard form

of the language is FORTRAN 77. This' most popular and Widely used language for scientific and

engineering calculation. A vast Library of softwares is available in FORTRAN.

COBOL. This abbreviation stands for Common Business Oriented Language. It was

introduced in 1960 by U.S. industry/government committee. It is a widely used language for large

business application/data processing such as handling of ledgers, accounts and payroll files.

PASCAL. It is a high-level. language named in the honour of the inventor of the first

mechanical calculator, Blaise Pascal (a French mathematician). The language was developed Nicklaus

Wirth in Switzerland in the early 1970s. It is suitable for both scientific and business applications, and

therefore, it may be called a multipurpose language. As it is a compact language compiler is quite

suitable for a smaller system. Program design and debugging is simpler. Program compiled from

PASCAL runs several times faster than the same program compiled from BASIC or FORTRAN.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 66

BASIC. It is an abbreviation for Beginners All-purpose Symbolic Instruction Code. It is for

scientific and engineering computation. It is not as powerful as FORTRAN. It is simple and easy

language. It was introduced in 1965 by Dartmouth College.

ALGOL. The abbreviation stands for Algorithmic Language. It is a scientific language of

handling numerical computation encountered in science and engineering. It was introduced in 1960 by

international committee. It is used in some universities and computer center, but not in industries. In

industries FORTRAN is common.

PL/1. It is an abbreviation for Programming- Language One. It was introduced in 1965 by

IBM. It is more powerful than FORTRAN. It requires a very large compiler. It is a multipurpose

language suitable for both scientific and business applications. It has features of both FORTRAN and

COBOL.

PL/M. It is an abbreviation for Programming Language Microcomputer. It was developed by

Intel in 1975. A programmer can write programs for Intel 8080/8085 in PL/M faster than assembly

language directly. PL/M compiler is used with Intel micro development system. It is a microprocessor-

oriented high-level language.

FORTH (from Fourth-Generation Computer). It is suitable for small computer system. It

introduced in 1974 by Moore and Rather. It efficiently utilises the resources of a computer such as

memory space and CPU execution speed. Like C, it has features of assembly language. It is used by

system programmers for software development.

APL. It has been developed by IBM. The abbreviation stands for A Programming Language. It

is a very powerful language. It allows users to define instruction. It has a large library of

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 67

predetermined functions. It requires a large computer to run. It is designed for mathematical work. It is

more powerful than FORTRAN; but it is very complex, and difficult to use.

ADA. It has been named after Ada Lady Lovelace. It was introduced in 1980 by CII-

Honeywell-Bull (France). It is a multipurpose language suitable for both scientific and business

applications. It combines the best features of PASCAL, ALGOL and PL/1 It also has the feature of

real-time multitasking required in control applications. As an engineers uses LSI devices to design a

digital system, one can use software components for writing complex programs.

C Language. It is a general purpose high-level language having features similar to PASCAL. It

also allows programmer to manipulate internal registers of the processor. It is a powerful, flexible and

very efficient language. It is used in writing operating system and software package.

PROLOG. It stands for Programming Logic. It is new language suitable for artificial

intelligence. It was developed in 1972 at the University of Marseillers. It is capable of handling large

databases.

LISP. It stands for List Processing. It was developed in early 1960s by McCarthy. This language

is also suitable for artificial intelligence. Both PROLOG and LISP are excellent language for artificial

intelligence application. PROLOG needs less memory space than LISP and hence PROLOG preferred

where memory space is limited. LISP is more powerful in I/O handling and graphics

SNOBOL. It stands for String Oriented SymBOlic Language. It was developed in mid 1960s. It

can manipulate strings of characters and hence, it is used for text processing.

LOGO. It was developed at MIT in the late 1960s by Seymour Papert and his colleagues It has

been used in Universities for complex scientific problems. It has also been used for children as

educational language to achieve intellectual growth and problem solving skills. Logo has graphic

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 68

features. Children can draw, color and animate images. It can also be used to compose music,

manipulate text, manage data etc. It runs on PCs.

APT. It stands for Automatically Programmed Tooling. It is used to control machine tools in

manufacturing applications.

PILOT. It stands for Programmed Inquiry Learning Or Teaching. It is used in the preparation of

computer-assisted instructions.

MODULA-2. It was developed by Nicklaus Wirth, the creator of PASCAL. It is strongly

structured language. Its compiler finds programming errors more easily as compared to the compilers

of other languages

Advantages of High-Level Language

1. Instructions are very clear.

2. The writing of program in a high-level language is easier and faster than the writing of

programs in assembly language.

3. Programs in high-level languages are portable i.e. they can run on any computer or

microcomputer having standard compiler for that language.

4. Easier documentation.

5. The program is independent of the structure of a particular computer. The program is problem

oriented rather than computer oriented.

6. Standard syntax.

Disadvantages of High-Level Languages

1. One has to learn the special rules for writing programs in a particular high-level language.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 69

2. Low speed. One statement in a high-level language corresponds to many instructions in

machine language. Hence the high-level language takes more time to produce result -i.e.

computation time is more.

3. Low efficiency of memory utilization. A program in high-level language occupies a larger part

of the memory.

4. Extensive hardware and software supports are required.

5. A compiler has to be provided to convert a high-level language program into a machine

language program. The compiler is costly.

2.8 Stacks:

The registers are required for some other operation in subsequent steps. These contents are

moved to certain memory locations by PUSH operation. Then the registers are used for other

operations. After completing these operations those contents which were saved in the memory are

transferred back to the registers by POP operation. Memory locations for this purpose is set aside by

the programmer in the beginning. The set of memory locations kept for this purpose is called stack.

The last memory location of the occupied portion of the stack is called stacktop.

A special 16-bit register known as stack pointer holds the address of stacktop. The stack

pointer is initialized in the beginning of the program by LXI or SPHL instruction. Any area of the

RAM can be used as stack. There is no restriction on the location of the stack in the memory. Data are

stored in the stack on last-in-first-out (LIFO) principle.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 70

Fig. 5.1 shows a typical stack and stacktop location. The SP register holds the address of

stacktop location. Fig. 5.2 (a) shows the position of a stack before PUSH operation. Suppose the

contents of the register pair B-C is to be pushed. After PUSH operation the stack position has been

shown in Fig. 5.2 (b). Similarly, POP operation is used to transfer the contents from the stack to the

register. The stack position before and after the POP operation has been shown Fig. 5.3 (a) and (b)

respectively.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 71

2.9 Subroutines:

While writing a program certain operations may occur several times and they are not available

as individual instruction. The program for such operations are repeated again and again in the main

program. A simple example of such operation is multiplication. The Intel 8085 does not have any

instruction for multiplication and hence, a program is written to perform multiplication. Similarly,

small programs are written for functions like sine, cosine, logarithm, square root etc. the concept of

instructions is used to avoid the repetition of smaller program.

The small program for a particular task is called subroutine. Subroutines are written separately

and stored in memory. They are called at various points of the main program by CALL instruction

where they are required. The last instruction of the subroutines is RET. After the completion of a

subroutine, the main program begins from the instruction immediately following the CALL

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 72

instruction. The techniques of subroutine saves memory locations. Fig. 5.4 shows a call-return

structure.

2.10 MACRO:

A sequence of instructions to which a name is assigned is called a Macro. The name of the

macro is used in assembly language programming. The macro facility is available with many

assemblers. Each macro is clearly defined and unique name is assigned to it.

Example 1:

COMPILE MACRO ADDRESS

LXI H, ADDRESS

MOV A, M

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 73

CMA

ENDM

In the above example COMPILE is the name of the macro. MACRO is written in the beginning of the

definition as shown in example1. ADDRESS is a parameter. ENDM is used to end the macro. If we

write COMPLE 2500H in an assembly language program, the assembler will replace this macro by

the following sequence of instructions in the program.

LXI H, 2500H

MOV A, M

CMA

This sequence of instruction will take the complement of the content of the memory location 2500H.

2.11 Microprogramming:

The CPU performs the following tasks to execute an instruction:

 The CPU places the content of the program counter on the address but to fetch the opcode of

the instruction from the memory.

 The CPU reads the opcode from the memory and places it in the instruction register.

 The CPU decodes the instruction.

 The CPU takes other data, if necessary, from the memory or other register to execute the

instruction.

 The CPU executes the instruction.

 The CPU increments the content of the program counter so that it will be able to fetch the next

instruction.

Two basic approaches to design of a CPU are: Hard-wiring and Microprogramming. In a

hardwired CPU logic circuits produce the required sequence of operations to execute an instruction.

This is a hardware approach to control the above mentioned operations. The same sequence of

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 74

operations can also be performed using software. To execute each step there is a micro operation. To

writing of a sequence of micro operations is known as microprogramming.

2.12 System software:

The hardware of a computer system can’t do anything by itself; software is required to direct it

what to do. The system software is a collection of programs written for a computer which allows user

to develop and run his program. The system software is stored in ROM/Disks. It includes operating

system, BIOS, assembler, compiler, editor, etc. an operating system is a collection of programs. It

control the overall operation of a computer. It provides programmers an interface to a computer. A

simple operating system is a called a monitor.

a) Monitor:

A monitor is a program which resides in a ROM or PROM. It carries out the following functions:

 Initializes the system.

 Loading of programs into ROM

 Control of input and output devices.

 Displaying of the contents of internal CPU registers or memory location.

 Modifying the contents of CPU registers or memory location.

 Execution of the program which is in RAM or ROM.

In a microprocessor kit a monitor controls its entire operation. It contains subroutines for debugging

programs. It also contains commands like INSERT, DELETE, DELAY, RELOCATE etc. it controls

CRT terminal, printer etc.

b) Operating System:

An operating system of a computer is the main component of the system software. It is

responsible for managing files on the disks and communication between the computer and peripherals,

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 75

memory space management etc. it is a program or collection of program which are usually stored on

disks. The operating system stored on disk is called Disk Operating System (DOS).

An operating system helps user in performing the following tasks:

 Create disk file

 Write programs and data into files; edit them and store them

 Read data from files

 Link subroutine with the main program

 Load inked programs and execute them

 Debugging of programs

An Operating System contain following standard programs:

File Manager: File Manager is a program which allows user to create, delete, copy or update files on

the disks. The term files refers to the collection of information supplied by the programmer. Which is

stored on the disk as a single entity and is accessible by name.

Linker: A large program is divided in smaller programs known as modules. It is easier to develop, test

and debug smaller programs. A linker is a program which links smaller programs together to form a

large program. The linker also links these subroutines with the main program. The linker links object

code(machine codes)program.

Locator: A locator is a program which assigns specific memory addresses for the machine codes of

the program to be loaded into the memory.

Debugger: Debugger is a program which allows user to test and debug the programs. All computers

including microprocessors kits provide debugging facility. To detect errors a program can be tested in

single steps. Each step of the program is executed and tested.

Assembler or Macro assembler: An assembler or Macro assembler generally forms a part of the

operating system of an MDS, microcomputer and personal computer. An assembler is a program

which translates an assembly language program into machine language program.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 76

c) Text Editor:

A text editor is a program which allows user to write source program or text into RAM. The

user write his program in assembly or high level language in proper format. A program written in these

language in the proper format is known as source program. The typing or program errors are easily

corrected using the commands of the editor. The use can add or delete lines anywhere in the program

using proper commands of the editor.

d) System Software, Application software & Utility program:

System software:

The software require for running user programs is known as system software. It includes

monitor, operating system, compiler, interpreter etc.

Application software:

Special purpose software written for specific use is known as application software. Examples

of application software (or program) are accounting packages, data base management packages and

computer-based engineering design packages.

Utility program: These are software tools which help users in developing, writing, debugging and

documenting programs.

e) Multiuser/Multitasking Operating System:

In a multiuser system a number of terminals are connected to a single CPU. Several users work

simultaneously on the computer. A multiuser system works on time-share principle.

In industrial applications a number of tasks are handled by the CPU. The term multitasking is

used in real-time industrial applications. They are attended on priority basis. A low priority task can be

interrupted by a higher priority task.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 77

In a multiuser/multitasking system a number of tasks are to be handled simultaneously. The

CPU must take up these tasks in a scheduled manner so that they are executed properly. The part of the

operating system which manages scheduling work is known as scheduler, dispatcher or supervisor.

f) Windows:

Windows 3.1 is an operating system environment recently developed by Microsoft. It provides

user a graphical interface for application program. It has been developed for personal computer.

Windows can use virtual memory resources as well. It promises more than 1000 enhancements, fast

speed and ease of use. Today, in almost all environment related to management, finance, sales,

marketing, development and other general office functions need a rapid access to information and

powerful tools to manipulate, analyse, exchange and present information.

g) UNIX:

UNIX is a multiuser system. It allows several users to share a CPU on time share basis. It

contains three layers. The innermost layer is known as kernel. It contains scheduler and a hierarchical

file structure. The middle layer of the operating system is known as shell which contains the command

interpreter. It decodes and carries out the user-entered commands. The outermost layer contains

programming tools such as assembler, editer, debugger, compiler and application packages.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 78

EXAMPLES OF ASSEMBLY LANGUAGE PROGRAMS

3.1 Simple Examples

Example 1.

Object: Place 05 in register B.

Program:

Memory Machine Mnemonics Operands Comments

Address Codes

FC00 06,05 MVI B, 05 Get 05 in register B.

FC02 76 HLT Stop

The instruction MVI B, 05 moves 05 to register B. HLT halts the program. A program is fed to

microprocessor kit in machine codes. The machine code for the instruction MVI B, 05 is 06, 05. the

1st byte of the instruction is 06 which is the machine code for the instruction MVI B. the code for HLT

is 76. this program can be executed on a microprocessor kit and the register B can be examined. After

the execution of the program the register B will contain 05.

Example 2.

Object: Get 05 in register A; then move it to register B.

Program:

Memory Machine Mnemonics Operands Comments

Address Codes

FC00 3E,05 MVI A, 05 Get 05 in register A.

FC02 72 MOV B, A Transfer 05 from register A to B.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 79

The instruction MVI A, 05 will moves 05 to register A. in the code form it is written as 3E, 05.

the1st byte of the instruction is 3E. this code is for MVI A. the second byte 05 is the data which is to

be placed in A. the instruction MOV B, A transfers the content of register A to register B.

Example 3.

Object: Load the content of the memory location FC50 H directly to the accumulator, then transfer it to

register B. the content of the memory location FC50 H is 05.

Program:

Memory Machine Mnemonics Operands Comments

Address Codes

FC00 3A,50,FC LDA FC50 Get the content of the memory location

FC50 H into ACC.

FC03 47 MOV B, A Move the content of register A to B.

FC04 76 HLT Halt.

The instruction LDA loads the accumulator directly with the content of the memory location

specified in the instruction. Thus the instruction LDA FC50 will load the accumulator with the content

of the memory location FC50 H. the instruction MOV B,A will move the content of the accumulator to

B. the content of the memory location FC50 H is 05. after the execution of the program the register B

will contain 05.

Example 4.

Object: Place the content of the memory location FC50 H in register B and that of FC51 H register C.

the contents of FC50 and FC51 H are 11 H and 12 H respectively.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 80

Program:

Memory Machine Mnemonics Operands Comments

Address Codes

FC00 21,50,FC LXA H, FC50H Get FC50 H in H-L pair.

FC03 47 MOV B, M Move the content of FC50 to B.

FC04 23 INX H Increment H-L pair by one.

FC05 4E MOV C, M Move the content of FC51 to C.

FC06 76 HLT Halt.

The instruction LXI H,FC50 H will place FC50 H in H-L pair. FC50 H is the address of the

memory location which contains 11 H. MOV B, M will move the content of FC50 H to register B. the

instruction INX H will increase the content of H-L pair by 1. the execution of the instruction INX H

will increase the content of H-L pair from FC50 to FC51 H. MOV C, M will move the content of FC51

H to register C. thus after the execution of the program the register B and C will contain 11 H and 12

H respectively.

3.2 Addition of Two 8-bit Numbers; Sum 8-bits.

Problem:

Add 49 H and 56 H

The 1st number 49 H is in the memory location 2501 H.

The 2nd number 56 H is in the memory location 2502 H.

The result is to be stored in the memory location 2503 H.

Numbers are represented in hexadecimal system.

Memory Machine Mnemonics Operands Comments

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 81

Address Codes

2000 21,01,25 LXI H, 2501H Get address of 1st number in H-L pair.

2003 7E MOV A, M 1st number in accumulator.

2004 23 INX H Increment content of H-L pair.

2005 86 ADD M Add 1st and 2nd number.

2006 32, 03,25 STA 2503 H Store sum in 2503 H.

2009 76 HLT

Data

2501 - 49 H

2502 – 56 H

The Sum is stored in the memory location 2503 H.

Result

2503 – 9F H

2501 H is the address of the memory location for the 1 st number. 2501 is placed in H-L pair by the

instruction LXI H, 2501 H. the next instruction is MOV A, M which moves the content of the memory

location addressed by H-L pair to the accumulator. In this case H-L pair contains 2501 H and,

therefore, the content of the memory location 2501 H is moved to the accumulator. Thus the 1 st

number 49 H has been moved to the accumulator. The instruction INX H increases the content H-L

pair by one. After the execution of INX H it becomes 2502 H. ADD M adds the content of the

accumulator and the content of the memory location addressed by H-L pair. The content of 2502 H is

the 2nd number 56 H. so 56 H is added to 49 H. sum resides in the accumulator. The instruction STA

2503 H stores the sum in the memory location 2503 H. the instruction HLT ends the program.

3.3 8-Bit Subtraction

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 82

Example

49 H 1st number

-32 H 2nd number

Result:

17 H

The 1st number 49 H is in the memory location 2501 H.

The 2nd number 32 H is in the memory location 2502 H.

The result is to be stored in the memory location 2503 H.

Program

Memory Machine Mnemonics Operands Comments

Address Codes

2000 21,01,25 LXI H, 2501 H Get address of 1st number in

H-L pair.

2003 7E MOV A, M 1st number in accumulator.

2004 23 INX H Increment content of H-L pair.

2005 86 SUB M 1st number – 2nd number.

2006 23 INX H Content of H-L pair becomes

2503 H

2006 32, 03,25 STA 2503 H Store sum in 2503 H.

2009 76 HLT

Data

2504 - 49 H

2505 – 32 H

The Sum is stored in the memory location 2503 H.

Result

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 83

2506 – 17 H

The 1st number is in the memory location 2501 is placed in H-L pair by the execution of the

instruction LXI H, 2501 H. the instruction is MOV A, M moves the content of the memory location

addressed by H-L pair to the accumulator. Thus the 1 st number 49 H which is in 2501 H is placed in

the accumulator. INX H increases the content H-L pair from 2501 to 2502 H. the instruction SUB M

subtracts the content of the memory location addressed by H-L pair from the accumulator. The 2 nd

number which is in the memory location 2502 H is subtracted from the 1 st number which is in the

accumulator. The result resides in the accumulator. The INX H increase the content of H-L pair from

2502 to 2503 H. the instruction MOV M, A transfer the content of the accumulator to the memory

location addressed by H-L pair. So the result is in the accumulator is stored in the memory location

2503 H. the instruction HLT ends the program.

3.4 Addition of Two 8-bit Numbers :Sum 16-Bit

Example

Add 98 H and 9A H

Sum = 01, 32 H

The 2nd number 32 H is in the memory location 2502 H.

The result is to be stored in 2503 and 2504 H.

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2000 21,01,25 LXI H, 2501 H Address of 1st number in H-L pair.

2003 0E, 00 MVI C, 00 MSBs of sum in register C. initial

2005 7E MOV A, M 1st number in Accumulator

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 84

2006 23 INX H Address of 2nd number 2502 in H-L 2007 86

ADD M 1st number + 2nd number.

2008 D2, OC, 20 JNC AHEAD Is carry? No, go to the label

AHEAD

200B 0C INR C Yes, increment C

200C 32, 03,25 AHEAD STA 2503 H LSB’s of sum in 2503 H.

200F 79 MOV A,C MSB’s of sum in Accumulator

2010 32, 04, 25 STA 2504 H MSB’s of sum in 2504.

2013 76 HLT Halt

Data

2501 – 98 H

2502 – 9A H

Result

2503 – 32 H, LSB’s of sum

2504 – 01 H, MSB’s of sum

The 1st instruction of the program LXI H,2501 H get the address of the 1 st number in H-L pair.

The MSBs of the sum is placed in register C. the initial value of the MSBs of the sum is kept 00. MOV

A, M transfers 1st number from the memory location 2501 H to the accumulator. INX H increases the

content of H-L pair from 2501 to 2502 H. the 2 nd number is in 2502 H. ADD M adds 1 st and 2nd

number. After the execution of the instruction JNC the instruction INR C is executed if the addition

two numbers produces a carry. The register C contains the MSBs of the sum. The accumulator

contains LSBs of the sum. The instruction STA 2503 H places the LSBs of sum in memory location

2503 H. the instruction MOV A, C move the MSBs of the sum from register C to the accumulator.

The instruction STA 2504 H stores the MSBs of the sum in 2504 H.

After the execution of the instruction JNC the program jumps to label AHEAD and executes

STA 2503 H. if the addition of two numbers does not produces a carry. The LSB of the sum is placed

in memory location 2503 H. Register C contains 00, so the execution of the instruction MOV A, C

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 85

transfers 00 in the accumulator. The instruction STA 2504 H stores 00 in the memory location 2504 H.

this is the MSB of the sum.

3.5 Decimal Addition of Two 8-bit numbers :Sum 16-Bit

Example 1

Add 84 D and 75 D - D Stands for Decimal

Sum = 159 = 01, 59 D

59 is the LSDs of the sum

01 is the MSDs of the sum.

The 1st number 84 D is in the memory location 2501 H.

The 2nd number 75 D is in the memory location 2502 H.

The sum is to be stored in 2503 and 2504 H.

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2000 21,01,25 LXI H, 2501 H Address of 1st number in H-L pair.

2003 0E, 00 MVI C, 00 MSBs of sum in register C. initial

2005 7E MOV A, M 1st number in Accumulator

2006 23 INX H Address of 2nd number 2502 in H-L 2007 86 ADD

M 1st number + 2nd number.

2008 27 DAA Decimal adjust.

2009 D2, OD, 20 JNC AHEAD Is carry? No, go to the label AHEAD

200C 0C INR C Yes, increment C

200D 32, 03,25 AHEAD STA 2503 H LSD’s of sum in 2503 H.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 86

2010 79 MOV A,C MSD’s of sum in Accumulator

2011 32, 04, 25 STA 2504 H MSD’s of sum in 2504.

2014 76 HLT Halt

Data

2501 – 84 D

2502 – 74 D

Result

2503 – 59 D, LSD’s of sum

2504 – 01 D, MSD’s of sum

3.6 Addition of Two 16-bit numbers :Sum 16-Bit or More

Example

5B98H 1st number

8E4CH 2nd number

sum 00, E 9 E 4 H

The 1st number is in the memory location 2502 H.

The 2nd number is in the memory location 2503 H.

The sum is stored in the memory location 2505 and 2507 H.

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2000 2A,01,25 LHLD 2501 H 1st 16-bit number in H-L pair..

2003 EB XCHG Get 1st number in D-E pair.

2004 2A,03,25 LHLD 2503 H 2nd 16-bit number in H-L pair..

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 87

2007 0E, 00 MVI C, 00 1st number in Accumulator

2009 19 DAD D 1st number + 2nd number.

200A D2, 0E, 20 JNC Is carry? No, go to the label AHEAD.

200D 0C INR C Yes, increment C

200E 22,05,25 AHEAD SHLD 2505 H Store LSBs of the sum in 2505 & 2506.

2011 79 MOV A,C MSD’s of sum in Accumulator

2012 32, 07, 25 STA 2507 H MSD’s of sum in 2504.

2015 76 HLT Halt

Data

2501 – 98 H, LSB of the 1st number.

2502 – 5B H, MSB of the 1st number.

2503 – 4C H, LSB of the 2nd number.

2504 – 8E H, MSB of the 2nd number.

Result

2505 – E4, LSB’s of sum.

2506 – E9, LSB’s of sum.

2507 – 00, MSB’s of sum.

3.7 8-Bit Decimal Subtraction

Example

96 D 1st number

- 38 D 2nd number

-------------------------------

Result : 58 D

Program

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 88

Memory Machine Mnemonics Operands Comments

Address Codes

2000 21,02,25 LXI H, 2502 H Get address of 2nd number in H-L pair.

2003 3E,99 MVI A, 99 Place 99 in accumulator.

2005 96 SUB M 9’s complement of 2nd number

2006 3C INR A 10s complement of 2nd number

2007 2B DCX H Content of H-L pair becomes 2503 H

2008 86 ADD M Store sum in 2503 H.

2009 27 DAA Decimal adjust

200A 32, 03, 25STA 2503 H Store result in 2503 H.

200D 76 HLT Halt

Data

2501 – 96

2502 – 38

The Sum is stored in the memory location 2503 H.

Result

2503 - 58

The instruction LXI H,2502 H places the address of the 2 nd number in H-L pair. MVI A,99

places 99 D in the accumulator. SUB M subtracts the 2 nd number (placed in 2502H) from 99 D to get

9’s complement of the 2nd number. INR A increments the content of the accumulator. Thus 10’s

complement of the 2nd number is obtained. DCX H decrements the content of the H-L pair to obtain the

address of the 1st number. ADD M adds 10’s complement of the 2 nd number to the 1st number. After

addition the result is in hexadecimal. The instruction DAA is used to get the result in decimal system.

The result is stored in the memory location 2503 H. the instruction HLT ends the program.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 89

3.8 Finds One’s Complement of an 8-Bit Number

Example

Find one’s complement of 96 H. the number in the binary form is represented as follows:

96 H = 1001 0110

(9) (6)

One’s complement = 0110 1001 = 69 H

(6) (9)

One’s complement of a number its 0 bits are replaced by 1 and 1 by 0.

The number is placed in the memory location 2501 H.

The result is stored in the memory location 2502 H.

Program

Memory Machine Mnemonics Operands Comments

Address Codes

2000 3A,01,25 LDA 2501 H Get address data in accumulator

2003 2F CMA Take it’s Complement.

2004 32, 02, 25 STA 2502 Store result in 2502 H.

2007 76 HLT Halt

Data

2504 – 96 H

Result

2502 - 69 H

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 90

The instruction LDA 2501 H transfers the number from memory location 2501 H to the

accumulator. CMA takes complement of the number. STA 2502 H stores the result in the memory

location 2502 H. HLT ends the program.

3.9 Finds One’s Complement of an 16-Bit Number

Example

Find one’s complement of 5485 H.

The number in the binary form can be represented as follows:

5485 H= 0101 0100 1000 0101

(5) (4) (8) (5)

One’s complement = 1010 1011 0111 1010 = AB7A H

(A) (B) (7) (A)

The number is in the memory location 2501 and 2502 H.

The result is to be stored in the memory location 2503 H and 2504 H.

Program

Memory Machine Mnemonics Operands Comments

Address Codes

2000 21,01,25 LXI H, 2501H Address of LSBs of the number

2003 7E MOV A, M 8 LSBs of the number in accumulator

2004 2F CMA Complement of the 8 LSBs of the number

2005 32,03,25 STA 2503 H Store 8 LSBs of result

2008 23 INX H Address of the MSBs of the number

2009 7E MOV A, M 8 MSBs of the number in accumulator

200A 2F CMA Complement of the 8 MSBs of the number

200B 32,04,25 STA2504 Store 8 MSBs of the result

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 91

200E 76 HLT Halt

Data

2501 – 85 H, LSBs of the number

2502 - 54 H, MSBs of the number

Result

2503 - 7A H, LSBs of the result

2504 - AB H, MSBs of the result

The 8 LSBs of the number are in the memory location 2501 H. The address 2501 is placed in

H-L pair. The 8 LSBs of the number are transferred from 2501 H to accumulator. The instruction

CMA takes one’s complement of 8 LSBs. The 8 LSBs of the result are stored in the memory location

2503 H. the address of 8 MSBs of the number is 2502 H, and it is placed in H-L pair. The 8 MSBs of

the number are transferred from 2502 H to the accumulator. The instruction CMA takes one’s

complement of 8 MSBs. The 8 MSBs of the result are stored in memory location 2504.

3.10 Finds Two’s Complement of an 8-Bit Number

Example

Find one’s complement of 96 H. the number in the binary form is represented as follows:

96 H = 1001 0110

(9) (6)

1’s complement = 0110 1001 = 69

(6) (9)

+ 0000 0001

---------------------

2’s complement = 0110 1010 = 6A

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 92

(6) (A)

Two’s complement of a number is obtained by adding 1 to the 1’s complement of the number.

The number is placed in the memory location 2501 H.

The result is to be stored in the memory location 2502 H.

Program

Memory Machine Mnemonics Operands Comments

Address Codes

2000 3A,01,25 LDA 2501 H Get data in accumulator

2003 2F CMA Take it’s Complement.

2004 3C INR A Take 2’s complement

2005 32, 02, 25 STA 2502 H Store result in 2502 H.

2008 76 HLT Stop

Data

2501 - 96 H

Result

2502 - 6A H

3.11 Finds Two’s Complement of a 16-Bit Number

Example

Find two’s complement of 5B8C.

The number in the binary form can be represented as follows:

5B8C = 0101 1011 1000 1100

(5) (B) (8) (C)

1’s complement = 1010 0100 0111 0011 = A473

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 93

(A) (4) (7) (3)

+ 0000 0000 0000 0001

-------------------------------------

2’s complement = 1010 0100 0111 0100 = A474

The number is stored in the memory location 2501 and 2502 H.

The result is to be stored in the memory location 2503 H and 2504 H.

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2000 21,01,25 LXI H, 2501H Address of 8 LSB’s of the number 2003 06, 00 MVI

B, 00 Use register B to store carry

2005 7E MOV A, M 8 LSBs in accumulator

2006 2F CMA 1’s complement of 8 LSBs of the number

2007 C6, 01 ADI 01 2’s complement of 8 LSBs of the number

2009 32, 03, 25 STA 2503 Store 8 LSB’s of the result

200C D2, 10, 20 JNC GO

200F 04 INR B store carry

2010 23 GO INX H Address of 8 MSB’s of the number

2011 7E MOV A, M 8 MSBs of the number accumulator

2012 2F CMA 1’s complement of 8 MSB’s of the no.

2013 80 ADD B Add carry

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 94

2014 32, 04,25 STA 2504 Store 8 MSB’s of the result

2017 76 HLT Halt

Data

2501 - 8C, LSBs of the number

2502 - 5B, MSBs of the number

Result

2503 - 74, LSBs of the result

2504 - A4, MSBs of the result

2’s complement of the number is A474

3.12 Shift an 8-Bit Number Left by One Bit

Example

Shift 65 left by one bit.

The binary representation of 65 is given below:

65 = 0110 0101

(6) (5)

result of shifting

65 left by one bit = 1100 1010 = CA

(C) (A)

To shift a number left by one bit the number is added to itself or it is doubled. If 65 is added to 65, the

result is CA as shown below:

65 = 0110 0101

+ 65 = 0110 0101

--------------------

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 95

1100 1010 = CA

The number is placed in memory 2501 H.

The result is to be stored in memory 2502 H.

Program

Memory Machine Mnemonics Operands Comments

Address Codes

2000 3A,01,25 LDA 2501 H Get data in accumulator

2003 87 ADD A shift it left by one bit

2004 32, 02, 25 STA 2502 H Store result in 2502 H.

2007 76 HLT Stop

Data

2501 - 65 H

Result

2502 – CA H

The instruction LDA 2501 H transfers the number from memory location 2501 H to the accumulator.

ADD A adds the contents of the accumulator to itself. The result is twice the number and thus the

number is shifted left by one bit.

3.13 Shift an 8-Bit Number Left by 2 Bits

Example

Shift 15 left by two bits.

The binary representation of 15 is given below:

15 = 0001 0101

(1) (5)

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 96

shift left by one bit = 0010 1010 = 2A

(2) (A)

shift the number left by 2 bits = 0101 0100 = 54

(5) (4)

The shifting of a number left by two bits can be achieved the number to itself and again adding the

sum to itself. The instruction ADD A twice.

The number is placed in the memory location 2501 H.

The result is to be stored in memory location 2502 H.

Program

Memory Machine Mnemonics Operands Comments

Address Codes

2000 3A,01,25 LDA 2501 H Get data in accumulator

2003 87 ADD A shift it left by one bit

2004 87 ADD A shift it left by one bit

2005 32, 02, 25 STA 2502 HStore result in 2502 H.

2008 76 HLT Stop

Data

2501 - 15 H

Result

2502 – 54 H

3.14 Shift a 16-Bit Number by One Bit

Example

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 97

Shift 7596 left by one bit.

The binary representation of 7596 is given below:

7596 = 0111 0101 1001 0110

(7) (5) (9) (6)

shift left by one bit = 1110 1011 0010 1100

(E) (B) (2) (C)

The number is placed in the memory location 2501 and 2502 H.

The result is to be stored in memory location 2503 and 2504 H.

Program

Memory Machine Mnemonics Operands Comments

Address Codes

2000 2A,01,25 LHLD 2501H Get data in H-L pair

2003 29 DAD H shift left by one bit

2004 22, 03, 25 SHLD 2503H store result in 2503 and 2504 H

2007 76 HLT Stop

Data

2501 - 96, LSB’s of the number

2502 - 75, MSB’s of the number

Result

2503 – 2C, LSB’s of the result

2504 - EB, MSB’s of the result

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 98

The 16-bit number has been placed in two consecutive memory locations 2501 and 2502 H. the

instruction LHLD 2501 H transfers the 16-bit number from 2501 and 2505 H to H-L pair. DAD H is

an instruction for 16-bit addition. It adds the content of H-L pair itself. The 16-bit number is shifted

left by one bit. the 16-bit result is stored in the memory locations 2503 and 2504 H by SHLD

instruction.

3.15 Shifting of a 16-Bit Number left by 2- Bits

Example

Shift 1596 left by two bits.

The binary representation of 7596 is given below:

1596 = 0001 0101 1001 0110

(1) (5) (9) (6)

shift left by one bit = 0010 1011 0010 1100 = 2B2C

(2) (B) (2) (C)

The number is placed in the memory location 2501 and 2502 H.

The result is to be stored in memory location 2503 and 2504 H.

Program

Memory Machine Mnemonics Operands Comments

Address Codes

2000 2A,01,25 LHLD 2501H Get data in H-L pair

2003 29 DAD H shift left by one bit

2004 29 DAD H shift left by one bit

2005 22, 03, 25 SHLD 2503 H store result in 2503 and 2504 H

2008 76 HLT Stop

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 99

Data

2501 - 96, LSB’s of the number

2502 - 15, MSB’s of the number

Result

2505 – 58, LSB’s of the result

2506 - 56, MSB’s of the result

3.16 Mask off Least Significant 4 Bits of an 8-Bit number

Example

Number = A6

= 1010 0110

(A) (6)

Result = A0 = 1010 0000

(A) (0)

To mask off the least significant 4 bits of a given number. The LSD of the given number A6 is

[Link] is to be cleared (masked off). The MSD of the number A6 is A. in the binary form it is 1010. it is

not to be affected. If this number is multiplied by 1111. it will not be affected. Similarly the LSD of

the number is 6. in the binary form it is represented by 0110. if it is multiplied by 0000. it becomes

0000.i.e it is cleared. Thus if the number A6 is multiplied by F0, the LSD of the number is masked

off.

Program

Memory Machine Mnemonics Operands Comments

Address Codes

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 100

2000 3A,01,25 LDA 2501H Get data in accumulator

2003 E6, F0 ANI F0 mask off the least significant 4 bits

2005 32,02, 25 STA 2502H Store result in 2502 H

2008 76 HLT Stop

Data

2501 - A6

Result

2502 - A0

The instruction LAD 2501 H transfer the content of memory location 2501 H i.e. the given

number to the accumulator. ANI F0 logically ANDs the content of the accumulator with F0 to clear

the least significant 4 bits of the number. STA 2502 H stores the result in memory locations 2502 H.

HLT stops the program.

3.17 Mask off Most Significant 4 Bits of an 8-Bit number

Example

Number = A6

= 1010 0110

(A) (6)

Result = 06 = 0000 0110

(0) (6)

To mask off 4 most significant of a number. 4 MSBs are multiplied by 0000. the least

significant bits are not to be affected and, therefore, they are multiplied by 1111. i.e. F. thus if an 8-bit

number is multiplied by 0F, the 4 most significant bits are cleared.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 101

Program

Memory Machine Mnemonics Operands Comments

Address Codes

2000 3A,01,25 LDA 2501H Get data in accumulator

2003 E6, F0 ANI F0 mask off the most significant 4 bits

2005 32,02, 25 STA 2502H Store result in 2502 H

2008 76 HLT Stop

Data

2501 - A6

Result

2503 -06

The instruction LAD 2501 H transfer the content of memory location 2501 H to the

accumulator. ANI F0 logically ANDs the content of the accumulator with F0 to clear the most

significant 4 bits of the number. STA 2502 H stores the result in memory locations 2502 H. HLT

stops the program.

3.18 To Find Larger of Two Numbers

Example

Find the larger of 98 H and 87 H.

The first number 98 H is placed in the memory location 2501 H.

The 2nd number 87 H is placed in the memory location 2502 H.

The result is stored in the memory location 2503 H.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 102

The numbers are represented in hexadecimal system. The 1 st number is moved from its memory

location to the accumulator. It is compared with 2 nd number. The larger of the two is then placed in the

accumulator. From the accumulator the larger number is moved to the desired memory location.

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2000 21,01,25 LXI H, 2501H Address of 1st number in H-L pair

2003 7E MOV A, M 1st number in accumulator

2004 23 INX H Address of 2nd number in H-L pair

2005 BE CMP M Compare 2ns number with 1st number.

Is 2nd number is greater than 1st?

2006 D2, 0A,20 JNC AHEAD No, larger number is in accumulator.

Go to AHEAD

2009 7E MOV A, M Yes, get 2nd number in accumulator 200A 32, 03,25 AHEADSTA

2503H Store large number in 2503 H.

20D 76 HLT Halt

Data

2501 - 98 H

2502 – 87 H

Result

2503 - 98 H and it stored in memory location 2503 H.

The 1st step of the program is LXI H, 2501 H. the address of the memory location of the 1 st

number is 2501 H. i.e. 2501 is placed in H-L pair. The next instruction of the program is MOV A, M.

the execution of this instruction moves the content of the memory to the accumulator. Now the 1 st

number i.e. 98 is in the accumulator. INX H increases the content of H-L pair by 1. the content of H-L

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 103

pair is increased from 2501 to 2502. the address of the memory location for 2 nd number is 2502. the

instruction CMP M means that the content of the memory location 2502 is compared with the content

of accumulator. The instruction JNC is executed and the program jumps to the instruction STA 2503.

the larger number is in the accumulator. The instruction STA 2503 H stores the larger number.

3.19 Find the Largest Number in a Data Array

Example

The numbers in a series are : 98, 75 and 99. the numbers are placed in the memory

location 2501 to 2503 H. the result is stored in the memory location 2504 H.

The 1st of the series is placed in accumulator and it is compared with the 2 nd number. The

larger of two number is placed in the accumulator. Again this number is placed in the accumulator is

compared with the 3rd number of series and larger number is placed in the accumulator. All the

numbers of the series are compared and the largest number is stored in the desired memory location.

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2000 21,01,25 LXI H, 2500 H Address of count in H-L pair

2003 4E MOV C, M Count in register C

2004 23 INX H Address of 1st number in H-L pair

2005 7E MOV A, M 1st number in accumulator

2006 0D DCR C Decrement count

2007 23 LOOP INX H Address of next number

2008 BE CMP M Compare next number with

previous maximum.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 104

Is next number > previous

maximum?

2009 D2,0D,20 JNC AHEAD No, larger Number is accumulator.

Go to the label AHEAD.

200C 7E MOV A, M Yes, get larger number in

accumulator.

200E C2. 07, 20 JNZ LOOP

2011 32, 50, 24 STA 2450 H Store result in 2450 H.

2014 76 HLT Stop.

Data

2500 - 03 (count)

2501 - 98

2502 - 75

2503 - 99

Result

2450 - 99

The memory location 2500 H contains the count of the series. 2500 H is placed in H-L pair.

The next instruction MOV C, M places the count in register C. INX H increase the content of H-L pair

by one. Now 2501 is in H-L pair. The 1 st number of the series resides in the memory location 2501 H.

MOV A, M moves the 1st number (98) in accumulator. DCR C decreases the count from 03 to [Link]

means that now there are two more numbers in series. INX H increases the content of the H-L pair

from 2501 to 2503 H. the 2nd number of the series is in the memory location 2502 H. CMP M

compares content of the accumulator(1st number) with the content of 2502 H(2nd number).

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 105

The 1st number 98 is greater than the 2nd number 75, there will be no carry. The instruction JNC

will be executed and program will move the label AHEAD. The count will be decreased from 02 to 01.

it indicates that now there is one number left in the series. As the content of register C is not zero. The

program will move to the label LOOP. The INX H will change the content of H-L pair from 2502 to

2503 H. 2503 H is the address of memory location for 3 rd number. Again CMP M will compare the

content of accumulator (98) with the content of 2503 H. the content of 2503 H is 99 which is greater

than the content of accumulator. In this case there will be a carry. After JNC instruction the program

will take up the instruction MOV A, M the larger number (99) will move from the memory location

2503 H to accumulator. DCR C will reduce the content of register C from 01 to 00. as the content of

register C is 00, the program will not jump to the label LOOP. The instruction STA 2450 H will

executed. The largest number (99) which is in the accumulator will be stored in the memory location

2450 H. the instruction HLT will end the program.

3.20 An Alternative Program To Find the Largest Number from a series of Number

Example

The numbers in a series are : 98, 75 and 99. the count is store din memory location 2500

H. the numbers are placed in the memory location 2501 to 2503 H. the result is stored in the memory

location 2450 H.

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2400 21,01,25 LXI H, 2500H Address of count in H-L pair

2403 4E MOV C, M Count in register C

2404 97 SUB A Get 00 in accumulator.

2405 23 LOOP INX H Address of the next number of

the series

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 106

2406 BE CMP M Compare next number with previous

maximum. Is next number > previous

maximum?

2407 D2,0B,24 JNC AHEAD No, larger Number is accumulator. Go

to the label AHEAD.

240A 7E MOV A, M Yes, get larger number in accumulator

240B 0D AHEAD DCR C Decrement count

240C C2,05,24 JNZ LOOP

240F 32, 50, 24 STA 2450 H Store result in 2450 H.

2412 76 HLT Stop.

Data

2504 - 03 (count)

2505 - 98

2506 - 75

2507 - 99

Result

2450 - 99

The memory location 2500 H contains the count of the series. 2500 H is placed in H-L pair.

The instruction MOV C, M places the count in register C. in example count is 03. the instruction SUB

A makes the content of accumulator 00. As 00 is the smallest 8-bit number, it is taken as initial value

for comparison. INX H point out the 1st number of the series. CMP M compares 1st number with 00. as

the 1st number with 00. as the 1 st number is greater than 00, there is a carry, and after the execution of

JNC, the instruction MOV A, M is executed. The first number i.e. 98 is now transferred to the

accumulator. Then the count in register C is decremented and the program is transferred to the label

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 107

LOOP. Then INX H point the address of the 2 nd number of the series(75). The 1 st number (98) is larger

than 2nd number, there is no carry, and after the execution of the instruction JNC the program jumps to

the label AHEAD. The 1st number being the larger number is retained in accumulator. The count is

decremented and program jumps to LOOP again process the third number of the series.

3.21 To Alternative Program to Arrange an Array of Data in Ascending (Descending

Order)

Example

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2000 21,00,25 LXI H, 2500H Address for count

2003 4E MOV C, M Count for number of passes register C

2004 21,00,25 BACKLXI H,2500

2007 56 MOV D,M Count for number of comparison

in register D

2008 23 INX H

2009 7E MOV A, M 1st Number in accumulator.

200A 23 LOOP INX H Address of next number.

200B 46 MOV B, M Next number in Register B

200C B8 CMP B Compare next number with

previous greatest number

200D D2, 16, 20 JNC AHEAD if previous greatest number > next

number, go to AHEAD

2010 2B DCX H

2011 77 MOV M, A Place smaller of the two compared

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 108

numbers in memory

2012 78 MOV A, B Place greater of the two compared

numbers in accumulator

2013 C3,18, 20 JMP GO

2016 2B AHEAD DCX H

2017 70 MOV M, B Place smaller of the two compared

numbers in memory

2018 23 GO INX H

2019 15 DCR D Decrease the count for comparison

201A C2,0A,20 JNZ LOOP

201D 77 MOV M, A Place the greatest number after a

pass in the memory

201E 0D DCR C Decrease the count for pass

201F C2,04,20 JNZ BACK Store result in 2450 H.

2022 76 HLT Stop

Data Result

2500 – Count 04

2501 – 60 15

2502 – 40 25

2503 – 50 40

2504 – 15 50

2505 – 25 60

3.22 To Find Smaller of Two Numbers

Example

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 109

Find the smaller of 84 H and 99 H.

Find the larger of 98 H and 87 H.

The first number 84 H is placed in the memory location 2501 H.

The 2nd number 99 H is placed in the memory location 2502 H.

The result is stored in the memory location 2503 H.

The numbers are represented in hexadecimal system. The 1 st number is moved from its memory

location to the accumulator. It is compared with 2 nd number. The smaller of the two is then placed in

the accumulator. From the accumulator the smaller number is moved to the desired memory location.

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2000 21,01,25 LXI H, 2501H Address of 1st number in H-L pair

2003 7E MOV A, M 1st number in accumulator

2004 23 INX H Address of 2nd number in H-L pair

2005 BE CMP M Compare 2ns number with 1st number.

Is 2nd number is greater than 1st?

2006 D2, 0A,20 JC AHEAD Yes, smaller number is in

accumulator. Go to AHEAD

2009 7E MOV A, M Yes, get 2nd number in

accumulator

200A 32, 03,25 AHEAD STA 2503H 4 Store smaller number in 2503 H.

20D 76 HLT Halt

Data

2502 - 84 H

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 110

2502 – 99 H

Result

2503 - 84 H and it stored in memory location 2503 H.

2501 H is the address of the memory location for the 1 st number. The instruction LXI H, 2501

H places 2501 H in H-L pair. The next instruction MOV A, M moves the content of the memory

location 2501 H to accumulator. Thus 1 st number 84 H (example) is now in accumulator. The

instruction INX H increases the content of H-L pair from 2501 to 2502 H. the instruction CMP M

compares the content of the accumulator(1 st number) with the content of the memory location 2502

H( 2nd number).if the 1st number is smaller than the 2nd number. There is a carry. The instruction JC is

executed and the program jumps to STA 2503 H. the smaller number (84 H) is in the accumulator and

the instruction STA 2503 H stores it in the memory location 2503 H. the instruction HLT will end the

program.

3.23 Find the Smallest Numbers in a Data Array:

Example

The numbers of a series are: 86, 58 and 75.

As there are three numbers in the series, count = 03.

The count is placed in the memory location 2500 H.

The numbers are placed in the memory location 2501 to 2503 H.

The result is to be stored in the memory location 2450 H.

The 1st number of the series is placed in the accumulator and it is compared with the 2 nd

number in which is in the memory. The smaller of the two is placed in the accumulator. Again this

number which is in the accumulator is compared with the 3 rd number of series and smaller number is

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 111

placed in the accumulator. This process of comparison is repeated till all the numbers of the series are

compared and the smallest number is stored in the desired memory location.

The memory location 2500 H contains the count of the series. Count is 03. 2500 is placed in H-

L pair. The instruction MOV C, M places the count in register C. INX H increases the content of H-L

pair from 2500 to 2501 H. the first number of series resides in the memory location 2501 H. MOV A,

M moves the 1st number (86) in the accumulator. DCR C decreases the count from 03 to 02, INX H

increases the content of H-L pair from 2501 to 2502 H. the 2 nd number of the series is in 2502 H. CMP

M compare the content of the accumulator(1 st number) with the content memory location 2502 H(2 nd

number).

The 1st number is greater than the 2 nd number 58. there is no carry, the instruction MOV A, M

will be executed. The small number 58 will be placed in the accumulator. DCR C will decrease count

from 02 to 01. the content of register C is non zero, the program will jump to the label LOOP. The

INX H will change the content of H-L pair from 2502 to 2503 H. the third number of series is in 2503

H. again CMP M will compare the content of accumulator (58) with the content of 2503 H. the content

of 2503 H is 75 which is greater than the content of accumulator. There will be a carry. After the

execution of instruction JC AHEAD the program will jump to the label AHEAD. The content of the

accumulator will remain as it is. DCR C will reduce the count from 01 to 00. the content of register C

is zero. Program will not jump. The smallest number (58) is in the accumulator will be stored in the

memory location 2450 H. the instruction HLT will end the program.

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2000 21,00,25 LXI H, 2500 H Get address for count in H-L pair

2003 4E MOV C, M Count in register C

2004 23 INX H Get address of 1st number in H-L pair

2005 7E MOV A, M 1st number in accumulator

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 112

2006 0D DCR C Decrement count

2007 23 LOOP INX H Address of next number in H-L pair

2008 BE CMP M Compare next number with previous

smallest. Is previous smallest less than

next number?

2009 DA,0D,20 JC AHEAD Yes, smaller number in accumulator.

Go to AHEAD

200C 7E MOV A, M No, get next number in accumulator.

200D 0D DCR C Decrement count

200E C2,07,20 JNZ LOOP

2011 32, 50,24 AHEAD STA 2450 H Store smaller number in 2450 H.

2014 76 HLT Halt

Data 2500 – 03

2501 – 86 H

2502 – 58 H

2503 – 75 H

Result

2450 - 58 H

3.24 An Alternative Program To Find Smallest Number from a series of Numbers

Example

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 113

The number of a series are: 86, 58 and 75. there are three numbers in the series, count = 03. the

count is stored in the memory location 2500 H. the numbers are stored in the memory location 2501 to

2503 H.

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2000 21,00,25 LXI H, 2500 H Get address for count in H-L pair

2003 4E MOV C, M Count in register

2004 3E,FF MVI A, FF Get FF in accumulator

2006 23 LOOP INX H Address of the next number of the series

2007 CMP M Compare next number with

previous smallest. Is next number

< previous smallest?

200A D2, 0A,20 JC AHEAD No, get smaller number is in

accumulator. Go to AHEAD.

200B 7E MOV A, M Yes,get smaller number in

accumulator

200C AHEAD DCR C Decrement count.

200D JNZ LOOP

2010 32, 03,25 AHEAD STA 2450 H Store smaller number in 2450 H.

2013 76 HLT Halt

Data

2500 - 03 H

2501 – 86 H

2502 – 58 H

2503 – 75 H

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 114

Result

2450 - 58 H

The memory location 2500 H contains the count of the series. 2500 H is placed in H-L pair.

MOV C, M, M transfer the count to register C. MVI A, FF brings FF into the accumulator. As FF is

the largest 8-bit number, it is taken an initial number for comparison. INX H points out the address of

the 1st number. CMP M compares the content of the accumulator i.e. FF with the 1 st number (86

example). As FF is greater than 86, there is no carry. After the execution of the instruction JC, the

instruction MOV A, M is executed to transfer the 1 st number(86) to the accumulator. Then the count is

decremented and the program jumps to the label LOOP. Now INX H points out the address of the 2 nd

number(58 H). As58 H is smaller than 86H, 58 H is transferred to the accumulator. Again the count is

decremented and the program goes back to the label LOOP. This time INX H points out the 3 rd

number (75 H). As 58 is smaller than 75, there will be a carry. After the execution of JC the program

will jump to AHEAD, and the count will be decremented. 58 H will remain in the accumulator. The

smallest number of the series is obtained and stored in the memory location 2450 H.

3.25 Sum of a Series of 8-Bit Numbers; Sum:8 Bit

Example

Add 16, 2B, 39 and 12 H.

The numbers are placed in the memory locations 2501 to 2504 H.

The sum is to be stored in the memory location 2450 H

As there are 4 numbers in the series, count = 04

The initial value of the sum is made 00. the number of the series are taken one by one and

added to the sum.

Program

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 115

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2400 21,00,25 LXI H, 2500 H Address for the count in H-L pair

2403 4E MOV C, M Count in register C.

2404 3E,00 MVI A, 00 Initial value of sum = 00

2406 23 LOOP INX H Address of the next data in H-L pair.

2407 86 ADD M Previous sum + next number

2408 0D DCR C Decrement count

2409 C2,06,24 JNZ LOOP Is count = 0? No, Jump to LOOP

240C 32,50,24 AHEAD STA 2450 H Store sum in 2450 H..

240F 76 HLT Stop

Data

2500 - 04 H

2501 – 16 H

2502 – 2B H

2503 – 39 H

2504 - 12 H

Result

2450 - 8C H

3.26 Sum of a Series of 8-Bit Numbers; Sum:16 Bit

Example

Add 45, 98, 8A and E2 H. these are hexadecimal numbers.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 116

The numbers are placed in the memory locations 2501 to 2504 H, and count in 2500 H.

The sum is to be stored in the memory location 2450 and 2451H.

As there are 4 numbers in the series, count = 04. The initial value of the sum is made 00. the

number of the series are taken one by one and added to the sum.

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2400 21,00,25 LXI H, 2500 H Address for the count in H-L pair

2403 4E MOV C, M Count in register C.

2404 3E,00 MVI A, 00 LSBs of sum = 00 (initial value)

2406 47 MOV B, A MSBs of sum = 00 (initial value)

2407 23 LOOP INX H Address of next data in H-L pair

2408 86 ADD M Previous sum + next number

2409 D2,0D,24 JNC AHEAD Is carry ? No, go to AHEAD

240C 04 INR B Yes, add carry to MSBs of sum

240D 0D AHEAD DCR C Decrement count

240E C2, 07, 24 JNZ LOOP Is count = 0? No, jump to LOOP

2411 32, 50, 24 STA 2450 H Store LSBs of the sum in 2450 H

2414 78 MOV A, B Get MSBs of sum in accumulator

2415 32, 51, 24 STA 2451 H Store MSBs of sum in 2451 H

2418 76 HLT Stop

Data

2500 - 04 H

2501 – 45 H

2502 – 98 H

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 117

2503 – 8A H

2504 - E2 H

Result

2451 - 49 H, LSBs of sum

2452 – 02 H, MSBs of sum

The count is placed in register C. the LSBs of the sum reside in the accumulator, and MSBs of the sum

in register B. initial value of the LSBs and MSBs of the sum are made 00. the 1 st number is added to

the initial sum. Count is decreased by one and the program jumps to LOOP. The address of the 2 nd

number is placed in H-L pair. ADD M adds 2 nd number to the previous sum which is in the

accumulator. If there is any carry after addition, that is stored in register B. the process is repeated and

the remaining numbers of the series are added. The LSBs of the sum is stored in memory location

2450 H and MSBs of the sum in 2451 H.

3.27 Sum of a Series of 8-Bit Decimal Numbers; Sum:16 Bit

Example

Add 65, 46, 35 and 98 D. these are decimal numbers. D stands for decimal.

Sum = 0244 D

The numbers are placed in the memory locations 2501 to 2504 H

The sum is to be stored in the memory location 2450 and 2451.

The instruction DAA is used in the program for decimal adjustment. It is used after ADD

instruction.

Program

Memory Machine Labels Mnemonics Operands Comments

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 118

Address Codes

2400 21,00,25 LXI H, 2500 H Address for the count in H-L pair

2403 4E MOV C, M Count in register C.

2404 3E,00 MVI A, 00 LSBs of sum = 00 (initial value)

2406 47 MOV B, A MSBs of sum = 00 (initial value)

2407 23 LOOP INX H Address of next data in H-L pair

2408 86 ADD M Sum = sum + data

2409 27 DAA Decimal adjustment

2409 D2,0E,24 JNC AHEAD Is carry ? No, go to AHEAD

240C 04 INR B Yes, add carry to MSBs of sum

240D 0D AHEADDCR C Decrement count

240E C2, 07, 24 JNZ LOOP Is count = 0? No, jump to LOOP

2411 32, 50, 24 STA 2450 H Store LSBs of the sum in 2450 H

2414 78 MOV A, B Get MSBs of sum in accumulator

2415 32, 51, 24 STA 2451 H Store MSBs of sum in 2451 H

2418 76 HLT Stop

Data

2500 - 04 H

2501 – 65 H

2502 – 46 H

2503 – 35 H

2504 - 98 H

Result

2453 - 44 D, LSBs of sum

2454 – 02 D, MSBs of sum

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 119

3.28 8-Bit Division

Example

Divide 489B by 1A.

These are hexadecimal numbers. The dividend is a 16-bit number and divisor 8-bit number. If the

dividend of a problem is an 8-bit number. it is extended to a 16-bit number by placing zeros in MSBs

positions.

The dividend is placed in the memory location 2501 and 2502 H.

The divisor is placed in the memory location 2503 H

The results are stored in the memory location 2504 and 2505 H

The quotient is stored in the memory location 2504 H.

The remainder is stored in the memory location 2505 H.

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2400 2A,01,25 LHLD 2501 H Get dividend in H-L pair

2403 3A,03,25 LDA 2503 H Get divisor from 2503 H

2406 47 MOV B, A Divisor in register B

2407 0E,08 MVI C, 08 Count = 08 in register C

2409 29 LOOP DAD H Shift dividend and quotient in

accumulator

240A 7C MOV A, H MSB of dividend in accumulator

240B 90 SUB B Subtract divisor from most significant bits

of dividend

240C DA, 11, 24 JC AHEAD Is most significant part of dividend >

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 120

divisor? No, go to AHEAD

240F 67 MOV H, A MSB of dividend in register H

2410 2C INR L Yes, add 1 to quotient

2411 0D AHEAD DCR C Decrement count

2412 C2, 09, 24 JNZ LOOP Is count = 0? No, jump to LOOP

2415 22, 04, 25 SHLD 2504 H Store quotient in 2504 and remainder

in 2505H

2418 76 HLT Stop

Data

2501 – 9B H, LSBs of dividend

2502 – 48 H, MSBs of dividend

2503 – 1A H, Divisor

Result

2504 – F2, Quotient

2505 – 07, remainder

The count register C is kept 08. the trial subtraction is done 8 times and an 8-bit quotient is

obtained. The instruction DAD H shifts dividend and quotient left by one bit. Due to shift of dividend

the bit positions in register L fall vacant. In the vacant bit positions quotient is stored. The MSB of the

dividend should be zero. Otherwise it will be shifted to carry bit. If a problem contain MSB not equal

to zero. It will be solved by splitting it in two parts. Shifting of dividend before subtraction is not done

in ordinary division.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 121

3.29 Multibyte Addition

Example

3 A 9 C 8 A 6 7 H, 1st Number

+ 9 B 4 7 6 C 8 B H, 2nd Number

------------------------------------------

D 5 E 3 F 6 F 2 H, Sum

A byte consist of 8-bits. The above example two multibyte hexa numbers are to be added. Each

number consist of 4 bytes. An 8-bit microcomputer takes one byte of the numbers at a time and adds

them with carry. A counter is initiated to count the byte. In example count = 4.

The count is placed in the memory location 2500 H

The 1st number is placed in the memory locations 2501 to 2504 H.

The 2nd number is placed in the memory locations 2601 to 2604 H.

The sum is placed in the memory locations 2501 to 2504 H

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2400 21,00,25 LXI H, 2500 H Address of byte count in H-L pair

2403 4E MOV C, M Byte count in register C

2404 23 INX H Address of 1st byte of 1st number

2405 11, 01, 26 LXI D, 2601 H Address of 1st byte of 2nd number

2408 B7 ORA A Clear carry

2409 1A LOOP LDAX D Get byte of 2nd number in accumulator

240A 8E ADC M Byte of 2nd number + byte of 1st

number + carry

240B 77 MOV M, A Store sum in memory addressed

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 122

by H-L pair.

240C 23 INX H Increment the content of H-L pair

240D 13 INX D Increment the content of D-E pair

240E 0D DCR C Decrement count

240F C2, 09, 24 JNZ LOOP Is count = 0? No, jump to LOOP

2412 76 HLT Stop

Data

2500 – 04

2501 – 67 2601 – 8B

2502 – 8A 2602 – 6C

2503 – 9C 2603 - 47

2504 – 3A 2604 – 9B

the sum is stored in the memory locations 2501 to 2504 H.

Result

2501 – F2

2502 – F6

2503 – E3

2504 – D5

3.30 Multibyte Subtraction

Example

E C 8 B 9 4 5 A 1st Number

- 4 B 3 C A 8 B 9 2nd Number

------------------------
Department of Computer Science, Thanthai Hans Roever College, Perambalur
 Microprocessor and It’s Applications 123

A14EEBA1

The count is placed in the memory location 2500 H

The 2nd number is placed in the memory locations 2501 to 2504 H.

The 1st number is placed in the memory locations 2601 to 2604 H.

The result is placed in the memory locations 2501 to 2504 H

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2400 21,00,25 LXI H, 2500 H Address of byte count in H-L pair

2403 4E MOV C, M Byte count in register C

2404 23 INX H Address of 1st byte of 1st number

2405 11, 01, 26 LXI D, 2601 H Address of 1st byte of 2nd number

2408 B7 ORA A Clear carry

2409 1A LOOP LDAX D Get byte of 2nd number in accumulator

240A 9E SBB M Subtract byte of 2nd number from

byte of 1st number with borrow

240B 77 MOV M, A Store sum in memory addressed

by H-L pair.

240C 23 INX H Increment the content of H-L pair

240D 13 INX D Increment the content of D-E pair

240E 0D DCR C Decrement count

240F C2, 09, 24 JNZ LOOP Is count = 0? No, jump to LOOP

2412 76 HLT Stop

Data

2500 – 04

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 124

2501 – B9 2601 – 5A

2502 – A8 2602 – 94

2503 – 3C 2603 – 8B

2504 – 4B 2604 – EC

Result

2501 – A1

2502 – EB

2503 – 4E

2504 – A1

3.31 Ascending Order

Example

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

LOOP2 MVI B, 00

LXI H, 4150

MOV C, M

DCR C

INX H

MOV A, M

LOOP INX H

CMP M

JC LOOP1

MOV D, M

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 125

MOV M, A

DCX H

MOV M, D

INX H

MVI B, 01

LOOP1 DCR C

JNZ LOOP

DCR B

JZ LOOP2

HLT

Data

4150 - 03

4151 – 0A

4152 – 08

4153 – 0B

Result

4151 - 08

4152 – 0A

4153 – 0B

3.32 Descending Order

Example

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 126

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

LOOP2 MVI B, 00

LXI H, 4150

MOV C, M

DCR C

INX H

MOV A, M

LOOP INX H

CMP M

JNC LOOP1

MOV D, M

MOV M, A

DCX H

MOV M, D

INX H

MVI B, 01

LOOP1 DCR C

JNZ LOOP

DCR B

JZ LOOP2

HLT

Data

4150 - 03

4151 – 0A

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 127

4152 – AA

4153 – 0C

Result

4151 - AA

4152 – 0C

4153 – 0A

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 128

PERIPHERAL DEVICES AND INTERFACING

4.1 Introduction

A microprocessor Combined with memory and input/output devices forms a microcomputer.

The microprocessor is the heart of a microcomputer. Memories and input/output devices are interfaced

to microprocessor to form a microcomputer..

4.2 Address Space Partitioning

Intel 8085 uses a 16-bit wide address bus for addressing memories and I/O devices. Using 16-

bit wide address bus it can access 216 = 64K bytes of memory and I/O devices. There are two schemes

for allocation of address to memories and input/output devices.

i. Memory mapped I/O scheme

ii. I/O Mapped I/O scheme

i. Memory Mapped I/O Scheme:

In Memory Mapped I/O scheme there is only one address space. Address space is defined as

the set of all possible addresses that a microprocessor can generate. Some addresses are assigned to

memories and some addresses to I/O devices. Suppose memories locations are assigned the addresses

2000 to 24FF. one address is assigned to each memory location. Any one of these addresses cannot be

assigned to I/O device. The addresses for I/O devices are different from the addresses which have been

assigned to memories. For example, 2500, 2501, 2502 etc.

All the data transfer instructions of the microprocessor can be used for both memory as well as

I/O devices. For example, MOV A, M will be valid for data transfer from the memory location or I/O

device whose address is in H-L pair. If the H-L pair contains the address of memory location, data will

be transferred from the memory location to the accumulator.

ii. I/O Mapped I/O Scheme:

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 129

In this scheme the addresses assigned to memory locations can also be assigned to I/O devices.

Since the same address may be assigned to a memory location or an I/O device. The microprocessor

must issue a signal to distinguish whether the address on the address bus is for a memory location or

an I/O device. When the signal is high the address on the address bus is for an I/O device. When the

signal is low the address on the address bus is for a memory location. Two extra instructions IN and

OUT are used to address I/O devices . The IN instruction is used to read the data of an input device.

The OUT instruction is used to send data to an output device.

4.3 Memory and I/O Interfacing

Several memory chips and I/O devices are connected to a microprocessor. Fig. 7.1 shows a

schematic diagram to interface memory chips or I/O devices to a microprocessor. An address decoding

circuit is employed to select the required I/O device or a memory chip. Fig 7.2 shows a schematic

diagram of a decoding circuit. If IO/M’ is high the decoder 2 is activated and the required I/O device is

selected.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 130

Memory Interfacing:

The address of a memory location or an I/O device is sent out by the microprocessor. The

corresponding memory chip or I/O device is selected by a decoding circuit. A 1 to 8 lines decoder will

be illustrated. Fig. 7.3 shows the interface of memory chips through 74LS138.G1, G2A and G2B are

enable signals. To enable 74LS138, G1 should be high, and G2A and G2B should be low. A, B and C

are select lines. By applying proper logic to select lines any one of the outputs can be selected. Y0,

Y1….Y7 are 8 output lines. An output lines goes low when it is selected. Other output lines remains

high. Table 7.1 shows the truth table for 74LS138. when G1 is low or G2A is high or G2B is high, all

output lines become high. Thus 74LS138 acts as decoder only when G1 is high, and G2A and G2B are

low.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 131

The memory locations for EPROM 1 will lie in the range 0000 to 1FFF. These are the memory

locations for ZONE 0 for the memory chip which is connected to the output line Y0 of the decoder.

Similarly for ZONE 1 is 2000 to 3FFF and for ZONE 7 is E000 to FFFF. Table 7.2 shows the memory

locations for various zones.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 132

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 133

The entire memory address (64K for 8085) has been divided into 8 zones. Address lines A 15,

A14 and A13 have been applied to the select lines A, B, and C of the 74LS138. the logic applied to these

lines selects a particular memory device, an EPROM or a RAM. Other address lines A 0, A1, A2……A12

go directly to the memory chip. IO/M’ is connected to G2B. when IO/M’ goes low for memory

read/write operation. G2B goes low. G1 is connected to +5Vd.c, supply and G2A is grounded.

I/O Interfacing:

Fig 7.4 shows the interface of I/O devices through decoder 74LS138. as the address of an I/O

device is of 8-bits,only A8-A15 lines of address bus are used for I/O addressing. The address lines A 8,

A9 and A10 have been applied lines A, B and C of the 74LS138. the address lines A11-A15 are applied to

G2B through a NAND gate. G2B becomes low only when all address lines A 11-A15 are high. G2A is

grounded. IO/M’ is connected to G1. when IO/M’ goes high for I/O read/ write Operation. G1 goes

high.

A14 A13 A12 A11 A10 A9 A8 Selected Corres- I/O Device

Output ponding
1 1 1 1 1 0 0 0 Yo F8 Input Device 1
Table 7.3
1 1 1 1 1 0 0 1 Yt F9 Input Device 2
Address of I/O
1 1 1 1 1 0 1 0 Y2 FA Input Device 3
device
1 1 1 1 1. 0 1 1 Y3 FB Output Device 1

1 1 1 1 1 1 0 0 Y4 FC Output Device 2 connected to

1 1 1 1 1 1 0 1 Y5 FD Output Device 3 74LS138

1 1 1 1 1 1 1 0 Y6 FE Unused
1 1 1 1 1 1 1 1 FF Unused
Y7

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 134

4.4 Data Transfer Schemes

In a microprocessor-based system or in a computer data transfer takes place between two

devices such as microprocessor and memory, microprocessor and I/O devices, and memory and I/O

devices. Usually, memories are compatible with microprocessor because the same technology is

employed in the manufacturing of both memories and microprocessors.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 135

A microprocessor-based system or a computer may have several I/O devices of different speed.

A slow I/O device cannot transfer data when microprocessor issues instruction for the same because it

takes some time to get ready. To solve the problem of speed mismatch between a microprocessor and

I/O devices a number of data transfer techniques have been developed. The data transfer schemes are

classified into the following two broad categories.

i. Programmed data transfer schemes.

ii. DMA (Directly Memory Access) Data transfer scheme.

i. Programmed Data Transfer Schemes

In Programmed data transfer schemes are controlled by the CPU. Data are transferred from an

I/O deice to the CPU. The programs are executed by the CPU when an I/O device is ready to transfer

data. The microprocessor executes the program to transfer data programmed data transfer schemes are

employed when small amount of data are to be transferred. The programmed data transfer schemes are

classified into the following three categories.

i. Synchronous data transfer scheme

ii. Asynchronous data transfer scheme

iii. Interrupt driven data transfer scheme

Synchronous Data Transfer: Synchronous means “ at the same time.” The device which sends data

and the device with receives data are synchronized with the same clock. When the CPU and I/O

devices match in speed, this technique of data transfer is employed. The IN instruction is used to read

data from an input device or input port. The OUT instruction is used to send data from the CPU to an

output device or output port. As the CPU and the I/O device match in speed, the I/O device is ready to

transfer data when IN or OUT instruction is issued by the CPU.

Asynchronous Data Transfer: Asynchronous means “at irregular intervals”. In this method data

transfer is not based on predetermined timing pattern. This technique of data transfer is used when the

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 136

speed of an I/O device does not match the speed of the microprocessor. In this technique the status of

the I/O device i.e. whether the device is ready or not, is checked by the microprocessor before the data

are transferred. The microprocessor initiates the I/O device to get ready and then continuously checks

the status of the I/O device till the I/O device becomes ready to transfer data. When I/O device ready,

the microprocessor sends instructions to transfer data. This method of data transfer is also called

handshaking mode of data transfer because some signals are exchanged between the I/O device and

microprocessor before the actual data transfer.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 137

The microprocessor issues an initiating signal to the I/O device to get ready (or to start). When

I/O device becomes ready it sends signals to the processor to indicate that it is ready. Such signals are

called handshake signals.

Interrupt Driven Data Transfer: In this scheme the microprocessor initiates an I/O device to get

ready, and then it executes its main program. When I/O device becomes ready to transfer the data. It

sends a high signal to the microprocessor through a special input line called a interrupt line.

Fig. 7.7 shows the interfacing of an A/D converter to transfer data employing interrupt driven

data transfer scheme. The microprocessor sends first the start of conversion signal, S/C to the A/D

converter. Thereafter, the microprocessor executes its main program. A/D converter is a slow device

compared to a microprocessor. It takes some time to convert analog signal to equivalent digital

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 138

quantity. When A/D converter completes the task of conversion, it makes end of conversional signal,

E/C high. The E/C signal is connected to an interrupt line of the microprocessor. When interrupt line

goes high, the microprocessor takes all necessary steps to transfer data from the A/D converter. After

completing the data transfer the microprocessor returns back to execute the main program that it was

executing prior to the interrupt.

ii. DMA (Directly Memory Access) Data transfer scheme

In DMA data transfer scheme CPU doest not participate. Data are directly transferred from an

I/O device to the memory vice versa. The data transfer is controlled by the I/O device or a DMA

controller. This schemes is large amount of data are to be transferred. If bulk data are transferred

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 139

through the CPU, I/O device which wants to send data using DMA technique, sends the HOLD signal

to the CPU. The CPU send a hold acknowledge signal to the I/O device to indicate that it has received

eth HOLD request and it will give up the busses in the next machine cycle. The I/O devices take over

the control of buses and directly transfers data to the memory or reads from the memory.

DMA data transfer scheme is a faster scheme as compared to programmed data transfer

scheme. It is used to transfer data from mass storage devices such as hard disk, floppy disks etc. DMA

data transfer schemes are of the following two types:

i. Burst mode of DMA data transfer

ii. Cycle stealing techniques of DMA data transfer

Burst mode of DMA data transfer: A scheme of DMA data transfer, in which the I/O device

withdraws the DMA request only after all the data bytes have been transferred, is called burst mode

data transfer.

Cycle Stealing Technique: In this technique a long block of data is transferred by a sequence of DMA

cycles. In this method after transferring one byte or several bytes. The I/O device withdraw DMA

request.

4.5 Interrupts of Intel 8085

The Intel 8085 has five interrupt inputs namely TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.

The TRAP has the highest priority, followed by RST 7.5, RST 6.5 and RST 5.5. The INTR has the

lowest priority. When interrupts are to be used they are enabled by software using the instruction EI

(Enable Interrupt) in the main program.

Fig. 7.8 shows the schematic diagram of interrupts of Intel 8085. The instruction EI sets the

interrupt enable flip-flop to enable the interrupts. The use of the instruction EI enables all the

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 140

interrupts. The instruction DI (Disable Interrupt) is used to disable interrupts. The DI instruction resets

the interrupt enable flip-flop and disables all the interrupts except nonmaskable interrupt TRAP, see

Fig. 7.8.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 141

Hardware and Software Interrupts: Interrupt caused by I/O device are called hardware interrupt.

The normal operation of a microprocessor can also be interrupted by special instructions. Such

interrupt is called a software interrupt. RST instruction of the 8085 are used for software interrupt.

When RST instruction is inserted in a program. The program is executed up to the point where RST

has been inserted.

The internal abnormal or unusual conditions which prevent the normal processing sequence of

a microprocessor are called exceptions.

When several I/O devices are connected to the INTR interrupt line, an external hardware is

used to interface I/O devices. The external hardware circuit generates RST codes to implement the

multiple interrupt scheme.

Interrupt Call-Locations: When an interrupt occurs the program is transferred to a specific memory

location. Then the monitor transfers the program from the specific memory location to a memory

location in RAM, from where the user can write the program for interrupt service sub-routine (ISS).

For TRAP, RST 7.5, 6.5 and 5.5 the program is automatically transferred to specific memory locations

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 142

without any external hardware. The necessary hardware is already provided within 8085. The specific

memory locations for these interrupts are as follows :

Interrupt Call-Location in Hex

TRAP 0024

RST 7.5 003C

RST 6.5 0034

RST 5.5 002C

An interrupt for which hardware· automatically transfers the program to a specific memory location is

known as vectored interrupt.

RST 7.5, 6.5 and 5.5: RST 7.5, RST 6.5 and RST 5.5 are maskable interrupts. These interrupts are

enabled by software using instructions EI and SIM (Set Interrupt Mask). The execution of the

instruction SIM enables/disables interrupts according to the bit pattern of the accumulator. Fig. 7.9

shows accumulator contents for SIM instruction.

Bits 0 - 2 set/rest the mask bits of interrupt mask register for RST 5.5, 6.7 and 7.5. Bit 0 is for

RST 5.5 mask, bit 1 for RST 6.5 mask and bit 2 for RST 7.5 mask. If a bit is set to 1 the corresponding

interrupt is masked off (disabled). If it is set to 0, the corresponding interrupt is enabled. Bit 3 is set to

1 to make bits 0 - 2 effective. Bit 4 is an additional control for RST 7.5. if it is set to 1, the flip-flop for

RST 7.5 is reset.

Pending Interrupts: When one interrupt request is being served, other interrupt may occur resulting

in a pending request. When more than one interrupts occur simultaneously, the interrupt having higher

priority is served and the interrupts with lower priority remain pending. As 8085 contains several

interrupt lines; an interrupt may occur while other interrupt is being served resulting in a pending

interrupt.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 143

Fig. 7.10 shows accumulator contents after the execution of instruction RIM. Bits 0-2 a for

interrupt masks; 1=masked. Bit 3 indicates interrupt enable flag; 1=enabled. Bits 4-6 indicate pending

interrupts; 1=pending. Bit 7 -serial input data,

4.6 Interfacing Devices and I/O Devices

To communicate with the outside world microcomputers use peripherals (I/O devices).

Commonly used peripherals are: A/D converter, D/A converter, CRT, printers, hard disk, floppy disks,

magnetic tapes etc. Peripherals are connected to the microcomputer through electronic circuits known

as interfacing circuits. Some of the general purpose of the devices are:

i. I/O port

ii. Programmable Peripheral Interface (PPI)

iii. DMA controller

iv. Interrupt Controller

v. Communication Interface

vi. Programmable Counter/Interval Timer.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 144

Examples of such devices are: CRT controller, Floppy Disk controller, Keyboard and Display

interface.

Generation of Control Signal for memory and I/O devices: Intel 8085 issues control signal RD’,

WR’ for read and write operation of memory and I/O devices. A status signal IO/M’ to distinguish

whether read/write operation is to be performed by memory or I/O device.

MEMR’ – Memory read

MEMW’ – Memory write

IOR’ – I/O read

IOW’ – I/O write

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 145

These control signals are generated using RD’ WR’ and IO/M’ using logic gates.

To get MEMR’ use IO/M v RD’. v is a symbol for logical OR operation. Memory read operation takes

place when IO/M’ and RD’ both are low. IO/M’ and RD’ are applied to an OR gate. The output of the

OR gate is MEMR’. When both IO/M’ and RD’ are low, MEMR’ goes low it activates memory for

read operation.

To get MEMW’, use IO/M’ v WR’

I/O read/write operation take place when IO/M’ is high. To get IOR’ and IOW’ signals IO/M’ is

inverted and then applied to OR gates.

4.7 I/O Ports

An input device is connected to the microprocessor through an input port. An input port is a

place for unloading data. An input device unloads data into the port. The microprocessor reads data

from the input port. Thus data are transferred from the input device to the accumulator via input port.

Similarly, the output device is connected to the microprocessor through an output port. The

microprocessor unloads data into an output port. As the output port is connected to the output device,

data are transferred to the output device. Fig. 7.12 shows a schematic connection of CPU, I/O port, I/O

devices.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 146

The Intel 8212 is an 8-bit nonprogrammable I/O port. It can be connected to the microprocessor

either as an input port or an output port. If we require one input port and one output port, two units of

8212 will be required. One of them will be connected in input mode and other in the output mode. Fig.

7.13 shows the connection of 8212 in input mode and output mode.

Programmable Peripheral Interface (PPI): A programmable peripheral interface is a multiport

device. The ports may be programmed in a variety of ways as required by the programmer. The device

is very useful for interfacing peripheral devices.

Example :

Intel 8255: The Intel 8255 is a programmable peripheral interface (PPI). It has two versions, namely

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 147

the Intel 8255A and the Intel 8255A-5. General descriptions for both are same. There are some

differences in their electrical characteristics. It has three 8-bit ports, namely Port A, Port B and Port C.

The Port C has been further divided into two 4-bit ports. Port C upper and Port C lower. Thus a total of

4 ports are available, two 8-bit port and two 4-bit ports. Each port can be programmed either as an

input port or an output

Architecture of Intel 8255A : Fig. 7.14 shows the pin diagram of Intel 8255A. it is a 40 pin I.C.

package.

Power dissipation 1 Watt.

VIL = Input low voltage = Minimum 0.5 V, Maximum 0.8 V.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 148

VIH = Input high voltage = Minimum 2 V, Maximum Vcc.

VOL = Output low voltage = 0.45 V.

VOH = Output high voltage = 2.4 V.

IDR = Darlington drive current=Minimum 1 mA, Maximum 4 mA on any 8 pins of the port.

The pins for various ports are as follows :

PAo-PA7 8 pins of port A

PBo- PB7 8 pins of port B

PCo-PC3 4 pins of port Clower

PC4-PC7 4 pins of port Cupper

The important control signals are as follows :

CS (Chip Select). It is a chip select signal. The LOW status of this signal enables

communication between the CPU and 8255.

RD(Read). When RD goes LOW the 8255 sends out data or status information to the CPU on

the data bus. In other words it allows the CPU to read data from the input port of 8255.

WR (Write). When WR goes LOW the CPU writes data or control word into 8255. The CPU

writes data into the output port of 8255 and the control word into the control word register.

A0 and A1. The selection of input port and control word register is done using A0 and A1 in

conjunction with RD and WR. If two 8255 units are used the address of ports are as follows :

For the 1st unit of 8255, i.e. 8255.1

Port/control word Port/control word

register register address

Port A 00

Port B 01

Port C 02

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 149

Control word register 03

For the 2nd unit of 8255, i.e. 8255.2

Port/control word Port/control word

register register address

Port A 08

Port B 09

Port C 0A

Control word register 0B

Operating Mode of 8255: The Intel 8255 has the following three modes of operation which are

selected by software:

Mode 0-Simple Input/Output ,

Mode l-Strobed Input/Output,

Mode 2-Bidirectional Port.

The 8255 has two 8-bit ports (Port A and Port B) and two 4-bit ports (Port Cupper and Port

Clower).

Mode 0 operation a Port can be operated as a simple input or output port. Each of the four ports

of 8255 can be programmed to be either an input or output port.

Mode 1 is strobed input/output mode of operation. The port A and Port B both are designed to

operate in this mode of operation. When Port A and Port B are programmed in Mode 1, six pins of Port

C are used for their control. PCo, PCl and PC2 are used for the control of the port B which can be used

either as input or output port. If the Port A is operated as an input PC3, PC4 and PCs are used for its

control. The remaining pins of Port C i.e. PC6 and PC7 can be used as either input or output. When

Port A is operated as an output port, pins PC3, and PC6 and PC7 are used for its control.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 150

Mode 2 is strobed bidirectional mode of operation. In this mode Port A can be programmed to

operate as a bidirectional port. The Mode 2 operation is only for Port A. When Port A programmed in

Mode 2, the Port B can be used in either Mode 1 or Mode 0. For Mode 2 operation PC3 to PC7 are

used for the control of Port A.

Operating Modes

I/O Mode BSR mode (Bit Set/Reset mode)

Mode 0 Mode 1 Mode 2

Simple I/O mode Handshake mode Bidirectional mode

Strobed mode

Port A, B, C Port A, B Port A

Control Groups: For the control purpose 24 lines of I/O ports are divided into two groups, namely

Group A and Group B. The Group A contains the Port A and the Port C upper The Group B contains the

Port B and the Port Clower. A control word is formed which contains the information regarding the

function and modes of the ports. The CPU outputs the control word to 8255. The control word

initializes ports. The control blocks receive control words from internal data bus of 8255 and issue the

proper commands to their associated ports.

Control Groups

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 151

Group A Group B

Port A, Port C upper (C4-C7) Port B, Port C lower ( C0-C3)

Control Word: The bits of the control word are as shown in Fig. 7.15. control word is written into the

control word register which is within 8255. No read operation of the control word register is allowed.

If a particular port is to be made an input port, the bit corresponding to that port is set to 1. For making

port an output port, the corresponding bit for the port is set to 0. The detailed description the bits of the

control word is as follows:

Bit No. 0. I It is for Port Clower.

To make Port Clower an input port, the bit is set to 1.

To make Port Clower an output port, the bit is set to 0.

Bit No.1. It is for Port B.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 152

To make Port B an input port, the bit is set to 1.

To make Port B an output port, the bit is set to 0.

Bit No.2. It is for the selection of the mode for the Port B. If the Port B has to operate in Mode

0, the bit is set to O. For Mode 1 operation of the port B, it is set to 1.

Bit No.3. It is for the Port Cupper.

To make Port Cupper an input port, the bit is set to 1.

To make port Cupper an output port, the bit is set to 0.

Bit No.4. It is for the Port A.

To make Port A an input port, the bit is set to 1.

To make Port A an output port, the bit is set to 0.

Bit No.5 These bits are to define the operating mode of the Port A. For the various

and 6. modes of Port A these bits are defined as follows :

Mode of Port A Bit No. 6 Bit No. 5

Mode 0 0 0

Mode 1 0 1

Mode 2 1 0 or 1

For Mode 2 bit No.5 is set either 0 or 1; it is immaterial.

Bit No.7. It is set to 1 if ports A, B and C are defined as input/output ports. It is set to 0 if the

individual pins of the Port C are to be set or reset.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 153

Example 1: Form control word for the following configuration of the ports of Intel 8255

for Mode 0 operation;

Port A-output

Port B -output

Port Clower-output

Port Cupper-input

The control word bit for the above configuration of the ports are as shown in Fig. 7.17. The

control word for the above definition of the ports of Intel 8255 is 88 H.

7 6 5 4 3 2 1 0 Bit No.

1 0 0 0 1 0 0 0

Control Word Bits

8 8

Example 2: Make Control word for the following arrangement of the ports of Intel 8255

for Mode 0 operation;

Port A-output

Port B -output

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 154

Port Clower-output

Port Cupper-output

The control word bit for the above configuration of the ports are as shown in Fig. 7.18. The

control word for the above definition of the ports of Intel 8255 is 80 H.

7 6 5 4 3 2 1 0 Bit No.

1 0 0 0 0 0 0 0

Control Word Bits

8 0

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 155

MICROPROCESSOR APPLICATIONS

5.1 Introduction

A microprocessor-based system being very small and compact forms a part of the equipment

which is being controlled. Nowadays microprocessor-based systems are replacing electromechanical

logic. They have numerous applications such as measurement, display and control of current, voltage,

power factor, frequency, temperature, stress, strain, pressure, force, deflection, vibration, water level

etc. communication, transportation, traffic control, lift control, military equipment, robotics…

5.2 Delay Subroutine:

A delay program is used to provide the desired delay. To generate delay a few registers of the

microprocessor are loaded with desired numbers and then decremented to zero. The delay time

depends on the numbers loaded in the registers.

Delay Subroutine using one Register:

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

FC00 06, 10 MVI B, 10H Get 10 in register B.

FC02 05 LOOP DCR B Decrement register B.

FC03 C2, 02, FC JNZ LOOP content of register B become 0? No,

jump to LOOP. Yes, proceed ahead

FC06 C9 RET

To generate very small delay only one register can be used. In above program register B has

been loaded by 10H. then register B is decremented and program moves in a loop till the content of

register B becomes zero. After this program returns to the main program.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 156

To calculate delay time is examined that how many times each instruction of the above

program is executed.

Instruction states

MVI B, 10 7

DCR B 4

JNZ 7/10

RET 10

The instruction JNZ takes 10 states when the content of register B is not zero and the program

jump to the label LOOP. JNZ takes only 7 states when the content of register B has become zero and

the program proceeds further to execute RET instruction.

The instructions MVI B, l0H and RET are executed only once. The instruction DCR B is

executed 16 times. The instruction JNZ is executed 16 times, out of which 15 times the program jumps

to the label LOOP as the content of register B has not become zero, and takes 10 states each time. At

last the content of register B becomes zero, JNZ is executed and the program proceeds further. The last

execution of instruction JNZ takes only 7 states.

Delay Subroutine using Register Pair:

Program

Labels Mnemonics Operands Comments

LXI D, FFFF Get FFFF in register pair D-E

LOOP DCX D Decrement Count.

MOV A, D Move content of register D to accumulator

ORA E Check if D and E are zero

JNZ LOOP If D- E is not zero, jump to LOOP

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 157

RET return to main program.

States required for each instruction of the above program are:

Instruction States

LXI D 10

DCX D 6

MOV A, D 4

ORA E 4

JNZ 7/10

RET 10

Delay Subroutine using Two Register :

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2400 06, 10 MVI B, 10H Get 10 in register B.

2402 0E, 78 LOOPI MVI C, 78 Get 78 in register C.

2405 0D LOOPII DCR C Decrement C.

2406 C2, 05, 24 JNZ LOOP II Is [C] zero? No, go to LOOP II yes

proceed further.

2409 05 DCR B Decrement B..

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 158
240A C2, 02, 24 JNZ LOOP I Is [B] zero? No, go to LOOP I yes

proceed further.

240D C9 RET Return to main program.

In the program registers Band C are loaded by the numbers 10H and 78H respectively. Then

these numbers are decremented to zero. To calculate the delay we have to examine that many times

each instruction of the program is executed. First of all the instruction MVI B, 10H is executed only

once and the register B is loaded by 10H. Then the next instruction MVI C, 78H is executed and the

register C is loaded by 78H. The instruction DCR C decrements register C by 1. Now the content of

register C is decreased from 78H to 77H.

The instruction JNZ examines whether the content of the register C has become zero. As the

content of the register C has become 77H; not zero, the program jumps to the label LOOP II. The

instruction DCR C again decrements register C by 1. The instruction JNZ in examines whether the

content of the register C has become zero. The program jumps to label LOOP II again. This process is

continued and the program moves in LOOP II till the content of register C becomes zero. In this way

the instruction DCR C and JNZ are executed 120 (78H) times to make the content of register C zero.

After this the program comes out of loop and moves further and executes the instruction DCR B. The

content of register B is decreased from 10H to 0F. The next instruction JNZ examines whether the

content of register B has become zero. As the content of register B is not zero. the program jumps to

the label LOOP I.

The instruction MVI C, 78H is again executed and the register C is again loaded by number

78H. The instructions DCR C and JNZ LOOP II are again executed 120 times to make the content of

register C zero. After this the program comes out of LOOP II and the instruction DCR B is executed.

Now the content of register B is decreased from F to E. The instruction JNZ LOOP I is executed and

the program jumps to the label LOOP I again. The whole process of loading of register C , making its

content zero and decrementing of register B is repeated again and again till the content of register B

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 159

becomes zero. Thus we see that the program jumps (16-1) times to the label LOOP I as the content of

register B is 10H.

the instruction MVI C, 78 H is executed 16 times. The instruction DCR C and JNZ LOOP II

executed 120x16= 1920 times because for each decrement of register B, DCR C and JNZ LOOP II are

executed 120 times. The instruction JNZ LOOP I is executed 16 times out of which program jumps to

LOOP I (16-1)= 15 times as the content of register B has not become zero and JNZ LOOP I takes 10

states each time. At last when the content of register B becomes zero, JNZ is executed and the program

proceeds further. This time the execution of JNZ takes only 7 states. Similarly, JNZ LOOP II is

executed 120x16 times out of which (120-1)x16 program jumps to LOOP II, and JNZ LOOP II takes

10 states each time when the content register C is not zero. JNZ LOOP II is executed 16 times and

proceeds further taking only 7 states each time when the content of register C is zero.

The delay time is calculated as follows:

Instruction states

MVI 7

DCR 4

JNZ 7/10

RET 10

Delay Subroutine using 3 Register :

Program

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2400 3E, 98 MVI A, 98H Get 10 Control word.

2402 D3, 03 OUT 03 Initialize port for LED display.

2404 06, 50 MVI B, 50 H

2406 0E, FF LOOP1 MVI C, FF

2408 16, FF LOOP2 MVI D, FF

240A 15 LOOP3 DCR D

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 160
240B C2, 0A, 24 JNZ LOOP 3 Delay subroutine with 3 registers.

240E 0D DCR C

240F C2, 08, 24 JNZ LOOP 2

2412 05 DCR B

2413 C2, 06, 24 JNZ LOOP 1

2416 3E, 01 MVI A, 01

2418 D3, 01 OUT 01 output for LED

241A 76 HLT stop

The numbers 50 in register B, FF in C and FF in D are moved to get the desired delay. The

delay time with these numbers is about 25 sec. this time has been noted by stop watch in laboratory.

The maximum delay with three register can be obtained when all registers are loaded with FF. the

maximum delay is about 74 sec.

5.3 7-Segment LED Display:

The seven-segment LED display is a multiple display. It can display all decimal digits and

some letters. It is very popular among multiple displays as it has the smallest number of separately

controlled light emitting diodes (LED). Multiple displays of 9-segment LED, 14-segment LED and

dot matrix type are available.

In seven-segment displays there are seven light emitting diodes (LED) as shown in Fig. 9.2

Each LED can be controlled separately. To display a digit or letter the desired segments made ON as

shown in Fig. 9.3 (a) to Fig. 9.3 (i).

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 161

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 162

There are two types of 7-segment displays namely, common-Cathode type and common-anode

type. In a common-cathode type display all the 7 cathodes of LEDs are tied together to the ground as

shown in Fig. 9.4 (a). When a +5 Vd.c is applied to any segment, the corresponding diode emits light.

Thus applying logic '1' i.e. positive logic to the desired segments, the desired letter or decimal number

can be displayed.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 163

In common-anode type display all the 7 anodes are tied together and connected to + 5 V supply

as shown Fig. 9.4 (b). A particular segment will emit light when 0 logic is applied to it.

The seven-segment displays are not connected to I/O ports directly. They are connected

through buffers or drivers/decoders. 7446A, 74L46, 7447, 74L47 and 74LS47 are decoders/drivers for

common-anode type seven segment displays. 7448, 74LS48, 7449 and 74LS49 are decoders/drivers

for common-cathode type seven segment displays. Fig. 9.5 shows the pin configuration of 74LS48.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 164

FND 500 and FND 503:

FND 500 and FND 503 are common cathode 7-segment displays. Fig 9.6 shows the pin

configuration of FND 503.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 165

FND 507/510. FND 507/510 are common-anode 7-segment displays.

MAN 74 A:

MAN 74A is a common-cathode 7-segment display. The pin configuration of MAN 74A is

shown in fig. 9.73

MAN 72. MAN72 is a common-anode 7-segment display

Fig. 9.8 shows the interfacing of decoders/drivers 74LS48 and 7-segment display MAN 74A with

microprocessor.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 166

Table 9.1 is a functional table for 74LS48. the program to display the decimal number is as follows:

Example: Write a program to display 5.

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2400 3E, 98 MVI A, 98H Get Control word.

2402 D3, 03 OUT 03 Initialize I/O ports.

2404 3E, 05 MVI A, 05 get 05 in accumulator

2406 D3, 01 OUT 01 send 05 at port B

2408 76 HLT stop.

The control word 98 H makes the port B an output port, The Microprocessor outputs 05 at the

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 167

Port B. The pins PBo - PB3 of the port B are connected to decoder/driver 74LS48. Thus the binary bits

corresponding to the decimal number 5 are applied to 74LS48 and it is displayed by the 7-segment

display. 0 is the MSB of the decimal number 05. The logic for 0 is outputed on the pins PB4 - PB7.

These pins are not connected anywhere and consequently 0 is not displayed. If we use 2

decoder/drivers and 7-segment displays. shown in Fig. 9.9, No.1 display will display 5 and No.2

display will show 0. Thus two units of display will display 2 desired decimal numbers. Suppose we

want to display 89. For this purpose, in the above program the data of the memory location 2405 is

changed to 89. Now the microprocessor will output 89 at Port B and 1st unit will display 9 and the 2nd

unit 8.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 168

5.4 Frequency Measurement:

To measure the frequency of a signal, the time period for half cycle is measured which is

inversely proportional to the frequency. A sinusoidal signal is converted to square wave using a

voltage comparator LM 311 or operational amplifier LM 747 or LM 324 as shown in Fig. 9.31. A

diode is used to rectify the output signal. A potential is used to reduce the magnitude to 5 volts.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 169

A program has been developed to sense the zero instant of the rectified square wave.

microprocessor measures the magnitude of the square wave at two consecutive points as shown in Fig.

9.32. The two magnitudes are compared and decision is taken on the basis of carry and zero status

flags, whether the point is at zero instant.

Various points have been shown in Fig. 9.32. Very near to P3 at its left side the magnitude of

square wave is zero, and at P4, 5V, at logic ’1’. The microprocessor subtracts the 1st value from the

2nd, so the result is non-zero and there is no carry. This is the basis for the selection of zero instant

point. Suppose the microprocessor takes reading at P1 and P2 where both magnitudes are zero.

Difference of the two is zero. So this is not the zero instant of the wave. At points P5, and P6, the

difference of the two values is zero, so it is also not a zero instant point. P7 and p8, the difference is

non-zero but there is carry. So it is the end point of the half-square wave.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 170

The microprocessor reads the magnitude of the square wave again and again, and moves in the

loop. It crosses the loop when the magnitude of the square wave becomes zero. Thus the time for half

cycle is measured. The count can be compared with the stored numbers in a look-up table and the

frequency can be displayed. The count which is inversely proportional to the frequency of the input

signal can be used for further processing and control as desired. An interfacing circuitry is shown in

Fig. 9.33.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 171

Program:

Memory Machine Labels Mnemonics Operands Comments

Address Codes

2000 3E, 98 MVI A, 98H Get Control word.

2002 D3, 03 OUT 03 Initialize ports.

2004 DB,00 BACK IN 00 Read voltage pulse at port A.

2006 47 MOV B, A

2007 DB, 00 IN 00 Read voltage pulse again at port A.

2009 B8 CMP B compare two readings

200A CA, 04, 20 JZ BACK

200D DA, 04, 20 JC BACK

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 172

2010 01, 00, 00 LXI B, 00, 00 Initialize B-C pair for counting

2013 03 LOOP INX B

2014 DB, 00 IN 00 read voltage pulse

2016 1F RAR

2017 DA, 13, 20 JC LOOP Check whether V has become zero.

No, go to LOOP

201A 76 HLT Stop

In the above program the part of the program from the memory address 2004 to 200F is detect the

zero instant of the square wave. IN 00 at the memory location 2004 is the 1st reading of the magnitude

of the square wave. MOV B, A transfers the 1st reading from the accumulator to the register B. Again

IN 00 at the memory address 2007 takes the 2nd reading of the magnitude. CMP B compares these two

readings. JZ indicates the condition that both readings are of equal magnitudes, i.e. readings are either

0, 0 or 1, 1. Therefore, it is not a condition of zero instant and the program jumps to the label BACK.

JC indicates that the 1st reading is 1 and the 2nd reading is 0. This is the condition for the end of

rectified square wave.

So, program again jumps to the label BACK. The program will move further only when the result

is non-zero and there is no carry. This will be the case when the 1st reading is 0 and the 2 nd reading is

1. This is the case of zero instant. Once the zero instant is detected the program move in a loop till the

square wave exists. Thus the time period for half cycle is measured. The count is inversely

proportional to the frequency. The count can be used for further processing control. If frequency is to

be displayed 7-segment displays can be interfaced and using look-up table technique it can be

displayed. The program given above is only for the frequency measurement.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 173

5.5 Temperature Measurement:

For the measurement of temperature one of the following devices are used:

(i) Resistance thermometers (-100 to + 3000 C)

(ii) Thermocouples (-250 to +20000 C)

(iii) Thermistors (-100 to + 1000 C)

(iv) Pyrometers (+100 to +50000 C)

Platinum wires are frequently used in resistance thermometers for industrial applications because

of greater resolution, and mechanical and electrical stability as compared to copper or nickel wire. A

change in temperature causes a change in resistance. The resistance thermometer is placed in an arm of

a Wheatstone bridge to get a voltage proportional to temperature.

A thermistor is a semiconductor device fabricated from a sintered mixture of metal alloys, having

a large negative temperature coefficient. A thermistor is used in a Wheatstone bridge to get a voltage

proportional to temperature. It can be used in range of -100 to + 100 0 C for greater accuracy as

compared to platinum resistance thermometer.

The different range of temperature are as follows: .

Material Temp. range 0 C

Iron-constantan - 200 to + 1300

Chromel-alumel - 200 to + 1200

Copper-constantan - 200 to +400

Chromel-constantan 0 to 1200

Pt-Rh-Platinum 0 to 1500

Tungsten-rhenium 0 to 2000

Microprocessor-Based Scheme.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 174

Fig. 9.40 (a) shows a microprocessor-based scheme for temperature measurement and control.

The output of a thermocouple proportional to the temperature of the furnace or oven etc. is in millivolt.

It is to be amplified using multistage amplifier The amplified voltage is applied to an A/D converter.

The microprocessor sends a start of conversion signal to the A/D converter.

The microprocessor displays the measured temperature. If the temperature of a furnace, oven

or water-bath is to be controlled, the microprocessor first measures its temperature, and then compares

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 175

the measured temperature with a reference temperature at which the temperature is to be maintained. If

the measured temperature is higher than the reference temperature, microprocessor sends control

signal to reduce temperature. if the measured temperature is less than the reference temperature, the

microprocessor sends a control signal to increase temperature The temperature of a furnace or oven

can be increased or decreased by increasing or decreasing the fuel input to the furnace. If heating is

done by electric heaters, current in heating element is controlled. Fig. 9.40 (b) shows an amplifier

circuit to amplify the output of the thermocouple. D.C. level detector is for initial adjustment.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 176

Program:

Memory Machine Labels Mnemonics Operands Comments

Address Codes

FC00 3E, 98 MVI A, 98H Control word for 8255.

FC02 D3, 0B OUT 0B

FC04 3E,00 LOOP MVI A, 00 send start of conversion pulse.

FC06 D3, 0A OUT 0A make PC3 first 0 then 1.

FC08 3E, 08 MVI A, 08

FC0A 3E, 08 OUT 0A

FC0C DB 0A READ IN 0A Check end of conversion

FC0E 17 RAL pulse

FC0F DA, 0C, FC JC READ

FC12 DB, 08 IN 08 Read output of A/D converter

FC14 32, F6, FF STA FFF6 store result

FC17 06, 00 MVI B, 00 Display result

FC19 CD, FA, 06 CALL 06FA

FC1C C3, 04, FC JMP LOOP

Result:

Temperature Transducer voltage Amplified voltage Digital Voltage

In 0C millivolts volts

45 0.3 0.66 2D
Department of Computer Science, Thanthai Hans Roever College, Perambalur
 Microprocessor and It’s Applications 177

50 0.5 0.95 38

55 0.8 1.29 44

60 0.9 1.56 51

65 1.2 2.03 62

70 1.4 2.19 70

75 1.5 2.49 7F

80 1.7 2.69 8B

85 2.0 3.05 9E

90 2.2 3.33 AA

95 2.5 3.72 C1

100 2.7 3.99 CA

5.6 Water Level Indicator:

A microprocessor-based water level indicator can be developed as shown in fig. 9.49. the

water tank is at ground potential. Probes are connected to 5 V d.c through resisters. When a probe is

immersed in water it is at ground potential and its logic is 0. when it is not immersed in water, it is at

5V potential and logic is 1. these probes are connected to an inverter which inverts the logic of probes.

After inversion the probe which is not immersed in water gives 0 logic and the probe immersed in

water output logic 1. the output of inverter are connected to port A of 8255. in the interface only six

probes have been used. The 6 output points of the inverter are connected to 5 pins of Port A. the

remaining 2 pins of Port A are grounded. The 2 nd unit of 8255, i.e. 8255.2 has been used for this

purpose.

The microprocessor reads the binary logic corresponding to water level from the port, and

displays it on 7-segment display which are connected to Port B. the values of water levels at which

probes are placed in the tank are stored in memory in the form of look-up table.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 178

The microprocessor counts how many probes are immersed in water and determines the LSB of

the memory address of look-up table. Suppose 1st, 2nd and 3rd probes are immersed in water. These

probes are at logic 1. the microprocessor counts that 3 probes are immersed in water and it picks up the

water level corresponding to memory location FD03 which is 30 cm.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 179

Automatic Pumping:

Automatic pumping can be done on the basis of water level in the tank. The program given

below has been developed to switch on a pump when water level is 20cm or less than 20 cm. the pump

is switched off when water level reaches 60 cms.

Memory Machine Labels Mnemonics Operands Comments

Address Codes

FBFD 31, 00, FE LXI SP, FE00 Initialize stack pointer.

FC00 3E, 98 MVI A, 98H Initialize I/O port of 8255.

FC02 D3, 0B OUT 0B

FC04 26, FD MVI H, FD MSB of memory address for look-up table.

FC06 06, 00 LOOP MVI B, 00 No. of probes immersed in water,

initial value = 00.

FC08 0E, 08 MVI C, 08 No. of counts.

FC0A DB, 08 IN 08 Read water level.

FC0C 17 READ RAL

FC0D D2, 11, FC JNC LOOK

FC10 04 INR B

FC11 0D LOOK DCR C

FC12 C2, 0C, FC JNZ READ

FC15 68 MOV L, B LSB of memory address for look-up table.

FC16 7E MOV A, M

FC17 D3, 09 OUT 09 Display water level.

FC19 CD, 40, FC CALL DELAY

FC1C FE, 20 CPI 20 is level > 20 cm?

FC1E D2, 27, FC JNC GO Yes, jump to GO

FC21 F5 PUSH PSW Save water level reading which is in ACC.

FC22 3E, 01 MVI A, 01 No; switch on pump

FC24 D3, 0A OUT 0A

FC26 F1 POP PSW get water level reading in acc.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 180
FC27 FE, 60 GO CPI 60 is water level < 60 cm?

FC29 DA, 06, FC JC LOOP yes; jump to LOOP.

FC2C 3E, 00 MVI A, 00 No; switch off pump.

FC2E D3, 0A OUT 0A

FC30 C3, 06, FC JMP LOOP

DELAY SUBROUTINE

Memory Machine Labels Mnemonics Operands Comments

Address Codes

FC40 06, 10 MVI B, 10H

FC42 0E, FF LOOP1 MVI C, FF

FC44 16, FF LOOP2 MVI D, FF

FC46 15 LOOP3 DCR D

FC47 C2, 46, FC JNZ LOOP3

FC4A 0D DCR C

FC4B C2, 44, FC JNZ LOOP2

FC4E 05 DCR B

FC4F C2, 42, FC JNZ LOOP1

FC52 C9 RET

Data

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 181

Water level in cm.

FD00 - 00

FD01 - 10

FD02 - 20

FD03 - 30

FD04 - 40

FD05 - 50

FD06 - 60

5.7 Microprocessor-Based Traffic Control:

Fig. 9.54 shows a simple arrangement and port connections for microprocessor-based traffic

control. All ports of 8255 have been programmed as output ports. The control word to make all ports

output ports for Mode 0 operation is 80H.

The connection of pins of the ports to LED have been made through buffers (7407). Positive

logic has been used to switch on LEDs. Three types of LEDs have been used red, yellow and green.

Green light glows to allow crossing, yellow to make alert, and red does not allow crossing.

Green light for right turns have not been shown. One can add some more LEDs for this

purpose, connect them to ports and make additions to the program.

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 182

Memory Machine Labels Mnemonics Operands Comments

Address Codes

FC00 3E, 80 MVI A, 80H Get control word for 8255.

FC02 D3, 0B OUT 0B Initialize ports of 8255.2.

FC04 3E, 01 LOOP MVI A, 01

FC06 D3, 09 OUT 09 Red ON for South

FC08 D3, 08 OUT 08 Red ON for North

FC0A 3E, 44 MVI A, 44 Green ON for east and west

FC0C D3, 0A OUT 0A

FC0E CD, 00, FD CALL DELAY I

FC11 3E, 22 MVI A, 22 Yellow ON for east and west

FC13 D3, 0A OUT 0A

FC15 3E, 02 MVI A,02

FC17 D3, 09 OUT 09

FC19 D3, 08 OUT 08

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 183
FC1B CD, 13, FD CALL DELAY II

FC1E 3E, 11 MVI A, 11

FC20 D3, 0A OUT 0A Red ON east and west

FC22 3E, 04 MVI A, 04

FC24 D3, 08 OUT 08 Green for North

FC26 D3, 09 OUT 09 Green for south

FC28 CD,00,FD CALL DELAY I

FC2B 3E, 22 MVI A, 22 Yellow ON for east and west

FC2D D3, 0A OUT 0A

FC2F 3E, 02 MVI A, 02

FC31 D3, 09 OUT 09 Yellow ON for South

FC33 D3, 08 OUT 08 Yellow ON for North

FC35 CD, 13, FD CALL DELAY II

FC38 C3, 04, FC JMP LOOP

DELAY 1

FD00 06, 20 MVI B, 20

FD02 0E,FF G03 MVI C, FF

FD04 16, FF G02 MVI D, FF

FD06 15 G01 DCR D

FD07 C2, 06, FD JNZ G01

FD0A 0D DCR C

FD0B C2, 04, FD JNZ G02

FD0E 05 DCR B

FD0F C2, 02, FD JNZ G03

FD12 C9 RET

DELAY I1

Department of Computer Science, Thanthai Hans Roever College, Perambalur

 Microprocessor and It’s Applications 184
FD13 06, 10 MVI B, 10

FD15 C3, 02, FD JMP FD02 G03

ALL THE BEST

Department of Computer Science, Thanthai Hans Roever College, Perambalur