Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

Experiment-1

OBJECT: Study and bread board realization of Logic Gates, K map, Flip- Flops (S-R, J-K,
T-Type and D-Type) equations, and realization of characteristics and excitation table of
various Flip- Flops.

APPARATUS REQUIRED:

[Link] COMPONENT SPECIFICATION QUANTITY

1 AND Gate IC 7408 1
2 OR Gate IC 7432 1
3 NOT Gate IC 7404 1
4 NAND- 2 INPUT Gate IC 7400 1
5 NOR Gate IC 7402 1
6 X-OR Gate IC 7486 1
7 NAND-3 INPUT Gate IC 7410 1
8 DIGITAL TRAINER KIT SCIENTECH 1
9 CONNECTING WIRES - As Req.
10 CONNECTING LEADS - As Req.

CIRCUIT DIAGRAMS :

SR-Type Flip Flop

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Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

T-Type Flip Flop

D TYPE FLIP FLOP

J K TYPE FLIP FLOP

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Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

THEORY

Circuit that takes the logical decision and the process are called logic gates. Each gate has
one or more input and only one output. OR, AND and NOT arebasic gates. NAND, NOR
and X-OR are known as Universal gates. Basic gatesform these gates.

AND GATE

The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is lowlevel when any one of the
inputs is low.

OR GATE

The OR gate performs a logical addition commonly known as OR function. The output is high
when any one of the inputs is high. The output is low level when both the inputs are low.

NOT GATE

The NOT gate is called an inverter. The output is high when the input is low. The output is
low when the input is high.

NAND GATE

The NAND gate is a contraction of AND-NOT. The output is high when

both inputs are low and any one of the input is low .The output is low level when both inputs
are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both
inputs are low. The output is low when one or both inputs are high.
XOR GATE:

The output is high when any one of the inputs is high. The output is low when both the inputs
are low and both the inputs are high.

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 Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

PIN DIAGRAM OF GATE

AND GATE

OR GATE

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Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

NOT GATE

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Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

XOR GATE

2- INPUT NAND GATE

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Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

3- INPUT NAND GATE

NOR GATE

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Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

FLIP FLOP

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to
store state information. A flip-flop is a bistable multivibrator. The circuit can be made to
change state by signals applied to one or more control inputs and will have one or two
outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a
fundamental building block of digital electronics systems used in computers,
communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such data storage can be used for
storage of state, and such a circuit is described as sequential logic. When used in a finite-state
machine, the output and next state depend not only on its current input, but also on its current
state (and hence, previous inputs). It can also be used for counting of pulses, and for
synchronizing variably-timed input signals to some reference timing signal.

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-

triggered). Although the term flip-flop has historically referred generically to both simple and
clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for
discussing clocked circuits; the simple ones are commonly called latches.

Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge- sensitive. That
is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a
single type (positive going or negative going) of clock edge.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

PROCEDURE

 First of all we need to affix the respective ICs in the bread board.
 Secondly we have to provide the input connections and also the
interconnections with the help of connecting leads and wires.

 Thirdly we have to provide the Vcc (+ 5V) and Ground at the respectivepins.

 Fourthly after thoroughly checking all the connections, we have to openthe power
button of the Digital Trainer Kit.

 Lastly, read the corresponding values and write it in your report.

OBSERVATION

S-R Flip Flop

TRUTH TABLE

S R Q(t)
0 0 No Change
0 1 0
1 0 1
1 1 Race

J-K Flip Flop

TRUTH TABLE

J K Q(t)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q(t)

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

T Flip Flop
TRUTH TABLE

T Q(t)
0 Q(t)
1 Q(t)
D Flip Flop
TRUTH TABLE

D Q(t)
0 0
1 1

RESULT
The study of various flip flops including SR, JK, T AND D and various logicgates has been
done.

CONCLUSION
The vivid description of various logic gates and their respective ICs including2 input and
three input and pin diagrams of various ICs and symbols and various flip flops including
SR, JK, T and D has been done.

PRECAUTIONS
 All the connections should be tight and proper.

 Handle the ICs carefully.

 Check the connections once again before switching on the digital trainerkit.

 Switch off the trainer kit after performing the Experiment.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

Experiment-2

OBJECT : Implementation of Half Adder, Full Adder and Subtractor.

APPARATUS REQUIRED

[Link] Apparatus Specification Quantity

1. AND IC7408 2
2. EX-OR IC 7486 2
3. OR IC 7432 1
4. NOT IC 7404 1
5. Digital Trainer’s Kit Scientech As Req.
6. Connecting Wires As Req.
7. Connecting Leads

CIRCUIT DIAGRAMS

HALF ADDER

FULL ADDER

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

HALF SUBTRACTOR

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Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

FULL SUBTRACTOR

THEORY

The most basic arithmetic operation is the addition of two binary digits. This simple addition
consists of four possible operations:

0+0 = 0 (sum) 0 (carry)

0+1 = 1 (sum) 0 (carry)

1+0 = 1 (sum) 0 (carry)

1+1 = 0 (sum) 1 (carry)

When both augends and addend are equal to 1, the binary sum consists of two digits. The
higher significant bit of this result is called a carry. A combinational circuit that performs the
addition of two bits is called a half adder. One performs the addition of three bits is a full
adder.

HALF ADDER

The circuit needs two binary inputs and two binary outputs. The truth table is listed below.
The carry output, C is 1 when both inputs are 1. The S output represents the least significant
bit of the Sum. The simplified Boolean functions for the two outputs can be obtained from the
truth table.

S = A’B + AB’C

= AB

Department of Computer Science Engineering, Integral University, Lucknow

 Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

FULL ADDER

A full adder is a combinational circuit that performs the arithmetic sum of three bits. It
consists of three inputs and two outputs. The outputs are necessary because the sum of three
binary digits range from 0-3 and binary 2 or 3 needs two digits. The truth table is shown here.
The Boolean expression for S and C are

S = A’B’Ci’ + A’BCi’ + ABCi

C = A’BCi + AB’Ci + ABCi’ + ABCi’

HALF SUBTRACTOR

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two
input and two outputs. The outputs are difference and borrow. The difference can be applied
using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter.

FULL SUBTRACTOR

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the
logic circuit should have three inputs and two outputs. The two half subtractor put together
gives a full subtractor .The first half subtractor will be C and A B. The output will be
difference output of full subtractor. The expression AB assembles the borrow output of the
half subtractor and the second term is the inverted difference output of first X-OR.

PROCEDURE

 Verify the gates.

 Make the connections as per the circuit diagram.

 Switch on VCC and apply various combinations of input according to truth table.

 Note down the output readings combinations of inputs.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

OBSERVATION
TRUTH TABLES

Half Adder

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Full Adder

A B Ci S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

HALF SUBTRACTOR

A B DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

FULL SUBTRACTOR
A B C DIFFERENE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

RESULT
The study of half adder, full adder and Subtractor has been done.

CONCLUSION

The thorough study of half adder, full adder, Subtractor with their truth tables
and their respective ICs has been done.

PRECAUTIONS

 All the connections should be tight and proper.

 Handle the ICs carefully.

 Check the connections once again before switching on the digital trainer
kit.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

Experiment-3

OBJECT : Implementation of Multiplexer and De multiplexer circuits usingIC

74153 and 74155.

APPARATUS REQUIRED
[Link] COMPONENT SPECIFICATION QUANTITY
1 MULTIPLEXER IC IC 74153 1
2 DE MULTIPLEXER IC IC 74155 1
3 DIGITAL TRAINER KIT SCIENTECH 1
4 CONNECTING WIRES As Req.
5 CONNECTING LEADS As Req.

CIRCUIT DIAGRAM-

MULTIPLEXER

DEMULTIPLEXER

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

THEORY
MULTIPLEXER
Multiplexer means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection
of a particular input line is controlled by a set of selection lines. Normally there are 2n input
line and n selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER

The function of De-multiplexer is in contrast to multiplexer function. It takes

information from one line and distributes it to a given number of output lines.
For this reason, the de-multiplexer is also known as a data distributor. Decoder
can also be used as de-multiplexer. In the 1: 4 de-multiplexer circuit, the data
input line goes to all of the AND gates. The data select lines enable only one
gate at a time and the data on the data input line will pass through the selected
gate to the associated data outputline.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

PROCEDURE

 First of all we need to affix the respective ICs (I.C 74153, 74155) in thebread
board.

 Secondly we have to provide the input connections and also the interconnections
with the help of connecting leads and wires according tothe pin diagram.

 Thirdly we have to provide the Vcc (+ 5V) at pin no 16 and Ground atpin no 8
respectively.

 Fourthly after thoroughly checking all the connections, we have to openthe power
button of the Digital Trainer Kit.

 Lastly, read the corresponding values and verify it and write it in yourreport.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

OBSERVATION TRUTH TABLE

MULTIPLEXER

G0 S0 S1 Y0
0 0 0 A0
0 0 1 A1
0 1 0 A2
0 1 1 A3
1 X X 0

DE MULTIPLEXER

D0 G0 S0 S1 Y0 Y1 Y2 Y3
X 1 X X 1 1 1 1
0 X X X 1 1 1 1
1 0 0 0 0 1 1 1
1 0 1 0 1 0 1 1
1 0 0 1 1 1 0 1
1 0 1 1 1 1 1 0

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

RESULT
The study of multiplexer and de multiplexer has been done.

CONCLUSION
The detailed study of Multiplexer using IC 74153 and De multiplexer using IC74155 along
with their pin diagrams has been done.

PRECAUTIONS

 All the connections should be tight and proper.

 Handle the ICs carefully.

 Check the connections once again before switching on the digital trainerkit.

 Switch off the trainer kit after performing the Experiment.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

Experiment-4

OBJECT : Implementation of Ripple counters and Registers.

APPARATUS REQUIRED

Serial number Apparatus Specification Quantity

1. ICs (Dual JK master slave Flip 7476 2
flop)
2. Quad 2-input NAND gates 7400 1
Quad 2-input AND gates
3. Digital Trainer’s Kit 7408 1

4. Connecting Wires
5. Connecting leads

CIRCUIT DIAGRAM :

COUNTER

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Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

SHIFT REGISTER

THEORY

A ripple counter is an asynchronous counter where only the first flip-flop is

clocked by an external clock. All subsequent flip-flops are clocked by the
output of the preceding flip-flop. Asynchronous counters are also called ripple-
counters because of the way the clock pulse ripples it way through the flip-
flops.

The MOD of the ripple counter or asynchronous counter is 2 n if n flip-flops are

used. For a 4-bit counter, the range of the count is 0000 to 1111 (24-1). A
counter may count up or count down or count up and down depending on the
input control. The count sequence usually repeats itself. When counting up, the
count sequence goes from 0000, 0001, 0010, .. 1110 , 1111 , 0000, 0001, ... etc.
When counting down the count sequence goes in the opposite manner: 1111,
1110, ... 0010, 0001, 0000, 1111, 1110, ... etc.

The complement of the count sequence counts in reverse direction. If the

complemented output counts up, the complemented output counts down. If the
complemented output counts down, the complemented output counts up.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

There are many ways to implement the ripple counter depending on the
characteristics of the flip flops used and the requirements of the count sequence.

 Clock Trigger: Positive edged or Negative edged

 JK or D flip-flops
 Count Direction: Up, Down, or Up/Down

Asynchronous counters are slower than synchronous counters because of the

delay in the transmission of the pulses from flip-flop to flip-flop. With a
synchronous circuit, all the bits in the count change synchronously with the
assertion of the clock. Examples of synchronous counters are the Ring and
Johnson counter.

It can be implemented using D-type flip-flops or JK-type flip-flops.

SHIFT REGISTERS
In digital circuits, a shift register is a cascade of flip flops, sharing the same
clock, in which the output of each flip-flop is connected to the "data" input of
the next flip-flop in the chain, resulting in a circuit that shifts by one position
the "bit array" stored in it, shifting in the data present at its input and shifting
out the last bit in the array, at each transition of the clock input.

More generally, a shift register may be multidimensional, such that its "data in"
and stage outputs are themselves bit arrays: this is implemented simply by
running several shift registers of the same bit-length in parallel.

Shift registers can have both parallel and serial inputs and outputs. These are
often configured as 'serial-in, parallel-out' (SIPO) or as 'parallel-in, serial-out'
(PISO). There are also types that have both serial and parallel input and types
with serial and parallel output. There are also 'bidirectional' shift registers which

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Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

Allow shifting in both directions: L→R or R→L. The serial input and last output
of a shift register can also be connected to create a 'circular shift register'.

This configuration allows conversion from serial to parallel format. Data is

input serially, as described in the SISO section above. Once the data has been
clocked in, it may be either read off at each output simultaneously, or it can be
shifted out and replaced.

In cases where the parallel outputs should not change during the serial loading
process, it is desirable to use a latched or buffered output. In a latched shift
register (such as the 74595) the serial data is first loaded into an internal buffer
register, then upon receipt of a load signal the state of the buffer register is
copied into a set of output registers. In general, the practical application of the
serial-in/parallel-out shift register is to convert data from serial format on a
single wire to parallel format on multiple wires.

PROCEDURE
 First of all we need to affix the respective ICs (I.C 7476, IC 7404, IC
7408) in the bread board.

 Secondly we have to provide the input connections and also the

interconnections with the help of connecting leads and wires.

 Thirdly we have to provide the Vcc (+ 5V) and Ground at the respective
pins.

 Fourthly after thoroughly checking all the connections, we have to open

the power button of the Digital Trainer Kit.

 Lastly, read the corresponding values and write it in your report.



Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

OBSERVATION

TRUTH TABLE

Outputs are shown below are available after switching on the kit.

Q3 Q2 Q1 Q0 Display
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9

PIN CONNECTIONS OF IC 7476

J1, J2, K1, K2 – Data Inputs

CP1, CP2 – Clock pulse inputs (Active falling edge)

CD1, CD2 – Direct Clear inputs (Active Low)

SD1, SD2 – Direct Set inputs (Active Low)

Q1, Q1, Q2, Q2 – Outputs

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

SHIFT REGISTER

Line Inputs Outputs

Number Clear Data CLK FFA FFB FFC FFD
Pulses
1 0 0 0 0 0 0 0
2 1 1 0 0 0 0 0
3 1 1 1 1 0 0 0
4 1 1 2 1 1 0 0
5 1 1 3 1 1 1 0
6 1 0 4 1 1 1 1
7 1 0 5 0 1 1 1
8 1 0 6 0 0 1 1
9 1 0 7 0 0 0 1
10 1 1 8 0 0 0 0
11 1 0 9 0 0 0 0
12 1 0 10 1 0 0 0
RESULT
The study of Ripple counter and register has been done.

CONCLUSION
The vivid description of ripple counters and shift registers along with their
respective circuit diagrams and the verification of their truth table have been
successfully done.

PRECAUTIONS
 All the connections should be tight and proper.

 Handle the ICs carefully.

 Check the connections once again before switching on the digital trainer
kit.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

Experiment-5

OBJECT: Study of 8085 and 8086 kit.

APPARATUSREQUIRED

[Link] COMPONENT QUANTITY

1. 8085KIT(SCIENCETECH) 1
2. 8086KIT(SCIENCETECH) 1

CIRCUIT DIAGRAM

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

THEORY

GENERAL DESCRIPTION

8085 Micro Processor is a single board Microprocessor training/ Development Kit

configured around the most widely used Microprocessor of today’s world. Based on 8085
Microprocessor, it can be used to train engineers to control any industrial process and to
develop software for 8080 and 8085 based systems. The 8085 communicates with the outside
world through a key board having 28 keys and seven segment hexadecimal displayed. The kit
also has the capability of interacting with CRT Terminal and IBM PC compatible computer
system through the serial interface provided on the board. The 8085 model has an extra on
board facility of audio cassette interface. 8085 provides 8K/32K bytes of RAM and 8K bytes
of EPROM. The total on board memory can be very easily expanded to 64K bytes in an
appropriate combination of RAM and ROM. The monitor is incorporated from 0000 - 1FFF
and the necessary 8K bytes of RAM has an address of2000 -3FFF. The Input/ Output
structure of 8085provides 24 programmable I/O lines using 8255. It has got 16 bit
programmable Timer/Counter for generating any type of counting etc. The on board
resident’s system monitor software is very powerful and provides various software utilities.
The kit provides various powerful software commands like, INSERT, DELETE ,BLOCK
MOVE, RELOCATE,STRING FILL&MEMORY COMPARE etc. which are very helpful in
debugging/developing the software. 8085 is configured around the internationally adopted
STD Bus, which is the most popular bus for process control and real time applications. All
the address, data and control lines are available at the edge connector. The kit is fully
expandable for any kind of application. SYSTEM SPECIFICATION CPU - 8 bit
Microprocessor, the 8085 MEMORY .

Department of Computer Science Engineering, Integral University, Lucknow

 Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

ThePS-8086 board which demonstrates the capabilities of the 40-pin 8086 (various families)
Sample programs are provided to demonstrate the unique features of the supported devices.
The PS-8086Kitcomeswiththefollowing:
ThePS–86A board is based on Intel 8086 Microprocessor, which operates at6.144MHz
using the crystal of [Link] board can operate using the 101/104PC keyboard supplied
along with the trainer kit and 2 Line by 16- character LCD display or from the PC (using the
Terminal Emulation Software).
Microprocessor’s Address, Data and Control bus pins are brought to the 50 pin FRC
[Link] -86A is equipped with powerful software monitor in two- 27C256 EPROM.

The monitor supports Video terminal RS232C interface, local 101 key board and LCD
display. The board has 64KB CMOS static RAM (type 62256). PS - 86A works on +9V DC.

8086 Specifications

 8086 Microprocessor operating at18.432MHz

 16KB powerful software monitor two 27C256EPROM
 Three16-bit programmable timers from 8253
 48 programmable I/O lines from two numbers of 8255
 Serial interface using 8251
 50 pin FRC connector for system bus expansion
 20 pin FRC connector for user interface from 8255
 9 pin D type connectors for RS232 interface
 Six different select able baud rates from150 to 9600

 101 PC type key board for entering user address/data and for commands
 Built in line-by-line assemble and disassemble

 User friendly software monitor for loading and executing programs with break point
facility.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

PROCEDURE

First of all we have to switch on the trainer kit. Secondly we

have to proceed by following the steps: RESET

EXAMINE

2000 NEXT

After the completion of the program

RESET

GO 2000

FILL

RESET

EXAMINE

2000 NEXT

OBSERVATION

The study of 8085 and 8086 kit has been thoroughly one with it spin diagram and the
concepts related to its programming have been studied.

RESULT

The study of 808 5and 8086 kit has been done.

CONCLUSION

The study of 8085 and 8086 kit has been thoroughly done with it spin diagram and the
concepts related to its programming have been studied.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

PRECAUTION

 All the inputs should be given properly.

 Handle the ICs carefully.

 Check the program once again before switching on the 8085trainer kit.

 Do not press the buttons too hard.

 Switch off the 8085 trainer kit after performing the Experiment.

Department of Computer Science Engineering, Integral University, Lucknow

 Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

Experiment-6
OBJECT: Write a program to add two 16 bit hexadecimal numbers without carry.

INSTRUMENT REQUIRED: 8086 Microprocessor Trainer Kit.

PROGRAM:

MEMORYLOCATION MACHINECODE OPCODE OPERAND

0206 BE0002 MOV SI,0200H
0209 8B04 MOV AX,[SI]
020B 46 INC SI
020C 46 INC SI
020D 8B1C MOV BX,[SI]
020F 03C3 ADD AX,BX
0211 BF0402 MOV DI,0204H
0214 8905 MOV [DI],AX
0216 F4 HLT

DESCRIPTION:

To solve the given objective we have taken two hexadecimal numbers in the memory locations of 0200H and 0202H and
added them and stored the result in the memory location of 0204H.
To solve the given objective we have taken the following steps:
1. Move the source index register (SI) pointer to the location of the first number.
2. Store the first number in the AX register using SI.
3. Double increment the SI pointer to point to the memory location of the second number.
4. Store the second number in the BX register using SI.
5. Now apply ADD operation to add the numbers in the registers AX and BX and store the result in AX.
6. Move the destination index (DI) pointer to point to the memory location where the
result is to be stored.
7. Finally move the result from the AX register to the destination using DI 8. HLT to Halt or End the program.

Department of Computer Science Engineering, Integral University, Lucknow

 Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

OUTPUT:

MEMORYLOCATION VALUE
0200H 10
0201H 3A
0202H 1C
0203H 2B
0204H 2C
0205H 65

RESULT: The addition of the two hexadecimal numbers 3A1CH and 2B1CH yielded 652CH
COMMENTS:
1. MOV SI, 0200H: 16 bit data can be moved using immediate addressing . 0200 is moved to source index.
2. ADD AX, BX: contents in the accumulator and the base register are added.
3. INC SI: The content of a specified 8-bit or 16-bit register or memory location(s) is incremented by one by this
instruction.
4. HLT: This instruction stops program execution. The processor stops fetching and executing instructions.
FLOWCHART:

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

EXPERIMENT NO.7

OBJECT: Write a program to add two16 bit hexadecimal numbers with carry.

INSTRUMENT REQUIRED: 8086 Microprocessor Trainer Kit.

PROGRAM:
MEMORYLOCATION MACHINECODE OPCODE OPERAND
0208 B100 MOV CL,00H
020A BE00 02 MOV SI,0200H
020D 8B04 MOV AX,[SI]
020F 46 INC SI
0210 46 INC SI
0211 8B1C MOV BX,[SI]
0213 03 C3 ADD AX,BX
0215 73 02 JNC L1
0217 FEC1 INC CL
0219 BF04 02 L1:MOV DI,0204H
021C 89 05 MOV [DI],AX
021E 47 INC DI
021F 47 INC DI
0220 89 0D MOV [DI],CL
0222 F4 HLT

DESCRIPTION:

To solve the given objective we have taken two hexadecimal numbers in the memory locations of
0200H and 0203H and added them and stored the result in the memory location of 0204H, we have
also stored the carry in the memory location 0206H

To solve the given objective we have taken the following steps:

1. Initialize the counter register CL to 0.
2. Move the source index register (SI) pointer to the location of the first number.
3. Store the first number in the AX register using SI.
4. Double increment the SI pointer to point to the memory location of the second number.
5. Store the second number in the BX register using SI.
6. Now apply ADD operation to add the numbers in the registers AX and BX and store the result in
AX.
7. Jump instruction is used that increments the carry counter if there is no carry else increments the
carry counter.
8. Move the destination index (DI) pointer to point to the memory location where the result is to be
stored.
9. Move the result from the AX register to the destination using DI
10. Finally increment the DI to point to the location to store the carry bit and move the carry bit to the
destination before halting.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

OUTPUT:

MEMORYLOCATION VALUE
0200H FF
0201H FF
0202H FF
0203H FF
0204H FE
0205H FF
0206H 01
0207H 00

RESULT: The addition of the two hexadecimal numbers FFFFH and FFFFH yields FFFEH as the sum and
0001 as the carry.
COMMENTS:

1. MOV SI,0200H: 16 bit data can be moved using immediate addressing . 0200 is moved to source index.
2. ADDAX,BX: Contents in the accumulator and the base register are added.
3. INCSI: The content of a specified 8-bitor16-bit register or memory location(s)is incremented by one by this
instruction.
4. HLT: This in struction stops program execution. The processor stops fetching and executing instructions.
FLOWCHART:

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

EXPERIMENT NO.8

OBJECT: Write a program to find the greatest number from an array of 10 numbers.

INSTRUMENT REQUIRED: 8086 Microprocessor Trainer Kit.

PROGRAM:
MEMORYLOCATION MACHINECODE OPCODE OPERAND
020B B109 MOV CL,09H
020D BE00 02 MOV SI,0200H
0210 8A04 MOV AL,[SI]
0212 46 L1 : INC SI
0213 3A04 CMP AL,[SI]
0215 73 02 JNBL2
0217 8A04 MOV AL,[SI]
0219 FEC9 L2 : DEC CL
021B 75 F5 JNZL1
021D BF0A02 MOV DI,020AH
0220 88 05 MOV [DI],AL
0222 F4 HLT

DESCRIPTION:

To solve the given objective we have taken ten hexadecimal number sin the memory locations from
0200H and 0209H. In order to find the greatest number amongst them we need to compare each
number with the other. The greatest number will be stored in the memory location 020AH.

To solve the given objective we have taken the following steps:

1. Initially we initialize the counter register CL to 9 because the number of comparisons with anyone
number would be 9. In other words it will compare 9 times.

2. Move the source index register(SI)pointer to the location of the first number.

3. Store the first number in the Al register using SI.

4. Initiate a loop and compare each element with the element stored in AL while simultaneously
decrementing counter CL.

5. If then number is greater than that stored in AL then we store that number in AL else we do not change the
value in AL.

6. The above mentioned process goes on until CL becomes zero, at this point we have the greatest
number in the AL register.
7. Move the destination index (DI) pointer to point to the memory location where the result is to be
stored.
8. Finally move the result from the AL register to the destination using DI and Halt.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

OUTPUT:

MEMORYLOCATION VALUE
0200H A1
0201H B1
0202H C1
0203H D1
0204H E1
0205H E2
0206H E3
0207H E4
0208H E5
0209H E6
020AH E6(greatest number)

RESULT: The greatest of the10hexadecimal numbers is E6H,which gets stored in the memory location 020AH.
COMMENTS:

1. INCSI: The content of a specified 8-bitor16-bit register or memory location(s)is incremented by one by this
instruction.
2. CMPAL,[SI]:The compare in struction compares two specified operands. For comparison one operand is
subtracted from the other.
3. JNC: It causes the program execution to jump to the label given in the instruction.
4. HLT: This in struction stops program execution. The processor stops fetching and executing instructions.

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

EXPERIMENT NO.9

OBJECT: Write a program to calculate the factorial of a number.

INSTRUMENT REQUIRED: 8086 Microprocessor Trainer Kit.

PROGRAM:
MEMORYLOCATION MACHINECODE OPCODE OPERAND
0204 BE00 02 MOV SI,0200H

0207 8B04 MOV AX,[SI]

0209 8BD8 MOV BX,AX

020B 4B DEC BX

020C F7 E3 L1 : MUL BX

020E 4B DEC BX

020F 75 FB JNZL1

0211 BF02 02 MOV DI,0202H

0214 89 05 MOV [DI],AX

0216 F4 HLT

DESCRIPTION:

To solve the given objective we have taken a hexadecimal number in the memory
location of 0200H and multiplied it successively to obtain the factorial.
To solve the given objective we have taken the following steps:

1. Move the source index register (SI)pointer to the location of the number.
2. Store the number in the AX register using SI.
3. Move the same number in the BX register to counter.
4. Decrement BX to get the next number to be multiplied.
5. Multiply the number in BX and AX recursively and decrement BX simultaneously
get the factorial eventually.
6. Move the destination index (DI) pointer to point to the memory location where the
result is to be stored.
7. Finally move the result from the AX register to the destination using DI and Halt.

OUTPUT:

MEMORYLOCATION VALUE
0200H 05
0201H 00
0202H 78
0203H 00

Department of Computer Science Engineering, Integral University, Lucknow

Computer Organization & Microprocessor Lab (CS-236) Even Semester 2025-26

RESULT:
The factorial of the hexadecimal number 0005H comes out To beas 0078H,which gets
stored in the memory location 0202H.
COMMENTS:

1. MOV SI, 0200H: 16 bit data can be moved using immediate addressing. 0200 is
moved to source index.
2. MUL BX: This instruction is used for the multiplication of 2 unsigned numbers. It
multiplies the content of BX with AX and stores in AX.
3. DECBX: This instruction decrements specified16-bit register by one.
4. JNZ: It causes the program execution to jump to the label given in the instruction.

Department of Computer Science Engineering, Integral University, Lucknow