Memory and I/O Interface, Serial Transmission,
8251 USART, 8257 DMA Controller
– Introduction
Microprocessor is the central processing unit of a computer system, but by itself it does not
have enough storage capacity and cannot directly interact with external devices. Therefore,
memory units and input/output devices must be connected with the microprocessor using
proper interfacing techniques.
Memory interfacing allows the processor to store programs and data externally, while I/O
interfacing allows communication with peripherals such as keyboard, display, printer, disk
drives, sensors, etc.
Proper interfacing ensures correct timing, address selection, and data transfer between CPU
and connected devices.
– Memory Interfacing
Memory interfacing is the method of connecting RAM and ROM chips with the
microprocessor so that the processor can read instructions and store or retrieve data.
The microprocessor uses:
• Address bus to specify memory location
• Data bus to transfer data
• Control bus to define operation (read/write)
Each memory chip has a specific range of addresses called memory map. Through address
decoding logic, the correct memory chip is selected for each operation.
Thus, memory interfacing ensures:
• Proper location selection
• Reliable data transfer
• Organized memory usage
– Need for Memory Interfacing
Microprocessors like 8086 have very limited internal storage. For practical applications,
large external memory is required.
Memory interfacing is required to:
• Store large programs
• Save temporary data during processing
• Hold system software like OS and drivers
Without interfacing:
• CPU cannot access required instructions
• System cannot function efficiently
Thus, memory interfacing expands storage capability and overall system functionality.
– Memory Interface Components
Address Bus
The address bus carries binary addresses from CPU to memory. Each unique address
identifies a specific memory location.
Data Bus
The data bus transfers actual data between microprocessor and memory. It is bidirectional
for reading and writing.
Control Signals
• RD (Read) signal enables memory to send data to CPU
• WR (Write) signal enables memory to store incoming data
• Chip Select (CS) activates the particular memory chip
Together, these signals coordinate accurate memory access.
– Memory Read Operation
● CPU places address on address bus
● Address decoding logic activates correct memory chip
● RD signal becomes active
● Selected memory outputs data
● CPU reads the data
This operation is used for fetching instructions and reading stored values.
– Memory Write Operation
● CPU places address on address bus
● CPU places data on data bus
● WR signal is activated
● Memory stores data at specified address
This allows updating variables and saving results.
– I/O Interfacing Concept
I/O interfacing connects external devices to the microprocessor so that data can flow in both
directions.
Since peripherals operate at different speeds and voltage levels, direct connection is not
possible. Interface circuits perform:
• Speed matching
• Signal conversion
• Data buffering
• Control synchronization
Thus I/O interface acts as a communication controller between CPU and devices.
– Purpose of I/O Interface
● Speed Matching
● CPU operates in nanoseconds while devices operate slower. Interface buffers data.
● Data Formatting
● Converts serial to parallel or vice versa.
● Control Management
● Generates handshake signals for safe data transfer.
● Protection
● Prevents electrical damage to CPU.
– Types of I/O Interfacing
MAPPED I/O
In memory mapped I/O, peripheral devices are assigned memory addresses just like RAM
and ROM. The microprocessor does not differentiate between memory and I/O devices.
Working Principle:
• I/O devices occupy some portion of memory address space
• Same address bus is used for memory and I/O
• CPU uses memory instructions such as MOV, LDA, STA
For example, if address F000H is assigned to a display device, writing data to this address
will send data to display.
Advantages:
• Allows use of all memory-related instructions
• Supports arithmetic and logical operations directly on I/O data
• Easier programming
• Flexible addressing
Disadvantages:
• Reduces total memory space available
• Address decoding becomes complex
• Large systems face memory wastage
Applications:
• Embedded systems
• Microcontrollers
• Systems requiring high-speed I/O access
ISOLATED I/O
In isolated I/O devices have separate address spaces.
Working Principle:
• Separate I/O address bus used
• Special instructions IN and OUT transfer data
• Control signals differentiate I/O operations
Example:
OUT 80H sends data to port 80H
Advantages:
• Does not reduce memory space
• Simple address decoding
• Clear separation of memory and I/O
Disadvantages:
• Limited instruction set
• Cannot use arithmetic directly on I/O ports
• Slightly slower than memory mapped I/O
Applications:
• Microprocessors like 8086
• Industrial control systems
– Serial Data Transmission
Serial data transmission is a method of communication in which data bits are transmitted
sequentially over a single communication channel.
Instead of sending multiple bits simultaneously, serial transmission sends one bit after
another in time sequence.
This method is preferred for:
• Long distance communication
• Low-cost systems
• High noise environments
– Characteristics of Serial Communication
Parallel transmission requires many wires which increases:
• Cost
• Signal distortion
• Synchronization problems
Serial transmission reduces:
• Wiring complexity
• Interference
• Maintenance difficulty
– Asynchronous Transmission
Asynchronous transmission sends each character independently without a shared clock.
Frame Format:
Start Bit → Data Bits → Parity Bit → Stop Bit(s)
Start bit alerts receiver.
Stop bit indicates the end of character.
Characteristics:
• Simple hardware
• Slower speed
• Higher overhead
• Widely used in serial ports
Advantages:
• Cheap implementation
• No clock synchronization needed
Disadvantages:
• Less efficient
• Lower speed
– Synchronous Transmission
In synchronous transmission, data is sent in blocks or frames with a shared clock signal.
Features:
• Continuous data stream
• No start/stop bits
• High efficiency
• Requires synchronization
Advantages:
• High speed
• Less overhead
• Ideal for large data transfer
Disadvantages:
• Complex hardware
• Synchronization required
– 8251 USART Introduction
The 8251 USART (Universal Synchronous/Asynchronous Receiver Transmitter) is a
programmable communication interface that manages serial data communication between a
microprocessor and external serial devices.
Its internal operation is based on coordinated functioning of several hardware blocks that
perform:
• Data buffering
• Serial-to-parallel conversion
• Parallel-to-serial conversion
• Timing control
• Error detection
• Status reporting
MAIN BLOCKS OF 8251 USART ARCHITECTURE
1. Data Bus Buffer (DBB)
Full Form: Data Bus Buffer
This block connects the USART to the microprocessor data bus.
Functions:
• Transfers data between CPU and USART
• Sends control words to USART
• Receives status words from USART
• Handles parallel communication
It acts as the communication gateway between CPU and serial interface.
2. Read/Write Control Logic (R/W Control Logic)
This block controls how USART interacts with the microprocessor.
Functions:
• Decodes CPU control signals
• Selects internal registers
• Controls read and write operations
• Synchronizes communication
It decides whether CPU is sending data, commands, or reading status.
3. Transmitter Section (TX Section)
TX = Transmit
Responsible for sending serial data.
Main parts:
• Transmit Buffer Register (TBR)
• Transmit Shift Register (TSR)
• Control circuitry
Functions:
• Accepts parallel data from CPU
• Converts it into serial bits
• Adds start bit, parity bit, stop bits
• Sends data through TxD (Transmit Data) pin
4. Receiver Section (RX Section)
RX = Receive
Responsible for receiving serial data.
Main parts:
• Receive Shift Register (RSR)
• Receive Buffer Register (RBR)
• Error detection logic
Functions:
• Receives serial data from RxD (Receive Data) pin
• Converts serial bits to parallel form
• Detects errors
• Sends correct data to CPU
5. Mode Register (MR)
MR = Mode Register
Programs the communication format.
Controls:
• Synchronous or Asynchronous mode
• Number of data bits
• Parity enabled or not
• Stop bits
Without this register, USART cannot operate.
6. Command Register (CR)
CR = Command Register
Controls the operation of transmitter and receiver.
Functions:
• Enable/disable transmitter
• Enable/disable receiver
• Reset errors
• Send break characters
• Control interrupts
Acts as operational control switch.
7. Status Register (SR)
SR = Status Register
Provides information about USART condition.
Indicates:
• TxRDY – Transmitter Ready
• RxRDY – Receiver Ready
• PE – Parity Error
• FE – Framing Error
• OE – Overrun Error
• TxEMPTY – Transmission complete
Helps CPU manage communication flow.
8. Clock & Timing Control
Controls bit timing and synchronization.
Inputs:
• TxC – Transmitter Clock
• RxC – Receiver Clock
Functions:
• Synchronizes data shifting
• Maintains correct bit duration
Advantages of 8251:
Versatility: The 8251 USART can be used for both synchronous and asynchronous
communication, making it a versatile peripheral.
Error detection: The USART includes built-in error detection features, such as parity
checking, which help to ensure the accuracy of transmitted data.
Flow control: The USART includes flow control features, which allow for the regulation of
data transmission and reception, preventing data loss and overloading.
Compatibility: The 8251 USART is compatible with a wide range of microprocessors,
making it a popular choice for serial communication in many different systems.
Ease of use: The USART includes simple interface pins and registers, making it relatively
easy to use and program.
Disadvantages of 8251:
Limited speed: The 8251 USART has a relatively low maximum data transfer rate of 115.2
kbps, which may be insufficient for some applications.
Limited buffer size: The USART has a small internal buffer size, which may result in data
loss if data is not read from the buffer in a timely manner.
Complex programming: Although the interface pins and registers of the USART are
relatively simple, programming the USART can be complex, requiring careful attention to
timing and other parameters.
Cost: While the 8251 USART is relatively affordable, it does add cost to a system,
particularly if multiple USARTs are required.
Limited functionality: While the 8251 USART is a useful peripheral for serial
communication, it does not include more advanced features, such as DMA (direct memory
access) or advanced error correction.
Serial vs Parallel Communication in Microprocessors
The following table highlights all the significant differences between serial
communication and parallel communication in microprocessors −
Parameter Serial Communication Parallel Communication
Definition Serial communication is a Parallel communication is
communication method in a communication method
which data is transferred in which multiple bits are
bit by bit. transferred at the same
time.
Number of communication Serial communication Multiple communication
lines needs a single lines are required for
communication line for simultaneous data
data transfer. transfer.
Nature of data transfer In serial communication, In parallel communication,
data transfer takes place multiple data bits transfer
sequentially i.e., one bit at the same time.
after the other.
Speed Serial communication is Parallel communication is
relatively slower. faster.
Suitable distance Serial communication is Parallel communication is
suitable for long distances. suitable for short
distances.
Complexity Serial communication is Parallel communication is
relatively simple, as it uses relatively complex, as it
only one single channel. uses multiple data lines.
Cost Serial communication is Parallel communication is
cost-effective. relatively expensive.
Reliability Due to minimal Parallel communication is
interference, serial less reliable, as it is more
communication is more prone to interference.
reliable.
Data transmission mode Serial communication Parallel communication
supports full-duplex mode supports half-duplex mode
and provides bi-directional and provides
communication. unidirectional
communication.
Error detection Serial communication Parallel communication
provides better error provides limited error
detection by using parity detection capabilities.
bits.
Applications In microprocessor Parallel communication is
systems, serial best for internal
communication is better communication within
for connecting external microprocessors
devices.
– DMA Concept
Direct Memory Access (DMA) is a data transfer technique that allows peripheral devices to
transfer large blocks of data directly to or from main memory without continuous
involvement of the microprocessor.
In a conventional system, the CPU controls every data transfer between I/O devices and
memory. This becomes inefficient when high-speed devices such as disk drives, network
interfaces, or data acquisition systems are used.
DMA removes this bottleneck by permitting peripherals to communicate with memory
directly.
– 8257 DMA Controller
[Link]
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– Advantages of 8257
● Increased Data Transfer Speed: Accelerates memory operations, making it
significantly faster than CPU-managed transfers.
● Reduced CPU Overhead: Frees up the CPU to perform other tasks while data
transfers occur in the background.
● Four Independent Channels: Features 4 channels that can be configured
independently, supporting up to 4 I/O devices.
● Large Data Handling: Each channel allows for up to
● of data transfer.
● Versatile Operation: Supports read, write, and verify transfer operations.
● Flexible Priority Logic: Employs priority logic to manage multiple peripheral requests
effectively.
● Operating Modes: Operates in both master and slave modes, providing flexibility in
system design.
● Specialized Features: Generates a MARK signal after every byte transferred to alert
peripheral devices.
– Disadvantages of 8257
● Increased System Cost & Complexity: As an additional, specialized hardware unit, it
increases the overall cost and complexity of the system design.
● Cache Coherence Issues: When the DMA modifies memory directly, the CPU’s cache
may contain stale data, leading to coherence problems.
● Bus Contention: While designed to free the CPU, the DMA controller still competes
with the CPU for system bus access, which can slow down the CPU if not managed
properly.
● Design Overhead: Implementing the 8257 requires careful management of control
signals (HRQ, HLDA) and, in some systems, external logic for address latching (e.g.,
using ALE).
● Fixed Limitations: The 8257 has limited channels (4) and can only handle transfers of
up to 64KB per channel.