DIGITAL ELECTRONICS 2A

Module Code: EEDE216

Session Number: WK3
Topic: SIGNAL CONVERSION AND PROCESSING
Outcomes
❑ Explain the basic process of converting ❑ Show how the op-amp can be used as
an analog signal to digital an inverting amplifier or a comparator
❑ Discuss the purpose of filtering. ❑ Explain how a flash ADC works
❑ Describe the sampling process. ❑ Discuss dual-slope ADCs
❑ Describe the purpose of the sample-
and-hold function ❑ Describe the operation of a
successive-approximation ADC
❑ Define the Nyquist frequency
❑ Describe a delta-sigma ADC
❑ Define the reason for aliasing and
discuss how it is eliminated ❑ Discuss testing ADCs for a missing
❑ Explain what an operational amplifier code, incorrect code and offset
is ❑ Describe the purpose of an ADC
Introduction: Sampling and Filtering
• An anti-aliasing filter and a sample-
and-hold circuit are two functions
typically found in a digital signal
processing system.
• The sample-and-hold function does
two operations, the first of which is
sampling.
• Sampling is the process of taking a
sufficient number of discrete values
at points on a waveform that will
define the shape of the waveform.
Introduction: Sampling and Filtering
• The requirements must be fulfilled to accurately sample an analogue
signal and precisely replicate the original signal.
• All analogue transmissions have a spectrum of component frequencies
except for a pure sine wave.
• These frequencies show up as harmonic multiples for a pure sine wave.
• An analogue signal's harmonics are sine waves with varying amplitudes
and frequencies.
• A low-pass filter, also known as an anti-aliasing filter, must be applied to
a signal before it can be sampled to remove any harmonic frequencies
that exceed a specific threshold set by the Nyquist frequency.
Sampling Theorem
• The sampling theorem states that,
in order to represent an analog
signal, the sampling frequency,
𝑓𝑠𝑎𝑚𝑝𝑙𝑒 , must be at least twice the
highest frequency component
𝑓𝑎 max (Nyquist frequency) of the
analog signal.

𝒇𝒔𝒂𝒎𝒑𝒍𝒆 > 𝟐𝒇𝒂 max

The Need for Filtering
• To eliminate any frequency components
(harmonics) in the analogue signal that
surpass the Nyquist frequency, low-pass
filtering is required.
• The undesirable phenomenon known as
aliasing will happen if the analogue signal
contains any frequency components that are
higher than the Nyquist frequency.
• If an alias signal's frequency is lower than the
highest frequency of the analogue signal
being sampled, distortion results from it
falling inside the input analogue signal's
spectrum or frequency band.
Application

• An example of the application of sampling is in digital audio equipment.

• The sampling rates used are 32 kHz, 44.1 kHz, or 48 kHz (the number of
samples per second).
• The 48 kHz rate is the most common, but the 44.1 kHz rate is used for audio
CDs and prerecorded tapes.
• According to the Nyquist rate, the sampling frequency must be at least twice
the audio signal.
• The CD sampling rate of 44.1 kHz captures frequencies up to about 22 kHz,
which exceeds the 20 kHz specification that is common for most audio
equipment.
Holding the Sampled Value

• The holding operation is the second part of the sample-and-hold function.

• After filtering and sampling, the sampled level must be held constant until the
next sample occurs.
• This is necessary for the ADC to have time to process the sampled value.
• This sample-and-hold operation results in a “stairstep” waveform that
approximates the analog input waveform
 Analog-to-Digital Conversion
• The process of converting the sample-and-hold circuit's output to a string of binary
codes that indicate the amplitude of the analogue input at each sample time is
known as analog-to-digital conversion.
• The analog-to-digital conversion can be performed using a constant value rather
than having the analogue signal change during a conversion interval, which is the
time between sample pulses, because the sample-and-hold method maintains the
amplitude of the analogue input signal constant between sample pulses.
Quantization
• The process of converting an analog
value to a code using and ADC circuit
is called quantization.
• Let's quantize an analogue waveform
replica into four levels (0–3) to
demonstrate.
• Four stages require two bits. For the
duration of the sample, the sampled
data remain intact.
• Data is quantized to the next lower
level
Quantization

• Two-bit quantization for the

waveform results
Quantization

• More quantization bits will

improve the accuracy.
• On the right, the same waveform
from earlier is quantized in 4 bits
(16 quantization levels)
Quantization

• Results of from the 16

quantization levels
Quantization
• Below shows the reconstruction of the waveform to compare the accuracy
between the 4 and 16 quantization levels
Methods of Analog-to-Digital Conversion
• There are two important ADC parameters;
resolution, which is the number of bits, and
throughput, which is the sampling rate an ADC can
handle in units of samples per second (sps).
• An operational amplifier is common to most types
of ADCs and digital-to-analog converters (DACs).
• An op-amp is a linear amplifier that has two inputs
(inverting and noninverting) and one output.
• It has a very high voltage gain and a very high
input impedance, as well as a very low output
impedance.
Methods of Analog-to-Digital Conversion
• When used as an inverting amplifier, the
op-amp is configured as shown

• When the op-amp is used as a comparator, two voltages

are applied to the inputs.
• When these input voltages differ by a very small
amount, the op-amp is driven into one of its two
saturated output states, either HIGH or LOW, depending
on which input voltage is greater.
Methods of Analog-to-Digital Conversion

• Now, let's define the operation of a

comparator.
• As implied by the name, it is a device or
circuit that compares two inputs' voltage
levels and outputs a high voltage or a low
voltage based on which is higher.
Flash (Simultaneous) Analog-to-Digital Converter
• The flash method utilizes special
high-speed comparators that
compare reference voltages with
the analog input voltage.
• When the input voltage exceeds
the reference voltage for a given
comparator, a HIGH is generated
• In general, (2𝑛 − 1) comparators
are required for conversion to an
n-bit binary code.
• A 3-bit converter that uses seven
comparator circuits
• The number of bits used in an ADC is
its resolution.
Flash (Simultaneous) Analog-to-Digital Converter
• The large number of comparators
necessary for a reasonable-sized
binary number is one of the
disadvantages of the flash ADC.
• Its main advantage is that it
provides a fast conversion time
because of a high throughput,
measured in samples per second
(sps).
• The reference voltage for each
comparator is set by the resistive
voltage-divider circuit.
• The output of each comparator is
connected to an input of the
priority encoder.
Flash (Simultaneous) Analog-to-Digital Converter
• The encoder is enabled by a pulse
on the EN input, and a 3-bit code
representing the value of the input
appears on the encoder’s outputs.
• The binary code is determined by
the highest-order input having a
HIGH level.
• The frequency of the enable pulses
and the number of bits in the
binary code determine the
accuracy with which the sequence
of binary codes represents the
input of the ADC.
• The signal is sampled each time
the enable pulse is active.
Example
• Determine the binary code output of the 3-bit flash ADC for the input signal
and the encoder enable pulses shown. For this example, VREF = +8 V.
Result
Dual-Slope Analog-to-Digital Converter
• A dual-slope ADC is common in digital
voltmeters and other types of
measurement instruments.
• A ramp generator (integrator) is used to
produce the dual-slope characteristic.
Below are some the results of an
integrator from different inputs
Dual-Slope Analog-to-Digital Converter
• Start by assuming that
the counter is reset
and the output of the
integrator is zero.
• Now assume that a
positive input voltage
is applied to the input
through the switch
(SW) as selected by the
control logic.

• With the inverting input of 𝐴1 is at virtual ground, and assuming that 𝑉𝑖𝑛 is constant for a period
of time, there will be constant current through the input resistor 𝑅 and therefore through the
capacitor 𝐶.
• Capacitor 𝐶 will charge linearly because the current is constant, and as a result, there will be a
negative-going linear voltage ramp on the output of 𝐴1 .
Dual-Slope Analog-to-Digital Converter

• When the counter reaches a specified count (𝑛), it will be reset (R), and the control logic will
switch the negative reference voltage (−𝑉𝑅𝐸𝐹 ) to the input of 𝐴1 .
• At this point the capacitor is charged to a negative voltage (−𝑉) proportional to the input
analog voltage.
 Dual-Slope Analog-to-Digital Converter
• Now the capacitor
discharges linearly because
of the constant current
from −𝑉𝑅𝐸𝐹 .
• This linear discharge
produces a positive-going
ramp on the 𝐴1 output,
starting at −𝑉 and having a
constant slope that is
independent of the charge
voltage.
• As the capacitor discharges, the counter advances from its RESET state.
• The time it takes the capacitor to discharge to zero depends on the initial voltage −𝑉
(proportional to 𝑉𝑖𝑛 ) because the discharge rate (slope) is constant.
Dual-Slope Analog-to-Digital Converter

• When the integrator (𝐴1 ) output voltage reaches zero, the comparator (𝐴2 ) switches to the
LOW state and disables the clock to the counter.
• The binary count is latched, thus completing one conversion cycle.
• The binary count is proportional to Vin because the time it takes the capacitor to discharge
depends only on −𝑉, and the counter records this interval of time.
Successive-Approximation Analog-to-Digital Converter

• One of the most widely used methods of

analog-to-digital conversion is
successive-approximation.
• It has a much faster conversion time than
the dual-slope conversion, but it is
slower than the flash method. It also has
a fixed conversion time that is the same
for any value of the analog input.
• An example is a 4-bit successive
approximation ADC
Successive-Approximation Analog-to-Digital Converter
• The basic operation is as follows: The input bits of
the DAC are enabled (made equal to a 1) one at a
time, starting with the most significant bit (MSB).
• As each bit is enabled, the comparator produces
an output that indicates whether the input signal
voltage is greater or less than the output of the
DAC.
• If the DAC output is greater than the input signal,
the comparator’s output is LOW, causing the bit in
the register to reset.
• If the output is less than the input signal, the 1 bit
is retained in the register.
Successive-Approximation Analog-to-Digital Converter
• The system does this with the MSB first,
then the next most significant bit, then
the next, and so on.
• After all the bits of the DAC have been
tried, the conversion cycle is complete.
• Let’s observe the step-by-step
conversion of a constant input voltage
(5.1 V in this case).
• Assuming that the DAC has the
following output characteristics: 𝑉𝑜𝑢𝑡 =
8 𝑉 for the 23 bit (MSB), 𝑉𝑜𝑢𝑡 = 4 𝑉 for
the 22 bit, 𝑉𝑜𝑢𝑡 = 2 𝑉 for the 21 bit, and
𝑉𝑜𝑢𝑡 = 1 𝑉 for the 20 bit (LSB).
Successive-Approximation Analog-to-Digital Converter
• (a) shows the first step in the conversion
cycle with the MSB = 1.
• The output of the DAC is 8 V.
• Since this is greater than the input of 5.1
V, the output of the comparator is LOW,
causing the MSB in the SAR to be reset
to a 0.
• (b) shows the second step in the
conversion cycle with the 22 bit equal to
a 1.
• The output of the DAC is 4 V.
Successive-Approximation Analog-to-Digital Converter
• Since this is less than the input of 5.1 V,
the output of the comparator switches
to a HIGH, causing this bit to be retained
in the SAR.
• (c) shows the third step in the
conversion cycle with the 21 bit equal to
a 1.
• The output of the DAC is 6 V because
there is a 1 on the 22 bit input and on
the 21 bit input; 4V + 2V = 6V.
• Since this is greater than the input of 5.1
V, the output of the comparator
switches to a LOW, causing this bit to be
reset to a 0.
Successive-Approximation Analog-to-Digital Converter
• (d) shows the fourth and final step in the
conversion cycle with the 20 bit equal to a 1.
• The output of the DAC is 5 V because there
is a 1 on the 22 bit input and on the 20 bit
input; 4V + 1V = 5V.
• The four bits have all been tried, thus
completing the conversion cycle.
• At this point the binary code in the register
is 0101, which is approximately the binary
value of the input of 5.1 V.
• Additional bits will produce an even more
accurate result. Another conversion cycle
now begins, and the basic process is
repeated. The SAR is cleared at the
beginning of each cycle.
Sigma-Delta Analog-to-Digital Converter
• Sigma-delta is a commonly used method for analog-to-digital conversion.
• It finds particular application in telecommunications, especially with audio signals.
• The method is based on delta modulation.
• Delta modulation involves quantizing the difference between two successive samples.
• Delta modulation is a 1-bit quantization method.
• The output of a delta modulator is a single-bit data stream.
• The relative number of 1s and 0s in the stream indicates the level or amplitude of the input
signal.
• The number of 1s over a given number of clock cycles determines the signal amplitude during
that interval.
• Maximum 1s correspond to the maximum positive input voltage.
• Half the maximum 1s indicate an input voltage of zero.
• No 1s (all 0s) correspond to the maximum negative input voltage.
Sigma-Delta Analog-to-Digital Converter

• In a scenario with 4096 1s during the

interval of a positive maximum input,
2048 1s occur when the input is zero.
• No 1s occur during the interval of a
negative maximum input.
• The number of 1s is proportional to
the signal level for values in between.
Sigma-Delta Analog-to-Digital Converter

• The analog input signal and the analog signal from the converted quantized bit stream
from the DAC in the feedback loop are applied to the summation (Σ) point.
• The difference (Δ) signal out of the Σ is integrated, and the 1-bit ADC increases or
decreases the number of 1s depending on the difference signal.
• This action attempts to keep the quantized signal that is fed back equal to the incoming
analog signal.
• The 1-bit quantizer is essentially a comparator followed by a latch.
Testing Analog-to-Digital Converters

• A DAC is used as part of the test setup to convert the ADC output back to analog form for
comparison with the test input.
• A test input in the form of a linear ramp is applied to the input of the ADC.
• The resulting binary output sequence is then applied to the DAC test unit and converted
to a stairstep ramp.
• The input and output ramps are compared for any deviation.
Analog-to-Digital Conversion Errors

• A 4-bit conversion is used to illustrate the principles. Assuming that the test input is an
ideal linear ramp.
Missing Code
• The stairstep output in (a) indicates that the binary code 1001 does not appear on the
output of the ADC.
• Notice that the 1000 value stays for two intervals and then the output jumps to the 1010
value.
Analog-to-Digital Conversion Errors

• In a flash ADC, for example, a failure of one of the op-amp comparators can cause a
missing-code error.
Incorrect Code
• The stairstep output in (b) indicates that several of the binary code words coming out of
the ADC are incorrect.
• Analysis indicates that the 21 -bit line is stuck in the LOW (0) state in this particular case.
Analog-to-Digital Conversion Errors

Offset
• Offset conditions are shown in (c).
• In this situation the ADC interprets the analog input voltage as greater than its
actual value.
END