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Adders Programs

The document describes three types of adders implemented in Verilog: Carry Select Adder, Carry Look Ahead Adder, and Carry Save Adder. Each adder module includes input and output specifications, along with the logic for calculating sums and carries. The Carry Select Adder uses multiplexers to handle different carry scenarios, while the Carry Look Ahead Adder optimizes carry generation, and the Carry Save Adder efficiently combines multiple inputs.
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0% found this document useful (0 votes)
4 views3 pages

Adders Programs

The document describes three types of adders implemented in Verilog: Carry Select Adder, Carry Look Ahead Adder, and Carry Save Adder. Each adder module includes input and output specifications, along with the logic for calculating sums and carries. The Carry Select Adder uses multiplexers to handle different carry scenarios, while the Carry Look Ahead Adder optimizes carry generation, and the Carry Save Adder efficiently combines multiple inputs.
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© All Rights Reserved
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CARRY SELECT ADDER

carry_select_adder.v
module carry_select_adder
( input [3:0] A,B,
input cin,
output [3:0] S,
output cout
);

wire [3:0] temp0,temp1,carry0,carry1;

//for carry 0
fulladder fa00(A[0],B[0],1'b0,temp0[0],carry0[0]);
fulladder fa01(A[1],B[1],carry0[0],temp0[1],carry0[1]);
fulladder fa02(A[2],B[2],carry0[1],temp0[2],carry0[2]);
fulladder fa03(A[3],B[3],carry0[2],temp0[3],carry0[3]);

//for carry 1
fulladder fa10(A[0],B[0],1'b1,temp1[0],carry1[0]);
fulladder fa11(A[1],B[1],carry1[0],temp1[1],carry1[1]);
fulladder fa12(A[2],B[2],carry1[1],temp1[2],carry1[2]);
fulladder fa13(A[3],B[3],carry1[2],temp1[3],carry1[3]);

//mux for carry


multiplexer2 mux_carry(carry0[3],carry1[3],cin,cout);
//mux's for sum
multiplexer2 mux_sum0(temp0[0],temp1[0],cin,S[0]);
multiplexer2 mux_sum1(temp0[1],temp1[1],cin,S[1]);
multiplexer2 mux_sum2(temp0[2],temp1[2],cin,S[2]);
multiplexer2 mux_sum3(temp0[3],temp1[3],cin,S[3]);

endmodule
CARRY LOOK AHEAD ADDER
module CarryLookAheadAdder(
input [3:0]A, B,
input Cin,
output [3:0] S,
output Cout
);
wire [3:0] Ci; // Carry intermediate for intermediate computation

assign Ci[0] = Cin;


assign Ci[1] = (A[0] & B[0]) | ((A[0]^B[0]) & Ci[0]);
//assign Ci[2] = (A[1] & B[1]) | ((A[1]^B[1]) & Ci[1]); expands to
assign Ci[2] = (A[1] & B[1]) | ((A[1]^B[1]) & ((A[0] & B[0]) | ((A[0]^B[0]) &
Ci[0])));
//assign Ci[3] = (A[2] & B[2]) | ((A[2]^B[2]) & Ci[2]); expands to
assign Ci[3] = (A[2] & B[2]) | ((A[2]^B[2]) & ((A[1] & B[1]) | ((A[1]^B[1]) &
((A[0] & B[0]) | ((A[0]^B[0]) & Ci[0])))));
//assign Cout = (A[3] & B[3]) | ((A[3]^B[3]) & Ci[3]); expands to
assign Cout = (A[3] & B[3]) | ((A[3]^B[3]) & ((A[2] & B[2]) | ((A[2]^B[2]) &
((A[1] & B[1]) | ((A[1]^B[1]) & ((A[0] & B[0]) | ((A[0]^B[0]) & Ci[0])))))));

assign S = A^B^Ci;
endmodule
CARRY SAVE ADDER
module carry_save_adder(input [3:0] a, b, c, d, output [3:0] sum, output carry);
wire [3:0] s1, s2;
assign s1 = a + b;
assign s2 = s1 + c;
assign sum = s2 + d;
assign carry = (s1 & b) | (s2 & c) | (sum & d); [^1^]
endmodule

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