UNIT-III

GATE LEVEL DESIGN

Introduction
The module (integrated circuit) is implemented in terms of logic gates and interconnections
between these gates. Designer should know the gate-level diagram of the design. In general,
gate-level modeling is used for implementing lowest level modules in a design like, full-adder,
multiplexers, etc. Boolean algebra is used to represent logical(combinational logic) functions of
digital circuits. A combinational logic expression is a mathematical formula which is to be
interpreted using the laws of Boolean algebra. Now the goal of logic design or optimization is to
find a network of logic gates that together compute the combinational logic function we want.
For example, given the expression a+b , we can compute its truth value for any given values of a
and b , and also we can evaluate relationships such as a+b = c. but logic design is difficult for
many reasons:
• We may not have a logic gate for every possible function, or even for every function of n
inputs.
• Not all gate networks that compute a given function are alike-networks may differ greatly in
their area and speed.
• Thus combinational logic expressions are the specification,
• A logic gate is an idealized or physical device implementing a Boolean function, that is, it
performs a logical operation on one or more logic inputs and produces a single logic output.
• Logic gates are primarily implemented using diodes or transistors acting as electronic
switches, but can also be constructed using electromagnetic relays (relay logic), fluidic logic,
pneumatic logic, optics, molecules, or even mechanical elements.
• With amplification, logic gates can be cascaded in the same way that Boolean functions can
be composed, allowing the construction of a physical model of all of Boolean logic.
• simplest form of electronic logic is diode logic. This allows AND and OR gates to be built, but
not inverters, and so is an incomplete form of logic. Further, without some kind of amplification
it is not possible to have such basic logic operations cascaded as required for more complex
logic functions.
• To build a functionally complete logic system, relays, valves (vacuum tubes), or transistors can
be used.
• The simplest family of logic gates using bipolar transistors is called resistor-transistor logic
(RTL). Unlike diode logic gates, RTL gates can be cascaded indefinitely to produce more complex
logic functions. These gates were used in early integrated circuits. For higher speed, the
resistors used in RTL were replaced by diodes, leading to diode-transistor logic (DTL).
• Transistor-transistor logic (TTL) then supplanted DTL with the observation that one transistor
could do the job of two diodes even more quickly, using only half the space.
• In virtually every type of contemporary chip implementation of digital systems, the bipolar
transistors have been replaced by complementary field-effect transistors (MOSFETs) to reduce
size and power consumption still further, thereby resulting in complementary metal–oxide–
semiconductor (CMOS) logic. that can be described with Boolean logic.
cMOS logic gates and other complex gates
General logic circuit Any Boolean logic function (F) has two possible values, either logic 0 or
logic 1. For some of the input combinations, F = 1 and for all other input combinations, F = 0. So
in general, any Boolean logic function can be realized using a structure as shown in figure.
• The switch S1 is closed and switch S is open for input combinations
that produces F = 1.
• The switch S1 is open and switch S2 is closed for input
combinations that produces F = 1.
• The switch S1 is open and switch S2 is open for input combinations
that produces F = 0.
Thus the output (F) is either connected to VDD or the ground, where
the logic 0 is represented by the ground and the logic 1 is represented
by V. So the requirement of digital logic design is to implement the
pull-upswitch(S1) and the pull-down switch(S).

CMOS static logic

A generalized CMOS logic circuit consists of two transistor nets nMOS and pMOS. The pMOS
transistor net is connected between the power supply and the logic gate output called as pull-
up network , Whereas the nMOS transistor net is connected between the output and ground
called as pull-down network. Depending on the applied input logic, the PUN connects the
output node to V and PDN connects the output node to the ground.

The transistor network is related to the Boolean function with a straight forward design
procedure:
• Design the pull down network (PDN) by realizing, AND (product) terms using series-connected
nMOSFETs. OR (sum) terms using parallel-connected nMOSFETS.
• Design the pull-up network by realizing,AND(product) terms using parallel-connected
nMOSFETs. OR (sum) terms using series-connected nMOSFETS.
• Add an inverter to the output to complement the function.
Some functions are inherently negated, such as NAND,NOR
gates do not need an inverter at the output terminal.
CMOS inverter
A CMOS inverter is the simplest logic circuit that uses one nMOS
and one pMOS transistor. The nMOS is used in PDN and the
pMOS is used in the PUN as shown in figure.
Working operation
1) When the input Vin is logic HIGH, then the nMOS transistor is ON and the pMOS transistor is
OFF.
Thus the output Y is pulled down to ground (logic 0) since it is connected to ground but not to
source V.
2) When the input V is logic LOW, then nMOS transistor is OFF and the pMOS transistor is ON,
Thus
the output Y is pulled up to V in (logic 1) since it is connected to source via pMOS but not to
ground.

CMOS NAND gate

The two input NAND function is
expressed by Y=A.B
Step 1 Take complement of Y
Y= A.B = A.B
Step 2 Design the PDN In this
case, there is only one AND
term, so there will be two
nMOSFETs in series as shown in
figure.
Step 3 Design the PUN. In PUN
there will be two pMOSFETs in
parallel , as shown in figure
finally join the PUN and PDN as
shown in figure which realizes
two –input NAND gate. Note that
we have
realized y, rather tat Y because
the inversion is automatically
provided by the nature of the
CMOS circuit
operation.

Working operation
1) Whenever at least one of the inputs is LOW, the
corresponding pMOS transistor will conduct while
the corresponding nMOS transistor will turn OFF.
Subsequently, the output voltage will be HIGH.
2) Conversely, if both inputs are simultaneously HIGH,
then both pMOS transistors will turn OFF, and
the output voltage will be pulled LOW by the two
conducting nMOS transistors.
CMOS NOR gate
The two input NOR function is expressed by Y=A+B
Step 1 Take complement of Y,Y= A+B = A+B
Step 2 Design the PDN In this case, there is only one OR term, so there will be two nMOSFETs
connected in
parallel, as shown in figure.
Step 3 Design the PUNIn PUN there will be two pMOSFETs in series , as shown in figure.

Finally join the PUN and PDN as shown in figure which realizes two –input NAND gate. Note
that we have realized y, rather tat Y because the inversion is automatically provided by the
nature of the cMOS circuit operation,

Working operation
1) Whenever at least one of the inputs is LOW, the corresponding pMOS transistor will conduct
while the corresponding nMOS transistor will turn OFF. Subsequently, the output voltage will
be HIGH.
2) Conversely, if both inputs are simultaneously HIGH, then both pMOS transistors will turn
OFF, and the output voltage will be pulled LOW by the two conducting nMOS transistors.
Complex gates in CMOS logic

A complex logic gate is one that implements a function that can provide the basic NOT, AND
and OR
operation but integrates them into a single circuit. CMOS is ideally suited for creating gates that
have logic equations by exhibiting the following, An AOI logic equation is equivalent to a
complemented SOP from, while an AOI equation is equivalent to a complemented POS
structure. In CMOS, output always produces NOT operation acting on input variable.

1) AOI Logic Function (OR) Design of XOR gate using CMOS logic.
AND-OR-INVERT logic function(AOI) implements operation in the order AND,OR,NOT. For
example ,
let us consider the function Y = AB+CD i.e., Y = NOT((A AND B)OR (C AND D)) The AOI logic gate
implementation for Y

CMOS implementation for Y

Step 1: Draw A.B (AND) function first by connecting 2 nMOS transistors in series.

2: Draw C.D implementation, by using 2 nMOS transistors in series.

Step 3: Y = A.B+C.D , In this function A.B and C.D are added, for addition , we have to draw
parallel
connection. So, A.B series connected in parallel with C.D as shown in figure.
Step 4: Draw pMOS connection,
 In nMOS A,B connected in series. So, in pMOS side, A.B should be connected in parallel.
 In nMOS C,D connected in series. So, in pMOS side, C.D should be connected in parallel.
 A.B and C.D networks are connected in parallel in nMOS side. So, in pMOS side, A.B and
C.D networks should be connected in series.
 In pMOS multiplication should be drawn in parallel, then addition should be drawn in
series as shown in figure.

Step 5: Take output at the point in between nMOS and pMOS networks.
1) OAI Logic Function (OR) Design of XNOR gate using CMOS logic.
OR-AND-INVERT logic function(AOI) implements operation in the order OR,AND,NOT. For
example ,let
us consider the function Y = (A+B).(C+D) i.e., Y = NOT((A OR B)AND (C OR D))
The OAI logic gate implementation for Y

SWITCH LOGIC
1) Switch logic is mainly based on pass transistor or transmission gate.
2) It is fast for small arrays and takes no static current from the supply, V DD. Hence power
dissipation of such arrays is small since current only flows on switching.
3) Switch (pass transistor) logic is analogous to logic arrays based on relay contacts; where in
path through each switch is isolated from the logic levels activating the switch.
PASS TRANSISTOR
1) This logic uses transistors as switches to carry logic signals from node to node instead of
connecting output nodes directly to V or ground(GND)
2) If a single transistor is a switch between two nodes, then voltage degradation equal to VDD
(threshold voltage) for high or low level depends up on nMOS or pMOS logic.
3) When using nMOS switch logic no pass transistor gate input may be driven through one or
more pass transistors as shown in figure.

4) Since the signal out of pass transistor T1 does not reach a full logic 1 by threshold voltage
effects signal is degraded by below a tru e logic 1, this degraged voltage would not permit the
output of T to reach an acceptable logic 1 level.

Advantages
They have topological simplicity.
1) Requires minimum geometry.
2) Do not dissipate standby power, since they do not have a path from supply to ground.
Disadvantages
1) Degradation in the voltage levels due to undesirable threshold voltage effects.
2) Never drive a pass transistor with the output of another pass transistor.
TRANSMISSION GATE
1) It is an electronic element, good non-mechanical relay built with CMOS technology.
2) It is made by parallel combination of an nMOS and pMOS transistors with the input at gate of
one transistor being complementary to the input at the gate of the other as shown in figure.
3) Thus current can flow through this element in either direction.
4) Depending on whether or not there is a voltage on the gate, the connection between the
input and output is either low resistance or high-resistance, respectively Ron = 100Ω and R > 5
MΩ.
Operation
• When the gate input to the nMOS transistor is ‘0’ and the complementary ‘1’ is gate input to
the pMOS , thus both are turned off.
• When gate input to the nMOS is ‘1’ and its complementary ‘0’ is the gate input to the pMOS ,
both are turned on and passes any signal ‘1’ and ‘0’ equally without any degradation.
• The use of transmission gates eliminates the undesirable threshold voltage effects which give
rise to loss of logic levels in pass-transistors as shown in figure
Advantages
1) Transmission gates eliminates the signal degradation in the output logic levels.
2) Transmission gate consists of two transistors in parallel and except near the positive and
negative rails.
Disadvantages
1) Transmission gate requires more area than nMOS pass circuitry.
2) Transmission gate requires complemented control signals.
“ Transmission gate logic can be used to design multiplexers(selector functions)”.

Design a 2-input multiplexer using CMOS transmission gates.

Figure shows a 2-input multiplexer circuit using

CMOS transmission gate.

If the control input S is low, the TG0 conducts

and the output F is equal to A. On the other
hand, if the control input S is high the TG1
conducts and the output F is equal to B.

ALTERNATIVE GATE CIRCUITS

CMOS suffers from increased area and
correspondingly increased capacitance and
delay, as the logic gates become more
complex. For this reason, designers developed
circuits (Alternate gate circuits) that can be
used to supplement the complementary type
circuits. These forms are not intended to
replace CMOS but rather to be used in special
applications for special purposes.
PSEUDO nMOS Logic
Pseudo nMOS logic is one type of alternate
gate circuit that is used as a supplement for the complementary MOS logic circuits. In the
pseudo-nMOS logic, the pull up network (PUN) is realized by a single pMOS transistor. The
gate terminal of the pMOS transistor is connected to the ground. It remains permanently in
the ON state. Depending on the input combinations, output goes low through the PDN.
Figure shows the general building block of logic circuits that follows pseudo nMOS logic.
Here, only the nMOS logic (Qn) is driven by the input voltage, while the gate of p-
transistor(Qp) is connected to ground or substrate and Qp acts as an active load for Qn.
Except for the load device, the pseudo-nMOS gate circuit is identical to the pull-down
network(PDN) of the complementary CMOS gate. The realization of logic circuits using
pseudo-nMOS logic is as shown in figure.
Advantages
1) Uses less number of transistors as compared to CMOS logic.
2) Geometrical area and delay gets reduced as it requires less transistors.
3) Low power dissipation.
Disadvantages
1) The main drawback of using a pseudo nMOS gate instead of a CMOS gate is that the
always on PMOS load conducts a steady current when the output voltage is lower than
VDD.
2) Layout problems are critical.
DYNAMIC CMOS LOGIC
A dynamic CMOS logic uses charge storage and clocking properties of MOS transistors to
implement logic operations. Figure shows the basic building block of dynamic CMOS logic.
Here the global clock ø drives nMOS evaluation transistor and pMOS precharge transistor. A
logic is implemented using an nFET array connected between output node and ground. The
gate (clock ø) defines two phases, evaluation and precharge phase during each clock cycle.

Working
 When clock ø = 0 the circuit is in precharge phase with the pMOS device Mp ON and
the evaluation nMOS Mn OFF. This establishes a conducting path between VDD and
the output allowing Cout to charge to a voltage Vout = VDD. Mp is often called the
precharge FET.

 When clock ø = 1 the circuit is in evaluation phase with the pMOS device Mp
OFF and the evaluation nMOS Mn ON. If the logic block acts like a closed switch the
Cout can discharge through logic array and Mn, this gives a final result of Vout =
VDD, logically this is an output of F = 1. Charge leakage eventually drops the output to
Vout = 0 Vwhich could be an incorrect logic value.

The logic formation is formed by three series connected FETs (3-input NAND gate) is
shown in figure.
 The dynamic CMOS logic circuit has a
serious problem when they are
cascaded. In the precharged phase (ø
=0) , output of all the stages are pre-
charged to logic high. In the evaluation
phase (ø = 1), the output of all stages
are evaluated simultaneously. Suppose
in the first stage, the inputs are such
that the output is logic low after the
evaluation. In the second stage, the
output of the first stage is one input and
there are other inputs. If the other
inputs of the second stage are such that
output of it discharges to logic low, then
the evaluated output of the first stage
can never make the output of the
second stage logic high. This is because,
by the time the first stage is being
evaluated, output of the second. Stage
is discharged, since evaluation happens
simultaneously. Remember that the
output cannot be charged to logic high
in the evaluation phase (ø = 1, pMOSFET in PUN is OFF), it can only be retained in the logic high
depending on the inputs.
Advantages
1. Low power dissipation.
2. Large noise margin.
3. Small area due to less number of transistors.

CMOS DOMINO LOGIC

Standard CMOS logic gates need a PMOS and an NMOS transistor for each logic input. The
pMOS transistors require a greater area tan the nMOS transistors carrying the same current.
So, a large chip area is necessary to perform complex logic operations. The package density in
CMOS is improved if a dynamic logic circuit, called the domino CMOS logic circuit, is used.
Domino CMOS logic is slightly modified version of the dynamic CMOS logic circuit. In this case,
a static inverter is connected at the output of each dynamic CMOS logic block. The addition of
the inverter solves the problem of cascading of dynamic CMOS logic circuits. The circuit
diagram of domino CMOS logic structures as shown in figure as follows
 A domino CMOS AND-
OR gate that realizes
the function y = AB +
CD is depicted in
figure. The left hand
part of the circuit
containing Mn,Mp,
T1,T2,,T3,and T4 forms
and AND-OR-
INVERTER (AOI) gate.
It derives the static
CMOS inverter formed
by N2 and P2 in the
right-hand part of the
circuit. The domino gate is activated by the single phase clock ø applied to the NMOS (Mn)
and the PMOS (Mp) transistors. The load on the AOI part of the circuits is the parasitic load
capacitance.
Working
 When ø = 0, is ON and Mn is OFF, so that no current flows in the AND-OR paths of the
AOI. The capacitor CL is charged to VDD through Mp since the latter is ON. The input to
the inverter is high, and drives the output voltage V0 to logic-0.

 When ø = 1, Mp is turned OFF and Mn is turned ON. If either (or both) A and B or C
and D is at logic-1, CL discharges through either T2,T1 and Mn or T3,T4 and Mp. So , the
inverter input is driven to logic-0 and hence the output voltage V0 to logic-1. The

Boolean expression for the output voltage is Y = AB + CD. Note : Logic input can change
only when ø = 0. No changes of the inputs are permitted when ø = 1 since a discharge
path may occur.
Advantages
1) Smaller areas compared to conventional CMOS logic.
2) Parasitic capacitances are smaller so that higher operating speeds are possible.
3) Operation is free of glitches since each gate can make one transition.
Disadvantages
1) Non inverting structures are possible because of the presence of inverting buffer.
2) Charge distribution may be a problem.
CLOCKED CMOS LOGIC
The clocked CMOS logic is also referred as C2MOS logic. Figure shows the general arrangement
of a clocked CMOS (C2MOS) logic. A pull-up p-block and a complementary n-block pull-down
structure represent p and n-transistors respectively and are used as implement clocked CMOS
logic shown in figure. However, the logic in this case is connected to the output only during the
ON period of the clock. Figure shows a clocked inverter circuit which is also belongs to
clocked CMOS logic family. The slower rise times and fall times can be expected due to
owing of extra transistors in series with the output.

Working
•When ø = 1 the circuit acts an
inverter , because transistors Q3 and
Q4 are ‘ON’ . It is said to be in the
“evaluation mode”. Therefore the
output Z changes its previous value.
•When ø = 0 the circuit is in hold
mode, because transistors Q3 and Q4
becomes ‘OFF’ . It is said to be in the
“precharge mode”. Therefore the
output Z remains its previous value.
n-p CMOS LOGIC
Figure shows the another variation of basic dynamic logic arrangement of CMOS logic called
as n-p CMOS logic. In this, logic the actual logic blocks are alternatively ‘n’ and ‘p’ in a cascaded
structure. The clock ø and ø- are used alternatively to fed the precharge and evaluate
transistors. However, the functions of top and bottom transistors are also alternate
between precharge and evaluate transistors.

Working
• During the pre charge
phase ø = 0 , the output
of the n-tree gate, OUT 1
OUT3 , are charged to
VDD, while the output of
the p-tree gate OUT2 is
pre discharged to 0V.
Since the n-tree gate
connects pMOS pull-up
devices, the PUN of the p-
 tree is turned off at that time.
• During the evaluation phase ø = 1, the outputs (OUT1,OUT3) of the n-tree gate can only
make a 1- 0 transition, conditionally turning on some transistors in the p-tree. This ensures
that no accidental discharge of OUT 2 can occur.
• Similarly n-tree blocks can follow p-tree gates without any problems, because the inputs to
the n-gate are pre charged to 0.
Disadvantages
Here, the p-tree blocks are slower than the n-tree modules, due to the lower current
drive of the pMOS transistors in the logic network.

PHYSICAL DESIGN:
INTRODUCTION
The physical design of VLSI-chips is a very complex optimization problem, which is normally
solved in various sub-steps. Because there are many interdependencies between these sub-
steps it is recommendable to combine some of them.
PHYSICAL VLSI-DESIGN
The design-cycle of VLSI-chips consists of different consecutive steps from high-level synthesis
(functional design) to production (packaging). The physical design is the process of transforming
a circuit description into the physical layout, which describes the position of cells and routes for
the interconnections between them. Figure 1shows a schematic representation of a layout. The
main concern in the physical design of VLSI-chips is to find a layout with minimal area, further
the total wirelength has to be minimized.

Due to its complexity, the physical design is normally broken in various sub-steps:
First the circuit has to be partitioned to generate some (up to 50) macro cells. In
the floorplanning phase the cells have to be placed on the layout surface. After placement
the global routing has to be done. In this step the `loose' routes for the interconnections
between the modules called macro cells are determined.
In the detailed routing the exact routes for the interconnection wires in the channels between
the macro cells have to be computed. The last step in the physical design is the compaction of
the layout, where it is compressed in all dimensions so that the total area is reduced. This
classical approach of the physical design is strongly serial with many interdependencies
between the sub-steps. For example during floorplanning and global routing there must be
enough routing space reserved to complete the exact wiring in the detailed routing phase.
Otherwise the placement has to be corrected and the global routing has to be computed again.

Floorplanning
A floorplanning is the process of placing blocks/macros in the chip/core area,
thereby determining the routing areas between them. In the floorplanning phase, the macro
cells have to be positioned on the layout surface in such a manner that no blocks overlap and
that there is enough space left to complete the interconnections. The input for the
floorplanning is a set of modules, a list of terminals (pins for interconnections) for each module
and a netlist, which describes the terminals which have to be connected. At this stage, good
estimates for the area of the single macro cells are available, but their exact dimensions can still
vary in a wide range. Consider for example a register file module consisting of 64 registers. It
can be organized as a 1X64, 2X32, 4X16, or 8X8 array which yields four implementations with
different aspect ratios. Floorplan determines the size of die and creates wire tracks for
placement of standard cells. It creates power ground (PG) connections. It also determines the
I/O pin/pad placement information.
Fig: Layout of a chip showing Floorplan.

A good floorplanning should meet the following

constrains.
•Minimize the total chip area,
•Make routing phase easy (routable),
•Improve the performance by reducing signal
delays.
Inputs for floorplan
•Synthesized netlist (.v, .vhdl)
•Design Constrains (SDC)
•Physical partitioning information of the design
•IO placement file (optional)
•Macro placement file (optional)
•Floorplanning control parameters.
Output of floorplan
•Die/Block area
•I/O pad/placed
•Macro placed
•Power grid design
•Power pre-routing
•Standard cell placement areas.
Design of Floorplan
Placing of Large Macros with defined core area, I/O Macros placing in periphery area which ,
includes power , ground and signal pad placement, Establishment of power and ground grid
(Rings and Straps)
Utilization is Design Area/Allocated Area
The placement of Standard cells and Macros with goal of 100% typically 80-85%
It is always better to give 65-70% which may help 30% for optimization , Hold Fixing , clock tree
synthesis , Signal Integrity , Routing ,Congestion

Floor Planning Considerations

Gate count estimation: Rough estimation is needed to calculate die size.
Critical Port placement: In Top-Down approach port location is decided by considering all blocks
location and communication between blocks. Moving ports a little does not vary but more leads
to routing and timing issues.
Fig: Floor planning output
Floor Planning Guide lines
 Checking of net connection from macro to macro and
macro to standard cells.
 More number of connection from macro to macro
place them near to each other most preferred is near core
boundaries
 If i/p pin is connected to macro place near to pin or pad
which is better.
 More connections of macro to standard cells
spread macro inside core area.
 Avoid criss cross placement of macros in order to save routing resources as well as from
routing , Placement and congestion issues.
 Soft Blockage: During placement that block is maintained free from standard cells and during
optimization buffers are placed in that block in-order to meet timing.
 Hard Blockage: It doesn’t allow any placement during optimization.
 Partial Blockage: If it is given 20%. Then 20% of placement is blocked during placement
providing spacing between macros to avoid congestion around macros.
 Go for iterative process of different floor plans when timing is not closing.
 Typically, macros are placed around edges of blocks, keeping one large main are for standard
cells
 Leave a hallow space between macros on all sides.
 For non-pin sides of macros a minimal separation is adequate,
 For pin sides of macros a larger separation is appropriate,
 Allow channels for routing, pin access and possible buffer insertion,
 Leave space between macros and edge of block, to allow for buffer insertion and power
stripes to feed standard cell rows between macro and block edge.
Placement
Placement is the process of placing standard cells in the rows created at floorplanning stage.
The goal is to minimize the total area and interconnects cost. The quality of routing is highly
determined by the placement.
Inputs for Placement stage:
•Gate level netlist,
•Floor planned design,
•Design libraries,
•Design constrains,
•Technology file.

Needs of Placement
Placement is a critical step in VLSI design flow mainly for the following four reasons
Placement is a key factor in determining the performance of a circuit. Placement largely
determines the length and hence, the delay of interconnects wires. Interconnects delay can
consumes as much as 75% of clock cycle in advance design. Therefore, a good placement
solution can substantially improve the performance of a circuit.

Placement determines the routing ability of a design. A well constructed placement solution
will have less routing demand (i.e., shorter total wire length) and will distribute the routing
demand more evenly to avoid routing hotspots. Placement decides the distribution of heat on a
die surface. An uneven temperature profile can lead to reliability and timing problems.

Power consumption is also affected by placement. A good placement solution can be reduce
the capacitive load because of the wires (by having shorter wire and larger separation between
adjacent wires). Hence the switching power consumption can be reduced.

Global Placement

The objective of global placement is to minimize the interconnect wire lengths and aims at
generating a rough placement solution that may violate some placement constrains (e.g., there
may be overlaps among modules) while maintaining a global view of whole netlist.
Detailed Placement

The objective of detailed placement is to meet design constraints such as Timing/Congestion

and to finalize standard cell placement. Detailed placement further improves the placement
solution in an iterative manner by rearranging a small group of modules in a local region while
keeping all other modules fixed.
ROUTING
The aim of the routing phase is to find the geometrical layouts for all nets. In the floorplanning
phase space on the layout surface has been provided to complete the interconnections. This
space can be described as a collection of single routing regions. Each region has a fixed capacity,
i.e. a maximum number of wires which can be routed through this region, and a number of
terminals, i.e.\ pins on the borders of the adjacent cells.
Due to the complexity, the routing is done in two sub-phases. In the global routing, the `loose'
routes for the nets are determined. For the computation of the global routing, the routing
space is represented as a graph, the edges of this graph represent the routing regions and are
weighted with the corresponding capacities (fig. 3). The global routing is described by a list of
routing regions for each net of the circuit, with none of the capacities of any routing region
being exceeded.

Figure 3: A routing graph (left) and a Figure 4: The detailed routing inside a channel
Global route for a four terminal net (right)
After global routing is done, for each routing region the number of nets routed through it is
known. In the detailed routing phase the exact routes for the wires have to be determined
(figure 4). This is done incrementally, i.e. one channel is routed at a time in a predefined order.

The global routing can be solved by graph based techniques, Integer Programming or
hierarchical approaches. For the detailed routing there exist solutions based on Greedy
Methods, graph algorithms or hierarchical approaches. The complexity and routability of a
layout depends on the number of layers which can be used for the completion of the
interconnections. Usually in macro cell layout there are two layers and the routing is done in
the manhattan-model, i.e. one layer is for the vertical, the other for the horizontal wires and
the nets change the layer when changing their direction.

ROUTING
It is important for the physically deciding the path of actual circuit. Proper routing stands for
minimizing the wire length.
Check Points for checking the proper routing
DRC: Design rule check
A tool for verifying the layout with the physical layout design rules set so as, to make sure that
none of the rules have been violated.
LVS: Layout versus schematic
It is the method to check the correctness of your layout designed by cross checking with netlist
generated from schematic using the tool.
Timing
After Clock Tree Synthesis (CTS), the routing process determines the precise path for
interconnection. This includes the standard cell & macro pins, the pins on the block boundary
or pads at the chip boundary.
In routing stage, metal & VIAs are used to create the electrical connection in layout so as, to
complete all connection defined by netlist.

Most of the routers available are grid base router. There are routing grids defined for the entire
layout. Consider it like graph. For grid based routers, they prefer routing direction defined for
each metal layer.
Consists of following steps
Global routing - here, only the routing resources are assigned to the routing end points.
Final/ Detailed routing - here, nets are physically routed
Search and Repair (remove violations like short, spacing etc)
Routing in done on routing grid.

This is a plan of the chip,

Shows the module/blocks

Floorplanning tools will help

position large blocks, rotating,
flipping to minimize the routing
between blocks. Helps predict
wiring loads and area of chip.
Floorplan budgets area, wire
area/delay. Make sure the pieces
fit together as planned. Implement
the global layout
Input Required
 Design netlist
 Area requirements
 Power requirements
 Timing constraints
 Physical partitioning information
 Die size vs. performance tradeoff
Optional
 I/O placement
 Macro placement information
Types of Routing
Two levels of routing
 Global: notional set of abutting channels
 Local: actual geometry required to complete signal connections
Two types of routing Types of Routing
 Channel routing
 Channel may grow in one dimension to accommodate wires
 Pins generally on only two sides
 Switchbox routing
 Cannot grow in any dimension
 Pins are on all four sides, fixing dimensions of the box
Global Routing
 Goal: assign wires to paths through channels
 Don’t worry about exact routing of wires within channel
 Final step is the detailed routing Global Routing and Detailed Routing
 Channel utilization
 Can estimate channel height from global routing using congestion
 Keep all channels about equally full to minimize wasted area
Detailed Routing
 Picking exact route of the wires
 Pay attention to the actual timing constraints
 Route time‐critical signals first
 Shortest path may not be best for global wiring
 May need to rip‐up wires and reroute to improve the global routing