Organization
& Architecture
Machine Instructions and Addressing Modes
Outcome
✩ Idea of Microcomputer Organization.
✩ Why Machine Instructions & Addressing Modes are necessary.
Designing Programming
Specific Computers Generic Computers
Processor
Designing Programming
Architects
Designing a Generic Computer:
Memory
Memory
Processor i/p
Memory
R4
Processor i/p
Memory
R4
Processor
R2
Processor
R4
Processor
R2
Processor
“Spilling”
R2
Processor
Memory
R2
Processor
#instructions
● Arithmetic Operations (Addition, Subtraction, Division, Multiplication)
● Logical Operations (AND, OR, NOT)
R1
R2
ALU
R3
R4
Memory
● Arithmetic Operations (Addition, Subtraction, Division, Multiplication)
● Logical Operations (AND, OR, NOT)
R1
R2
ALU
R3
R4
Memory
● Arithmetic Operations (Addition, Subtraction, Division, Multiplication)
● Logical Operations (AND, OR, NOT)
R1
R2
ALU
R3
R4
Memory
Desiρninρ a Generic Computer:
● Arithmetic Operations (Addition, Subtraction, Division, Multiplication)
● Logical Operations (AND, OR, NOT)
RD
R1
WR
ALU R2
R3
Timing
&
Control Unit R4
Memory
● Arithmetic Operations (Addition, Subtraction, Division, Multiplication)
● Logical Operations (AND, OR, NOT)
R1
ALU R2
R3
Timing
&
Control Unit R4
Register Section
Memory
Desiρninρ a Generic Computer:
● Arithmetic Operations (Addition, Subtraction, Division, Multiplication)
● Logical Operations (AND, OR, NOT)
● Arithmetic Operations (Addition, Subtraction, Division, Multiplication)
● Logical Operations (AND, OR, NOT)
R1
ALU R2
R3
Timing
&
Control Unit R4
Register Section
➤ Objective
➤ Cost
Architects
➤ Objective
➤ Cost 1KB Memory
1 Byte
9\chitects
➤ Objective
➤ Cost 1KB Memory
R1
R2
4 x 24
8-bit Decoder
Adder
R3 1 Byte
R4
10 x 210
CU
Decoder
IR R16
Note: The elaborated study and implementation of all these
phases is called Computer Architecture. 9\chitects
➤ Objective
➤ Cost
Programmers
Desiρninρ a Generic Computer:
➤ Objective Instruction Set / Machine Instruction
Architects Programmers
Instructions:
● Sequence of bits.
Instructions
Memory
Instructions:
● Sequence of bits.
Instruction Register
Processor
Memory
Typical Structure of Instructions:
Mode OPCODE Operand
e.g. ADD
The Data or the address of the Data.
SUB
INC
MUL
BR etc.
The interpretation of the Operand bits is given by the Mode bits.
● For 0-Address instructions (i.e. the operand bits are all 0s), the mode is
insignificant.
● For 1-Address instructions, the operand bits store the address of 1operand.
● For 2-Address instructions, the operand bits store the address of 2 operands.
Organization
& Architecture
Organizations Based on Reρisters (Part 1)
Outcome
✩ Types of Computer Organizations.
✩ How Single Accumulator Organization works.
Typical Structure of Instructions:
Mode OPCODE Operand
e.g. ADD
The Data or the address of the Data.
SUB
INC
MUL
BR etc.
The interpretation of the Operand bits is given by the Mode bits.
● For 0-Address instructions (i.e. the operand bits are all 0s), the mode is
insignificant.
● For 1-Address instructions, the operand bits store the address of 1operand.
● For 2-Address instructions, the operand bits store the address of 2 operands.
Computer Organizations Based on Registers:
-- Depending on the Computer’s Organization, the type of the instructions
may vary.
Computer Organization
Single Accumulator General Register
STACK Organization
Organization Organization
● Only basic registers are used.
Instruction Decoder
Memory
IR AR PC
System Bus
DR Acc
I/O
ALU
● Only basic registers are used.
● 0-Address and 1-Address Instructions are used.
0-Address lnstructions:
These instructions d o n ’ t have operand mentioned in them, rather
the operation is described along with the operand, inherently.
E.g. CMA
Accumulator
Single Accumulator Organization-Usefulness:
● If we try to reduce the number of addresses from the instruction, we
can effectively reduce the size of the instruction.
● Results in, significantly reduced Cost of the system.
Organization
Architecture
Organizations Based on Registers (Part 2)