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Module 2 Detailed Answers-1

The document provides detailed answers on various topics in computer architecture, including the differences between hardwired and microprogrammed control units, memory hierarchy, and specifics of direct mapped cache configurations. It outlines the characteristics of hardwired and microprogrammed control units, explains the structure of memory hierarchy, and presents calculations for cache configurations with varying sizes and block sizes. Each question is answered with precise technical details and calculations relevant to computer systems design.

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Bhavesh Digey
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9 views2 pages

Module 2 Detailed Answers-1

The document provides detailed answers on various topics in computer architecture, including the differences between hardwired and microprogrammed control units, memory hierarchy, and specifics of direct mapped cache configurations. It outlines the characteristics of hardwired and microprogrammed control units, explains the structure of memory hierarchy, and presents calculations for cache configurations with varying sizes and block sizes. Each question is answered with precise technical details and calculations relevant to computer systems design.

Uploaded by

Bhavesh Digey
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Module 2 - Detailed Answers

Q1. Difference between Hardwired and Microprogrammed Control


Unit

Hardwired Control Unit Microprogrammed Control Unit


Fixed hardware logic generates control signals
Microinstructions generate control signals
Very fast Comparatively slower
Difficult to modify Easy to modify
Used in RISC Used in CISC

Q2. Memory Hierarchy

Registers → Cache → Main Memory → Secondary Memory As we move down: • Size increases •
Speed decreases • Cost per bit decreases

Q3. Direct Mapped Cache (16KB, 256B block, 128KB main


memory)

Main memory = 128KB = 2^17 bytes → 17 address bits Block size = 256B = 2^8 → Offset = 8 bits
Cache lines = 16KB / 256B = 64 = 2^6 → Index = 6 bits Tag = 17 − (6 + 8) = 3 bits Tag directory
size = 64 × 3 = 192 bits

Q4. Direct Mapped Cache (512KB, 1KB block, Tag=7 bits)

Cache lines = 512KB / 1KB = 512 = 2^9 → Index = 9 bits Block size = 1KB = 2^10 → Offset = 10
bits Total address bits = 7 + 9 + 10 = 26 bits Main memory size = 2^26 bytes = 64MB Tag directory
size = 512 × 7 = 3584 bits

Q5. Direct Mapped Cache (4KB block, 16GB main memory,


Tag=10 bits)

Main memory = 16GB = 2^34 bytes → 34 address bits Block size = 4KB = 2^12 → Offset = 12 bits
Index = 34 − (10 + 12) = 12 bits Cache lines = 2^12 = 4096 Cache size = 4096 × 4KB = 16MB Tag
directory size = 4096 × 10 = 40960 bits

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