Module – 1

Introduction To Computer
Architecture and Organization
 Agenda
• Registers
• Register files
• Interconnection of components
• IAS machine
• Von Neumann and Harvard
Architecture
• RISC and CISC Architecture
 Registers
• Registers are very fast computer memory
th at i s u s e d to e x e c u te p r o g ram s an d
operations efficiently.
• Fast retrieval of data for processing by CPU
• Top of the Memory hierarchy
 Registers
• CPU mu s t h ave s ome working s pace
(temporary storage) called registers
• Top level of memory hierarchy
• General purpose Registers: - Used to store
temporary data during any ongoing operation
R1, R2, R3….
• S p e c i al p urp o se re g i ste rs: - hav e sp e c i f ic
functions
• Control registers: - Control the settings of CPU
 Special purpose registers
– Accumulator : This is the most frequently used register
used to store data taken from memory
– Program Counter (PC)
– Instruction Register (IR)-Contains the instruction most
recently fetched
– Memory Address Register (MAR) – contains the
address of location in memory
– Memory Buffer Register (MBR) – contains a word of
data to be written to memory or the word most recently
read
– Stack pointers (SP) – Points to the top of the stack
memory
– Segment registers –pointing to each segment of the
meory
 Status/ Flag/ Condition code
registers
Contains status information
Condition Codes
Sign
Zero
Carry
Overflow
Interrupt enable/disable
Supervisor
– It is also known as PSW (Program Status
Word)
Example Register Organizations

Understatement: There is no universally accepted philosophy

for organizing the processor registers
 Register Files (RF)
• Set of general-purpose registers.
• It functions as small RAM and
implemented using fast RAM technology.
• RF needs several access ports
simultaneously reading from or writing to
several registers. Hence RF is known as
multiport RAM.
• A standard RAM has just one access port
with an associated address bus and data
bus.
 Register file & Control unit
CPU Memory

Datapath
PC
Data
IR
Register File

Address
Control
ALU Unit
 A register file with three access ports -
symbol

Data in C
16
Address C 2
Port C

Register File
RF
2 2
Address A Port A Port B Address B
16 16
Data out A Data out B
 A Register File with three access ports – logic diagram

Ex: R3 ← R1 + R2
Data in C
Read Address A =
16
Write 11 2
01
4-way 16-bit
address C S demultiplexer Read Address B = 10
16 16 16
Write Address C =
16
11
0101
16-bit register R3 16-bit register R2 16-bit register R1 16-bit register R0
16 16
●
16 ●
● 16
●

2 4-way 16-bit 4-way 16-bit 2

S S
01 multiplexer multiplexer
Read Read
address A 16 16 address B
Data out A
Data out B
 A Register File with three access ports – logic diagram

1011 Ex: R3 ← R1 + R2
Data in C
Read Address A =
16
2
01
4-way 16-bit
Write
address C
11 S demultiplexer Read Address B = 10
16 16 16
Write Address C =
16
11
0110 0101
16-bit register R3 16-bit register R2 16-bit register R1 16-bit register R0
16 16
●
16 ●
● 16
●

2 4-way 16-bit 4-way 16-bit 2

S
01 multiplexer multiplexer S
10
Read Read
address A 16 16 address B
Data out A
Data out B
Interconnection of
components
 Interconnection of components
• The functional components of a computer
need to commu nicate with each oth er to
perform a task.
• Therefore, computer is a network of
components.
• The collection of paths connecting the various
components is called the interconnection
structure.
• The design of this structure will depend on the
exchanges that must be made among
modules.
 Input and output of a Memory
 Two Operations Component
 Read
 Input
 Enable Read Control signal
 Provide the address on address bus from where the data to
read
 Output
 Data from the given address

 Write
 Input
 Enable Write control signal
 Provide the address on address bus where the data to be
written
 Provide the data to be written on data bus
 Output
 -
 Input and Output of I/O Module
 I/O Module may control more
than one external device.
 E a ch o f the i nter f a ce to a n
external device is referred as a
por t and given each a unique
address (e.g., 0, 1, . . .
,M– 1)
 Finally, an I/O module may be
able to send interrupt signals to
the processor.
 Input and Output of Processor
component
 The processor reads in instructions and data,
writes out data after processing, and uses control
signals to control the overall operation of the
system.
 It also receives interrupt signals.
 Interconnections

 The interconnection structure must

s u ppo r t t h e f o l l o w i n g t y pe s o f
transfers:
 Memory ↔ Processor
 I/O ↔ Processor
 I/O ↔ Memory (DMA)
 Bus Interconnection
 It is a path way connecting two or more
devices.
 A bus consists of multiple
communication pathways, or lines.
 E ac h l i ne i s c apabl e o f t ransmi t t i ng
signals representing binary 1 and binary 0.
 Transmitting a word across a single line
(bit by
bit serially)
 Several lines of a bus can be used to
transmit binary digits simultaneously (in
parallel).
 For example, an 8-bit unit of data can
be transmitted over eight bus lines.
 A bus that connects major computer
 Bus
 The lines can be classif ied into three functional
groups: data, address, and control lines
 Data Lines – Data bus – provide a path for
moving data among system modules.
 The data bus may consist of 32, 64, 128, or even
more separate lines, the number of lines being
referred to as the width of the data bus.
 If the data bus is 32 bits wide and each instruction
is 64 bits long, then the processor must access the
memory module twice during each instruction
cycle.
 Address Bus
 Address Lines – Address Bus – Used to designate the
source or destination of the data on the data bus.
 For example, if the processor wishes to read a word (8
, 16, or 32 bits) of data from memory, it puts the
address of the desired word on the address lines.
 Typically, the higher-order bits are used to select a
particular module(Memory/IO) on the bus, and the
lower-order bits select a memory location or I/O port
within the module.
 For exam p l e, on an 8 - b i t ad d ress b us, ad d ress
01111111 and below might reference locations in a
memory module with 128 words of memory, and
ad d re ss 1 0 0 0 0 0 0 0 and ab ov e re fe r to d ev i c e s
 Control Bus
 The control lines are used to control the access to
and the use of the data and address lines.
 Because the data and address lines are shared by all
components, there must be a means of controlling
their use.
 Control signals transmit both command and timing
information among system modules.
 Timing signals indicate the validity of data and
address information.
 C o m m a n d s i g n a l s s p e c i f y o p e ra t i o n s t o b e
performed.
 Typical control lines include
 Memory write: Causes data on the bus to be
written into the addressed location
 Memor y read: Caus es data from the
addressed location to be placed on the bus
 I/O write: Causes data on the bus to be
output to the addressed I/O port
 I/O read: Causes data from the addressed
I/O port to be placed on the bus
 Transfer ACK: Indicates that data have been
accepted from or placed on the bus
 Typical control lines include
 Bus request: Indicates that a module needs
to gain control of the bus
 Bus grant: Indicates that a reques ting
module has been granted control of the bus
 Interrupt request: Indicates that an interrupt
is pending
 Interrupt ACK: Acknowledges that the
pending interrupt has been recognized
 Clock: Is used to synchronize operations
 Reset: Initializes all modules
 The operation of the bus

 If one module wishes to send data to another,

it must do two things:
 Obtain the use of the bus, and
 Transfer data via the bus.
 If one module wishes to request data from
another module, it must
 Obtain the use of the bus, and
 Transfer a request to the other module over the
appropriate control and address lines.
 It must then wait for that second module to
send the data.
 I/O Bus and Memory Bus
• Functions of Buses
 MEMORY BUSis for information transfers between CPU and
the Main Memory
 I/O BUS is for information transfers between CPU and I/O
devices through their I/O interface
• Many computers use
 a common single bus system for both memory and I/O interface
units
 separate control lines for each function
 common control lines for both functions
• Some computer systems use two separate buses
 one to communicate with memory and
 the other with I/O interfaces
 Isolated I/O – I/O Mapped I/O
 Separate I/O read/write control lines in addition to
memory read/write control lines
 Separate (isolated) memory and I/O address
spaces
 Distinct input and output instructions
 When CPU fetches and decodes the opcode of an
I/O instruction, it places the address into the
common address bus.
 Also enab les read/ write c ontrol lines => the
address in the address lines is for interface register
and not for a memory word.
 Isolated I/O

Dat
a
Addres
Read M Read IO
s
Write M
Write IO

Main CPU IO Port 1 IO Port 2 IO Port 3

Memory

IO Device A IO Device
B
Memory Mapped I/O
 A single set of read/write
control lines.
No distinction between memory
and I/O
 Memory and I/O addresses
share the common address space
 reduces memory address range available
 Memory addresses xffff0000 and above are used for
I/O devices
 No specif ic input or output instruction. The
same memory reference instructions can be
used for I/O transfers
Difference between memory-
mapped I/O and Isolated I/O
IAS Machine

Organization of the von Neumann machine
IAS – a prototype developed by John Von Neumann in 1946 at
Princeton

University. (Institute
Structure for Advanced
of Von NeumannStudy)
machine(IAS Computer)
IAS – Contd..
Memory Formats
1000 x 40 bit words ( 1000 storage locations of 40 binary bits each)
– Binary number( both data and instructions are stored here)
Number Format
– Each number is represented by a sign bit and a 39 bit value.
Instruction Format
- 20-bit instruction, 8-bit operation code (opcode)
-12-bit address
 IAS – memory format
• 1000 x 40 bit words ( 1000 storage locations of 40 binary
bits each)
– Binary number( both data and instructions are stored
here)
• Number Format:
– Each number is represented by a sign bit and a 39 bit
value.
• Instruction Format:
– A word may contain 20 bit instruction with each
instruction consisting of an 8 bit operation code
(opcode) specifying the operation to be performed
and a 12 bit address designating one of the words in
memory (0 to 999)
 IAS – Contd..

IAS – Total 21 Instructions

– Data Transfer
– Unconditional Branch Instruction
– Conditional Branch Instruction
– Arithmetic
– Address Modify Instruction
Expanded Structure of IAS
 Expanded structure of IAS computer
• Set of registers (storage in CPU)
– Memory Buffer Register (MBR)
• Contains a word to be stored in memory or sent to
the I/O unit, or it is used to receive a word from
memory or from the I/O unit.
– Memory Address Register (MAR)
• Specifies the address in memory of the word to be
written from or read into the MBR.
– Instruction Register (IR)
• Contains the 8 bit opcode instruction being executed.
– Instruction Buffer Register (IBR)
• Employed to hold temporarily the right hand
instruction from a word in memory
– Program Counter (PC)
• Contains the address of the next instruction pair to be
 IAS Operation - AC MQ
Flowchart No Input/out
MARPC Is next instruction
in IBR?
MBRM[MAR] Arithmetic & Logic put
Circuits
IBRMBR<20..39> Equipme
IRMBR<0..7> nts
yes
MARMBR<8..19> MBR
MBRM[MAR]
ACMBR
IRIBR<0..7>
MARIBR<8..19> IBR PC

PCPC+1
Main
PCMAR
Memory
MBRM[MAR] IR
AC MBR MAR
Contr
ol
Circui
ts
 AC
AC= 7
3 MQ
MEMORY
1. LOAD M(X) 500, ADD M(X) 501
2. STOR M(X) 500, (Other Ins)
.....
500. 3
501. 4 500
LOAD
MBRM(X)= 501
4
3
ADD MBR
500
M(X)
(Other STOR
Ins) M(X)

PC 2
1
MAR 501
500
2
1
MBR LOAD
STOR
M(X)
M(X)
500,
500,
3 ADD
4 (Other
M(X)
Ins)
501
IR LOAD
STOR
ADD M(X)
M(X)
IBR ADD
(Other
M(X)Ins)
501
AC 7
3
501
AddIBR
M(X) PC = 2
PC←
Mar
MAR = PC
← 1

3
LOAD M(X) 500, ADD M(X) 501

4
STOR M(X) 500, (Other Ins)
IR MAR
MAR
MAR =500
= 12
MAR==500
501
add = 501
add =
add 500
add==12
Register transfer operation for addition
operation

1. LOAD M(X) 500, ADD M(X) 501

• Register transfer operations: (PC = 1)
– MAR ← PC
– MBR ← M[MAR]
– IBR ← MBR[20:39]
– IR ← MBR[0:7]
– MAR ← MBR[8:19]
– MBR ← M[MAR]
– AC ← MBR
– IR ← IBR[0:7]
– MAR ← IBR[8:19]
– MBR ← M[MAR]
– AC ← AC + MBR
Fetch / Execute Cycle
 AC
AC= 7
3 MQ
MEMORY
1. LOAD M(X) 500, ADD M(X) 501
2. STOR M(X) 500, (Other Ins)
.....
500. 3
501. 4 500
LOAD
MBRM(X)= 501
4
3
ADD MBR
500
M(X)
(Other STOR
Ins) M(X)

PC 2
1
MAR 501
500
2
1
MBR LOAD
STOR
M(X)
M(X)
500,
500,
3 ADD
4 (Other
M(X)
Ins)
501
IR LOAD
STOR
ADD M(X)
M(X)
IBR ADD
(Other
M(X)Ins)
501
AC 7
3
501
AddIBR
M(X) PC = 2
PC←
Mar
MAR = PC
← 1

3
LOAD M(X) 500, ADD M(X) 501

4
STOR M(X) 500, (Other Ins)
IR MAR
MAR
MAR =500
= 12
MAR==500
501
add = 501
add =
add 500
add==12
Instruction set: Collection of instructions that the CPU
can execute

What an Instruction set should specify?

Which Operation to perform (Opcode)

Where to find the operand or operands (CPU registers, main
memory or I/O port)
Where to put the result, if there is result
Where to find the next instruction
IAS Instruction set
IAS Instruction set Contd..
Von Neumann and Harvard
Architecture
Von Neumann Architecture
Harvard Architecture
 Von Neumann and Harvard
Architecture
Parameters Von Neumann Architecture Harvard Architecture

Definition The Von Neumann Architecture is an Harvard Architecture is a modern type of

ancient type of computer architecture computer architecture that follows the
that follows the concept of a stored- concept of the relay-based model by
program computer. Harvard Mark I.

Physical It uses one single physical address for It uses two separate physical addresses
Address accessing and storing both data and for storing and accessing both
instructions. instructions and data.
Buses (Signal One common signal path (bus) helps in It uses separate buses for the transfer of
Paths) the transfer of both instruction and both data and instructions.
data.
Number of It requires two clock cycles for It executes any instruction using only one
Cycles executing a single instruction. single cycle.

Cost It is comparatively cheaper in cost than It is comparatively more expensive than

Harvard Architecture. the Von Neumann Architecture.
 Von Neumann and Harvard
Architecture
Access to CPU The CPU is not able to read/write data The CPU can easily read/write data as
and access instructions at the same well as access the instructions at any
time. given time.
Uses This method comes to play in the case This architecture is best for signal
of small computers and personal processing as well as microcontrollers.
computers.
Requirement of Von Neumann Architecture requires This one requires more hardware. It is
Hardware lesser architecture. It is because it only because it requires separate sets of data
needs to reach one common memory. as well as address buses for individual
memory.

Usage of This architecture does not waste any This type of architecture can result in
Space space as data and instruction shares space wastage as the instruction memory
same memory. cannot utilize the leftover space in the
data memory.

Execution The speed of execution of the Von The overall speed of execution of Harvard
Speed Neumann Architecture is comparatively Architecture is comparatively faster. It is
slower. It is because it is not capable of because the processor, in this case, is
fetching the instructions and data both capable of fetching both instructions and
at the same time. data at the very same time.
Modified Harvard Architecture
RISC and CISC Architecture
 RISC
• RISC :- Reduced Instruction Set Computer Processor
• A microprocessor architecture with a simple collection
and highly customized set of instructions.

• It is built to minimize the instruction execution time by

optimizing and limiting the number of instructions.

• It means each instruction cycle requires only one clock

cycle, and each cycle contains three parameters: fetch,
decode and execute.

• RISC chips require several transistors, making it cheaper

to design and reduce the execution time for instruction.
RISC Architecture
 Features of RISC Processor

• One cycle execution time: For executing each instruction in a
compu ter, th e RI SC processors requ ire on e C PI (C lock per
instruction).

• Pipelining technique: The pipelining technique is used in the RISC

processors to execute multiple parts or stages of instructions to
perform more efficiently.

• A large number of registers: RISC processors are optimized with

multiple registers that can be used to store instruction and quickly
respond to the computer and minimize interaction with computer
memory.

• I t su p p or ts a simp le addressin g mode an d f ix ed len g th of

instruction for executing the pipeline.
• It uses LOAD and STORE instruction to access the memory
location.
• Simple and limited instruction reduces the execution time of a
process in a RISC.
 CISC
• CISC:-Complex Instruction Set Computer
• It has a large collection of complex instructions
that range from simple to very complex and
specialized in the assembly language level,
w h i c h ta k e s a l o n g ti m e to e xe c u te th e
instructions.
• CISC approaches reducing the number of
instruction on each program and ignoring the
number of cycles per instruction.
• CISC chips are relatively slower as compared
to RISC chips but use little instruction than
RISC.
 Features of CISC Processor
• The length of the code is short, so it requires very
little RAM.
• CISC or complex instructions may take longer than a
single clock cycle to execute the code.
• Less instruction is needed to write an application.
• I t p r o v i d e s e a si e r p r o g r a m m i ng i n a sse m b l y
language.
• Sup p o r t fo r c o m p le x d at a st r uc t ure and e asy
compilation of high-level languages.
• It is c omp osed of few er reg ist ers and more
addressing modes, typically 5 to 20.
• Instructions can be larger than a single word.
• It emphasizes the building of instruction on hardware
because it is faster to create than the software.
CISC Architecture
 RISC CISC

1. RISC stands for Reduced Instruction Set Computer. 1. CISC stands for Complex Instruction Set Computer.

2. RISC processors have simple instructions taking 2. CSIC processor has complex instructions that take up
about one clock cycle. The average clock cycle per multiple clocks for execution. The average clock cycle
instruction (CPI) is 1.5 per instruction (CPI) is in the range of 2 and 15.
3. Performance is optimized with more focus on 3. Performance is optimized with more focus on
software hardware.
4. It has no memory unit and uses separate hardware 4. It has a memory unit to implement complex
to implement instructions.. instructions.

5. It has a hard-wired unit of programming. 5. It has a microprogramming unit.

6. The instruction set is reduced i.e. it has only a few
6. The instruction set has a variety of different
instructions in the instruction set. Many of these
instructions that can be used for complex operations.
instructions are very primitive.
7. Complex addressing modes are synthesized using
7. CISC already supports complex addressing modes
the software.
8. Multiple register sets are present 8. Only has a single register set
9. RISC processors are highly pipelined 9. They are normally not pipelined or less pipelined
10. The complexity of RISC lies with the compiler that
10. The complexity lies in the microprogram
executes the program
11 Execution time is very less 11. Execution time is very high
12. Code expansion can be a problem 12. Code expansion is not a problem
13. The decoding of instructions is simple. 13. Decoding of instructions is complex
14. The most common RISC microprocessors are 14. Examples of CISC processors are the System/360,
Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power VAX, PDP-11, Motorola 68000 family, AMD, and Intel x86
Architecture, and SPARC. CPUs.
15. RISC architecture is used in high-end applications
15. CISC architecture is used in low-end applications
such as video processing, telecommunications, and
such as security systems, home automation, etc.
image processing.
 References
• W. Stallings, Computer organization and
architecture, Prentice-Hall,2000
• J. P. Hayes, Computer system
architecture, McGraw Hill