Memory Management

Dr. Raghunath Dey

School of Computer Engineering
KIIT Deemed to be University
Objectives

• To provide a detailed description of

various ways of organizing memory
hardware
• To discuss various memory-management
techniques, including paging and
segmentation
Background
• Program must be brought (from disk) into memory
and placed within a process for it to be run
• Main memory and registers are only storage CPU can
access directly
• Memory unit only sees a stream of addresses + read
requests, or address + data and write requests
• Register access in one CPU clock (or less)
• Main memory can take many cycles
• Cache sits between main memory and CPU registers
• Protection of memory required to ensure correct
operation
Base and Limit Registers
• A pair of base and limit registers define the logical
address space
• CPU must check every memory access generated in
user mode to be sure it is between base and limit for
that user
Hardware Address Protection
Address Binding

• Programs on disk, ready to be brought into memory to execute form

an input queue
– Without support, must be loaded into address 0000
• Further, addresses represented in different ways at different stages
of a program’s life
– Source code addresses usually symbolic
– Compiled code addresses bind to relocatable addresses
• i.e. “14 bytes from beginning of this module”
– Linker or loader will bind relocatable addresses to absolute
addresses
• i.e. 74014
Binding of Instructions and Data to
Memory
• Address binding of instructions and data to
memory addresses can happen at three
different stages
– Compile time: If memory location known a priori,
absolute code can be generated; must recompile
code if starting location changes
– Load time: Must generate relocatable code if
memory location is not known at compile time.
Binding delayed until load time.
– Execution time: Binding delayed until run time if
the process can be moved during its execution
from one memory segment to another
• Need hardware support for address maps (e.g., base
and limit registers)
Multistep Processing of a User
Program
Logical vs. Physical Address Space
• The concept of a logical address space that is bound
to a separate physical address space is central to
proper memory management
– Logical address – generated by the CPU; also referred to
as virtual address
– Physical address – address seen by the memory unit
• Logical Address Space is set of all logical addresses
generated by CPU in reference to a program.
• Physical Address is set of all physical addresses
mapped to the corresponding logical addresses.
Visibility.
• User can view the logical address of a program. User
can never view physical address of program.
Memory-Management Unit (MMU)

• Hardware device that at run time maps virtual to

physical address
• The relocation register is added to every address
generated by a user process at the time it is sent to
memory
– Base register now called relocation register
– MS-DOS on Intel 80x86 used 4 relocation registers
• The user program deals with logical addresses; it
never sees the real physical addresses
– Execution-time binding occurs when reference is made to
location in memory
– Logical address bound to physical addresses
• The MMU is usually located within the computer's
central processing unit (CPU), but sometimes
operates in a separate integrated chip (IC).
 Dynamic relocation using a
relocation register

n Routine is not loaded until

it is called
n Better memory-space
utilization; unused routine
is never loaded
n All routines kept on disk in
relocatable load format
n Useful when large
amounts of code are
needed to handle
infrequently occurring
cases
n No special support from
the operating system is
Swapping
• A process can be swapped temporarily out of memory
to a backing store, and then brought back into memory
for continued execution
– Total physical memory space of processes can exceed
physical memory
• Backing store – fast disk large enough to
accommodate copies of all memory images for all
users; must provide direct access to these memory
images
• Roll out, roll in – swapping variant used for priority-
based scheduling algorithms; lower-priority process is
swapped out so higher-priority process can be loaded
and executed
• Major part of swap time is transfer time; total transfer
time is directly proportional to the amount of memory
swapped
• System maintains a ready queue of ready-to-run
processes which have memory images on disk
• Does the swapped out process need to swap
back in to same physical addresses?
• Depends on address binding method
– Plus consider pending I/O to / from process
memory space
• Modified versions of swapping are found on
many systems (i.e., UNIX, Linux, and
Windows)
– Swapping normally disabled
– Started if more than threshold amount of memory
allocated
– Disabled again once memory demand reduced
below threshold
Schematic View of Swapping
Context Switch Time including
Swapping
• If next processes to be put on CPU is not in memory,
need to swap out a process and swap in target
process
• Context switch time can then be very high
• 100MB process swapping to hard disk with transfer
rate of 50MB/sec
– Swap out time of 2000 ms (mili second)
– Plus swap in of same sized process
– Total context switch swapping component time of 4000ms
(4 seconds)
• Can reduce if reduce size of memory swapped – by
knowing how much memory really being used
– System calls to inform OS of memory use via
request_memory() and release_memory()
• Standard swapping not used in modern
operating systems
– But modified version common
• Swap only when free memory extremely low
Memory Management Techniques
• Memory management Techniques:
• The Memory management Techniques can be classified into following
main categories:
• Contiguous memory management schemes
• Non-Contiguous memory management schemes
 Cont..
• Contiguous memory management schemes:
• In a Contiguous memory management scheme, each program occupies
a single contiguous block of storage locations, i.e., a set of memory
locations with consecutive addresses.
• Single contiguous memory management schemes:
• The Single contiguous memory management scheme is the simplest
memory management scheme used in the earliest generation of computer
systems.
• In this scheme, the main memory is divided into two contiguous areas
or partitions. The operating systems reside permanently in one partition,
generally at the lower memory, and the user process is loaded into the
other partition.
 The single Contiguous memory management scheme is inefficient as it
limits computers to execute only one program at a time resulting in
wastage in memory space and CPU time.
Cont..
• Diagram:

User
Process

Operating
System
Multiple-partition allocation
• Multiple-partition allocation
– Degree of multiprogramming limited by number of partitions
– Variable-partition sizes for efficiency (sized to a given process’ needs)
– Hole – block of available memory; holes of various size are scattered throughout
memory
– When a process arrives, it is allocated memory from a hole large enough to
accommodate it
– Process exiting frees its partition, adjacent free partitions combined
– Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
 Cont..
• Multiple Partitioning:
• The single Contiguous memory management scheme is inefficient
as it limits computers to execute only one program at a time
resulting in wastage in memory space and CPU time.
• The problem of inefficient CPU use can be overcome using
multiprogramming that allows more than one program to run
concurrently.
• To switch between two processes, the operating systems need to
load both processes into the main memory.
• The operating system needs to divide the available main memory
into multiple parts to load multiple processes into the main
memory. Thus multiple processes can reside in the main memory
simultaneously.
Cont..
• Fixed Partitioning
• The main memory is divided into several fixed-sized
partitions in a fixed partition memory management scheme or
static partitioning.
• These partitions can be of the same size or different sizes.
• Each partition can hold a single process.
• T h e n u m b e r o f p a r t i t i o n s d e t e r m i n e s t h e d e g re e o f
multiprogramming, i.e., the maximum number of processes
in memory.
• In this method, the operating system maintains a table that
indicates which parts of memory are available and which are
occupied by processes.
• In this scheme, there is contiguous allocation, so spanning is
not allowed.
Cont..
 Cont..
• CASE 1: Now, let us assume a process P1 with size, 2 MB has arrived
(Example of “Internal Fragmentation”).
• CASE 2: Now, let us assume a process P2 with size, 7 MB has arrived.
• CASE 3: Now, let us assume a process P3 with size, 7 MB, has arrived.
• CASE 4: Now, let us assume a process P4 with size, 14 MB, has arrived.
• CASE 5: Now, let us assume a process P5 with size, 5 MB, has arrived.
(Example of “External Fragmentation”).
• CASE 6: Suppose, P4 finished its execution and is removed from MM,
and now, let us assume a process P6 with size, >16 MB, say 20 MB has
arrived.
• CASE 7: Suppose at any particular instance of time, the main memory
consists of the processes P1, P2, P3, and P4. Now, another process P5
with size 5 MB has arrived.
Cont..
• Dynamic Partitioning/Variable
Partitioning:
• The dynamic partitioning was designed to overcome the
problems of a fixed partitioning scheme.
• In a dynamic partitioning scheme, each process occupies
only as much memory as they require when loaded for
processing.
• Requested processes are allocated memory until the entire
physical memory is exhausted or the remaining space is
insufficient to hold the requesting process.
• In this scheme the partitions used are of variable size, and
the number of partitions is not defined at the system
generation time.
 Cont..
CASE 1: P1 = 2 MB arrived
CASE 2: P2 = 4 MB arrived
CASE 3: P3 = 8 MB arrived
CASE 4: P4 = 4 MB arrived
CASE 5: P5 = 8 MB arrived
CASE 6: P2 and P4 removed. (“Hole”)
CASE 7: P6 = 8 MB arrived
Conclusion:
1. No Internal Fragmentation.
2. No limitation on the number of
processes i.e. degree of
multiprogramming (of-course
restricted to RAM size)
3. No limitation on process size
4. External Fragmentation still
exists.
Fixed Partitioning with variable size
• How to satisfy a request of size n from a list of free
holes?
– First-fit: Allocate the first hole that is big enough

– Best-fit: Allocate the smallest hole that is big

enough; must search entire list, unless ordered by
size
– Produces the smallest leftover hole

– Worst-fit: Allocate the largest hole; must also search

entire list
– Produces the largest leftover hole
• First-fit and best-fit better than worst-fit in terms of
speed and storage utilization
Example: Process needs: 16K
 Cont..
• Limitations of Fixed size partitioning/Static partitioning:
• 1. Internal Fragmentation.
• 2. External Fragmentation.
• 3. Limit in process size.
• 4. Limitation on degree of multiprogramming.

• When a process is allocated to a memory block, and if the process is

smaller than the amount of memory requested, a free space is created in
the given memory block. Due to this, the free space of the memory block
is unused, which causes internal fragmentation.

• External fragmentation happens when there’s a sufficient quantity of

area within the memory to satisfy the memory request of a method.
However, the process’s memory request cannot be fulfilled because the
memory offered is in a non-contiguous manner.
 Cont..
• Fragmentation:
• Fragmentation is defined as when the process is loaded and removed after
execution from memory, it creates a small free hole.
• These holes can not be assigned to new processes because holes are not
combined or do not fulfill the memory requirement of the process.
• To achieve a degree of multiprogramming, we must reduce the waste of
memory or fragmentation problems.
• Compaction:
• To remove external fragmentation in dynamic partitioning, we use a method
known as compaction.
• Compaction is a technique to collect all the free memory present in form of
fragments into one large chunk of free memory, which can be used to run other
processes.
• It does that by moving all the processes towards one end of the memory and all
the available free space towards the other end of the memory so that it becomes
contiguous.
 Cont..
• After compaction, all the occupied space has been moved up and the free space
at the bottom.
• This makes the space contiguous and removes external fragmentation.
• Processes with large memory requirements can be now loaded into the main
memory.
• Advantages of Compaction
• Reduces external fragmentation.
• Make memory usage efficient.
• Memory becomes contiguous.
• Since memory becomes contiguous more processes can be loaded to memory.
• Disadvantages of Compaction
• System efficiency reduces.
• A huge amount of time is wasted in performing compaction.
• CPU sits idle for a long time.
Difference B/W Internal and External
Fragmentation
Fragmentation
• Fragmentation is an unwanted problem in the
operating system in which the processes are
loaded and unloaded from memory, and free
memory space is fragmented. Processes can't be
assigned to memory blocks due to their small size,
and the memory blocks stay unused.
– External Fragmentation – total memory space exists
to satisfy a request, but it is not contiguous
– Internal Fragmentation – allocated memory may be
slightly larger than requested memory; this size
difference is memory internal to a partition, but not
being used
• First fit analysis reveals that given N blocks
allocated, 0.5 N blocks lost to fragmentation
– -> 50-percent rule
• Reduce external fragmentation by
compaction
– Shuffle memory contents to place all free
memory together in one large block
– Compaction is possible only if relocation is
dynamic, and is done at execution time
Segmentation

• Memory-management scheme that supports user

view of memory
• A program is a collection of segments
– A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
User’s View of a Program
Logical View of Segmentation

4
1

3 2
4

user space physical memory space

Segmentation Architecture

• Logical address consists of a two tuple:

<segment-number, offset>,
• Segment table – maps two-dimensional physical
addresses; each table entry has:
– base – contains the starting physical address where
the segments reside in memory
– limit – specifies the length of the segment
• Segment-table base register (STBR) points to
the segment table’s location in memory
• Segment-table length register (STLR) indicates
number of segments used by a program;
segment number s is legal if s < STLR
• Protection
– With each entry in segment table associate:
• validation bit = 0  illegal segment
• read/write/execute privileges
• Protection bits associated with segments;
code sharing occurs at segment level
• Since segments vary in length, memory
allocation is a dynamic storage-allocation
problem
• A segmentation example is shown in the
following diagram
Segmentation Hardware
Advantages of Segmentation
• No Internal fragmentation.
• As a complete module is loaded all at once, segmentation improves
CPU utilization.
• The user’s perception of physical memory is quite similar to
segmentation. Users can divide user programs into modules via
segmentation. These modules are nothing more than the separate
processes’ codes.
• Segmentation is a method that can be used to segregate data from
security operations.
• Flexibility: Segmentation provides a higher degree of flexibility.
Segments can be of variable size, and processes can be designed
to have multiple segments, allowing for more fine-grained memory
allocation.
• Sharing: Segmentation allows for sharing of memory segments
between processes. This can be useful for inter-process
communication or for sharing code libraries.
• Protection: Segmentation provides a level of protection between
segments, preventing one process from accessing or modifying
another process’s memory segment. This can help increase the
security and stability of the system.
Disadvantage of Segmentation

• As processes are loaded and removed

from the memory, the free memory space
is broken into little pieces, causing
External fragmentation.
• Overhead is associated with keeping a
segment table for each activity.
• Due to the need for two memory accesses,
one for the segment table and the other
for main memory, access time to retrieve
the instruction increases.
Paging
• Physical address space of a process can be noncontiguous; process is
allocated physical memory whenever the latter is available
– Avoids external fragmentation
– Avoids problem of varying sized memory chunks
• Divide physical memory into fixed-sized blocks called frames
– Size is power of 2
• Divide logical memory into blocks of same size called pages
• Keep track of all free frames
• To run a program of size N pages, need to find N free frames and load
program
• Set up a page table to translate logical to physical addresses
• Backing store likewise split into pages
• Still have Internal fragmentation
Address Translation Scheme
• Address generated by CPU is divided into:
– Page number (p) – used as an index into a page table which contains
base address of each page in physical memory
– Page offset (d) – combined with base address to define the physical
memory address that is sent to the memory unit

– For given logical address space 2m and page size 2n

 5

3 2

§ Physical memory=32 bytes

§ (=25)
§ Assume that size of a page is 4 bytes (=22)
§ 25/22=23 (5-2= 3=> 23=8 pages)
§ A page size is 4 bytes (22) needs 2 bits to represent 4 bytes
§ (00, 01,10,11).
§ 8 pages can be represented in 3 bits
§ (000,001,010,011,100,101,110,111).
Paging Hardware
Paging Model of Logical and
Physical Memory
Paging Example
0
0

1 1

2 2

3
3

n=2 and m=4 32-byte memory and 4-byte pages

Paging (Cont.)
• Calculating internal fragmentation
– Page size = 2,048 bytes
– Process size = 72,766 bytes
– 35 pages + 1,086 bytes
– Internal fragmentation of 2,048 - 1,086 = 962 bytes
– Worst case fragmentation = 1 frame – 1 byte
– So small frame sizes desirable?
– But each page table entry takes memory to track
– Page sizes growing over time
• Solaris supports two page sizes – 8 KB and 4 MB
• Process view and physical memory now very different
Free Frames

Before allocation After allocation

Implementation of Page Table
• Page table is kept in main memory
• Page-table base register (PTBR) points to the page table
• Page-table length register (PTLR) indicates size of the page table
• In this scheme every data/instruction access requires two memory
accesses
– One for the page table and one for the data / instruction
• The two memory access problem can be solved by the use of a
special fast-lookup hardware cache called associative memory or
translation look-aside buffers (TLBs)
Implementation of Page Table (Cont.)
• Some TLBs store address-space identifiers (ASIDs) in each TLB entry –
uniquely identifies each process to provide address-space protection for
that process
– Otherwise need to flush at every context switch
• TLBs typically small (64 to 1,024 entries)
• On a TLB miss, value is loaded into the TLB for faster access next time
– Replacement policies must be considered
– Some entries can be wired down for permanent fast access
Paging Hardware With TLB
Effective Access Time
• The percentage of times that a particular page number is found in the TLB
is called the hit ratio. An 80-percent hit ratio means that we find the desired
page number in the TLB 80 percent of the time.
• If it takes 20 nanoseconds to search the TLB, and 100 nanoseconds to
access memory, then a mapped memory access takes 120 nanoseconds
when the page number is in the TLB.
• If we fail to find the page number in the TLB (20 nanoseconds), then we
must first access memory for the page table and frame number (100
nanoseconds), and then access the desired byte in memory (100
nanoseconds), for a total of 220 nanoseconds.
• To find the effective memory-access time, we must weigh each case by its
probability:
• EAT(effective access time)= P x hit memory time + (1-P) x miss memory
time. effective access time = 0.80 x 120 + 0.20 x 220 = 140 nanoseconds.
• Q1. For a 98-percent hit ratio, we have

• EAT(effective access time)= P x hit memory time + (1-P) x miss

memory time. Where: P is Hit ratio. effective access time = 0.98 x
120 + 0.02 x 220 = 122 nanoseconds.

• Q2. What will be the EAT if hit ratio is 70%, time for TLB is 30ns
and access to main memory is 90ns?

• Sol. P = 70% = 70/100 = 0.7 Hit memory time = 30ns + 90ns =

120ns
– Miss memory time = 30ns + 90ns + 90ns = 210ns Therefore, EAT = P x
Hit + (1-P) x Miss = 0.7 x 120 + 0.3 x 210 =84.0 + 63.0 =147 ns
Shared Pages Example
Memory Protection
• Memory protection implemented by associating protection bit with each
frame to indicate if read-only or read-write access is allowed
– Can also add more bits to indicate page execute-only, and so on
• Valid-invalid bit attached to each entry in the page table:
– “valid” indicates that the associated page is in the process’ logical
address space, and is thus a legal page
– “invalid” indicates that the page is not in the process’ logical
address space
• Any violations result in a trap to the kernel
Valid (v) or Invalid (i) Bit In A Page
Table
Hierarchical Page Tables

• Break up the logical address space into

multiple page tables
• A simple technique is a two-level page
table
• We then page the page table
Two-Level Page-Table Scheme
Two-Level Paging Example

• A logical address (on 32-bit machine with 1K page size) is divided into:
– a page number consisting of 22 bits
– a page offset consisting of 10 bits
• Since the page table is paged, the page number is further divided into:
– a 12-bit page number
– a 10-bit page offset
• Thus, a logical address is as follows:

• where p1 is an index into the outer page table, and p2 is the displacement
within the page of the inner page table
• Known as forward-mapped page table
Address-Translation Scheme
64-bit Logical Address Space
A system uses a 32-bit virtual address with a 4 KB page
size and a two-level paging scheme. The first-level and
second-level page tables each contain 1024 entries. How
many bits are used for the page offset, first-level index, and
second-level index?
Inverted Page Table

• Rather than each process having a page table and keeping track of
all possible logical pages, track all physical pages
• One entry for each real page of memory
• Entry consists of the virtual address of the page stored in that real
memory location, with information about the process that owns that
page
• Decreases memory needed to store each page table, but
increases time needed to search the table when a page reference
occurs
– TLB can accelerate access
– One mapping of a virtual address to the shared physical address
• Only one page table in the system (Global Page Table)
Inverted Page Table
Inverted Page Table Architecture
End..