[Link] [Link] the diagram of microprocessor based system.

Answer:

A microprocessor is a central processing unit (CPU) that serves as the brain of a computer or
electronic device. It is an integrated circuit that performs arithmetic and logic operations, controls
input and output devices, and executes instructions from memory.

Diagram of microprocessor based system.

[Link] between microprocessor and microcontroller

d) Difference between CALL and RET instruction.

[Link] the architecture of 8086 microprocessor and describe eu section

The 8086 microprocessor architecture is divided into two main sections:

1. Bus Interface Unit (BIU)

2. Execution Unit (EU)

Here is the diagram of the 8086 microprocessor architecture:

Execution Unit (EU) Description

The Execution Unit (EU) is responsible for decoding and executing instructions. It includes the
following components:

• Control Unit: Directs the operations of the internal processor.

• ALU (Arithmetic and Logic Unit): Performs arithmetic and logical operations.

• General Purpose Registers: Includes AX, BX, CX, DX which are used for various operations.

• Segment Registers: Includes CS, DS, SS, ES which are used to address memory segments.

• Pointer and Index Registers: Includes SP, BP, SI, DI which are used for indexed addressing.

• Flag Register: Indicates the status of the processor and results of operations.

• Instruction Decoder: Decodes the fetched instructions so that they can be executed by the
ALU.

b) Write the functionalities of the following pins of 8086 microprocessor:

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ii. NMI

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iv. BHE

v. DEN
 1. ALE (Address Latch Enable):

o Enables latching of the lower byte of the address (AD0-AD7) during memory access.

2. NMI (Non-Maskable Interrupt):

o High-priority interrupt that cannot be disabled by software, used for critical events.

3. INTR (Interrupt Request):

o Maskable interrupt pin for requesting processor attention from external devices.

4. BHE (Bus High Enable):

o Selects the upper byte (D8-D15) of the data bus during 16-bit memory transfers.

5. DEN (Data Enable):

o Enables data transceivers during read or write operations for data transfer.

c) Derive the Contents of the Flag Register of 8086 Microprocessor

i. CMP AL, FFh (Assume AL initially contains FFh)

The CMP instruction compares the contents of the AL register with the immediate value 0xFF by
performing the subtraction AL - 0xFF without storing the result, but updating the flags.

• Initial Value of AL: FFh

• Operation: FFh - FFh = 00h

Flags after CMP AL, FFh:

• Carry Flag (CF): 0 (No borrow)

• Parity Flag (PF): 1 (0x00 has an even number of 1s)

• Zero Flag (ZF): 1 (Result is zero)

• Overflow Flag (OF): 0 (No overflow)

ii. INC AL (Assume AL initially contains FFh)

The INC instruction increments the value in the AL register by 1.

• Initial Value of AL: FFh

• Operation: FFh + 1 = 100h (Which is 00h with a carry)

Flags after INC AL:

• Carry Flag (CF): Unchanged (Previous state unknown, assume it to be 0 for this operation)

• Parity Flag (PF): 1 (0x00 has an even number of 1s)

• Zero Flag (ZF): 1 (Result is zero)

• Overflow Flag (OF): 1 (Signed overflow from positive to negative)

3.a) Write your opinion: How can the 8259 PIC are extended to handle 64 interrupt requests?

The 8259 Programmable Interrupt Controller (PIC) is designed to handle up to 8 interrupt requests.
To extend this capability to handle 64 interrupt requests, multiple 8259 PICs can be cascaded.
Cascading involves connecting multiple 8259 PICs in a master-slave configuration. Here's how it
works:

1. Master-Slave Configuration: One 8259 acts as the master and the others act as slaves. The
master PIC can handle up to 8 slaves.

2. Interrupt Requests (IR): The master PIC’s interrupt request lines (IR0-IR7) can be connected
to the interrupt outputs of the slave PICs.

3. Slave PICs: Each slave PIC handles 8 interrupt lines, which means that with 8 slaves, a total
of 64 interrupts (8*8) can be managed.

Connection Details:

• The master PIC is connected to the CPU.

• The interrupt request lines of the master PIC (e.g., IR0-IR7) are connected to the interrupt
outputs of the slave PICs.

• Each slave PIC handles 8 interrupt inputs.

• When a slave PIC receives an interrupt, it sends an interrupt request to the master PIC on
one of the IR lines.

• The master PIC identifies which slave sent the request and processes the interrupt
accordingly.

b) The Need for the Programmable Interrupt Controller (8259A)

The 8259A Programmable Interrupt Controller (PIC) is necessary for the following reasons:

1. Handling Multiple Interrupts: It allows the CPU to handle multiple interrupt sources
efficiently by prioritizing and managing multiple interrupt requests.

2. Interrupt Priority Management: It provides a mechanism to prioritize interrupts so that

critical tasks can interrupt less critical ones.

3. Interrupt Vectoring: It generates the appropriate interrupt vector for the CPU, simplifying
the software required to handle interrupts.

4. Masking Interrupts: It allows selective enabling and disabling of interrupt requests,

providing flexibility in handling interrupts.

1. Interrupt Nesting: It supports nested interrupts, where higher priority interrupts can
interrupt the processing of lower priority ones.
c) Direct Memory Access (DMA)

Direct Memory Access (DMA) is the technique that provides direct access to the memory while the
microprocessor is temporarily disabled. Here’s how it works:

• DMA Controller: A separate DMA controller takes over the bus from the CPU to manage
memory access directly.

• Data Transfer: The DMA controller directly transfers data between I/O devices and memory
without CPU intervention.

• Bus Control: The CPU relinquishes control of the system bus to the DMA controller during
data transfer.

• Interrupt: After the transfer is complete, the DMA controller generates an interrupt to notify
the CPU that the operation is finished.

Steps in DMA Operation:

1. Initiation: The CPU initializes the DMA controller with the memory address, the I/O device
address, and the number of bytes to transfer.

2. Bus Request: The DMA controller sends a request to the CPU to take control of the bus.

3. Bus Grant: The CPU grants control of the bus to the DMA controller.

4. Data Transfer: The DMA controller transfers data directly between the I/O device and
memory.

5. Completion: The DMA controller releases the bus and sends an interrupt to the CPU
indicating completion of the transfer.

d) Single-Core and Multi-Core CPU

Single-Core CPU:

Definition: A single-core CPU has one processing unit (core) that executes instructions from
a single thread of a program at any given time.

Multi-Core CPU:

Definition: A multi-core CPU has multiple processing units (cores) on a single chip, each
capable of executing its own thread simultaneously.

Key Differences:

• Processing Units: Single-core has one processing unit; multi-core has multiple processing
units.

• Parallelism: Single-core executes one thread at a time; multi-core executes multiple threads
concurrently.

• Performance: Multi-core CPUs offer better performance for multitasking and parallel
processing tasks compared to single-core CPUs.
4.a poreeee

b. b) Addressing Mode in 8086

Addressing modes in the 8086 microprocessor specify how the operand of an instruction is accessed.
Different addressing modes provide flexibility and efficiency in accessing data.

Four Addressing Modes of 8086 with Examples:

1. Immediate Addressing Mode:

• Description: The operand is specified explicitly in the instruction.

• Example: MOV AX, 1234H

• This instruction moves the immediate value 1234H into the AX register.

2. Register Addressing Mode:

• Description: The operand is in a register.

• Example: MOV BX, AX

• This instruction copies the contents of the AX register into the BX register.

3. Direct Addressing Mode:

• Description: The effective address of the operand is given directly in the instruction.

• Example: MOV AX, [1234H]

• This instruction moves the contents of memory location 1234H into the AX
register.

4. Register Indirect Addressing Mode:

• Description: The effective address of the operand is in a register.

• Example: MOV AX, [BX]

• This instruction moves the contents of the memory location pointed to by

the BX register into the AX register.

Explanation of Commands

i. JE/JZ (Jump if Equal / Jump if Zero)

• Description: JE (Jump if Equal) and JZ (Jump if Zero) are conditional jump instructions that
cause a jump to a specified label if the Zero Flag (ZF) is set.

• Example:

CMP AX, BX

JE Label

• If AX is equal to BX, the ZF is set, and the execution jumps to the specified label.
ii. JAE (Jump if Above or Equal)

• Description: JAE (Jump if Above or Equal) is a conditional jump that occurs if the Carry Flag
(CF) is clear, indicating that the first operand is greater than or equal to the second operand.

• Example:

CMP AX, BX

JAE Label

• If AX is greater than or equal to BX, the CF is clear, and the execution jumps to the specified
label.

iii. JNAE (Jump if Not Above or Equal)

• Description: JNAE (Jump if Not Above or Equal) is a conditional jump that occurs if the Carry
Flag (CF) is set, indicating that the first operand is less than the second operand. This is also
known as JB (Jump if Below).

• Example:

CMP AX, BX

JNAE Label

• If AX is less than BX, the CF is set, and the execution jumps to the specified label.

iv. CMP (Compare)

• Description: CMP is used to compare two operands by subtracting the second operand from
the first operand and setting the flags accordingly without storing the result. It affects the
Zero Flag (ZF), Sign Flag (SF), Overflow Flag (OF), and Carry Flag (CF).

• Example:

CMP AX, BX

• This instruction compares AX with BX. If AX is equal to BX, ZF is set; if AX is greater than BX,
CF is cleared; if AX is less than BX, CF is set.
5.a) Differentiate between the real address and protected virtual address mode (PVAM) of 80286.

b) Comparison Between 8086, 80386, and Pentium Processor

[Link] does 8086 access odd and even memory bank?explain with block diagram

The memory chip is equally divided into two parts(banks). One of the banks contains even addresses
called Even bank and the other contains odd addresses called Odd bank. Even bank always gives
lower byte So Even bank is also called Lower bank(LB) and Odd bank is also called Higher bank(HB).

Purpose of memory banking:

As the 16-bit data is stored in 2 locations, lower byte in lower address and upper byte in next
consecutive address location.

How does banking work?

There are totally 20 address lines in 8086, that can access the
locations. Each location is decided by these 20 address lines ( A0 , A1
…A19 ).

If observed, for every consecutive location starting from even

location, there is only change in address ( A0 is only different ).

For Eg: Locations 0H and 1H are consecutive and have the same
address except A0.

Locations 3H and 4H are consecutive but their addresses don’t have

that similarity.

If A0 address line is discarded, 8086 sends a 19-bit address, there are two locations, one location in
higher bank and other location in lower with the same address, in this way 8086 can fetch 16 bit
data in one cycle. But if A0 is always discarded, 8086 can only perform 16-bit operations, and cannot
perform 8-bit operations.

So we need that

• 8086 can be able to select lower bank only for 8-bit operations.
• 8086 can be able to select higher bank only for 8-bit operations.
• 8086 can be able to select both banks at single time for 16-bit operations.
Then BHE, comes into picture. It stands for bus high enable or bank high enable, and it is
pronounced as BHE bar.

BHE bar is connected to the active low of the higher bank and A0 is connected to the active low of
lower bank.

• Whenever A0 = 0, lower bank is selected

• And if A0 = 1, lower bank is not selected

• A0 has nothing to do with higher bank

• Whenever BHE = 0, higher bank is selected

• And if BHE = 1, higher bank is not selected

• BHE has nothing to do with lower bank

BHE bar and A0 are decided by the processor according to instructions given.

• If it is an 8-bit instruction given an odd address then BHE=0 and A0 = 1.

• If it is a 16-bit instruction then BHE = 0 , A0 = 0
If it is a pentium processor, which is a 64-bit processor. Then there will be 8 memory banks.
Easy to understand:

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a) Define Paging and How Paging Works

Paging is a memory management scheme that eliminates the need for contiguous allocation of
physical memory and thereby minimizes fragmentation. It allows the physical address space of a
process to be non-contiguous.

How paging works

In a memory management system that takes advantage of paging, the OS reads data from
secondary storage in blocks called pages, all of which have identical size. The physical region of
memory containing a single page is called a frame. When paging is used, a frame does not have
to comprise a single physically contiguous region in secondary storage. This approach offers an
advantage over earlier memory management methods, because it facilitates more efficient and
faster use of storage.

b) Features of the 80486 Microprocessor

Here’s a concise summary of the Intel 80486 processor features in point form:

• 32-bit Architecture: Supports 8-bit, 16-bit, and 32-bit data types.

• Cache: 8 KB unified level 1 cache for code and data; advanced versions may have 16 KB.

• Clock Speeds: Available in 25 MHz, 33 MHz, 50 MHz, and 100 MHz (DX-4).

• Instruction Execution: Reduced execution time; load, store, and arithmetic instructions
execute in one cycle if data is cached.

• Bus Transfers: Faster bus transfer capabilities.

• Instruction Sets: Retains complex instruction sets from the 80386 with enhanced pipelining.

• Integrated FPU: Floating-point unit integrated to eliminate communication delays.

• Pipelining: Five-stage pipeline, with two stages for decoding and three for execution.

• Clock Technology: Supports clock-doubling and clock-tripling; operates at higher internal

speeds on existing motherboards.

• Power Management: Standard features include power management and System

Management Mode (SMM).

c) 8255A Control Word and Control Register with Necessary Diagram

The control word is an 8-bit value, where each bit has a specific function. The format is as
follows:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

D4 D3 D2 D1 C0 C1 C2 C3

Control Word Bit Description

• D0-D3: Defines the mode of operation for Port A and Port B.

• D4: Specifies if Port A is in mode 0 (0) or mode 1/2 (1).

• D5: Specifies if Port B is in mode 0 (0) or mode 1 (1).

• D6: Control for Port C, determines the mode (0: standard; 1: alternate).

• D7: Designates the control word itself (0 for control word, 1 for a specific function).

Control Word Configuration Example

1. Port A in mode 0 (input): 0

2. Port B in mode 1 (output): 1

3. Port C in standard mode: 0

Functional Diagram

Here's a simple functional diagram of the 8255A PPI:

Description of Ports

• Port A: Can be configured as input/output. Used for data transfer.

• Port B: Similar to Port A, configurable as input/output.

• Port C: Often used for control signals and can be further divided for specific use cases.
7.a. Basic Features of PLC and Its Applications

Plc feature:
• They are rugged and designed to withstand vibration, temperature, humidity and noise
• The interfacing for inputs and outputs is inside the controller.
• They are easily programmed and have an easily understood programming language.
• Programming is primarily concerned with logic and switching operation.

b) Calculating the Physical and Logical Address of the Code Segment Register
Given:
• CS (Code Segment register) = 1111H
• IP (Instruction Pointer) = 6721H

1. Logical Address Calculation

The logical address is a combination of the Code Segment (CS) and Instruction Pointer (IP). The
logical address is typically represented as:
Logical Address=CS (segment):IP (offset)
Given:
• CS = 1111H (in hexadecimal)
• IP = 6721H (in hexadecimal)
2. Physical Address Calculation
The physical address is calculated using the formula:
Physical Address=(CS×16)+IP
The CS is shifted left by 4 bits (or multiplied by 16) to account for the segment offset.
Calculations
Step 1: Convert CS and IP to Decimal

Step 2: Calculate the Physical Address

Step 3: Convert Physical Address Back to Hexadecimal

c) Define ladder diagram (Id) with ladder symbols/elements.

A ladder diagram is usually called a “Ladder Logic”, this represents a program by a graphical
diagram.

d) Differences Between ARM and Intel Processors:

Feature ARM Processor Intel Processor

Architecture RISC (Reduced Instruction Set) CISC (Complex Instruction
Set)
Instruction Set Smaller set, simpler Larger set, more complex
Power Typically more efficient Can be less efficient
Efficiency
Cost Generally lower cost Can be higher cost
Applications Mobile devices, embedded Personal computers, servers
systems