Simplifying Power Conversion in

High-Voltage Systems

Sheng-yang Yu
System Manager
Power Design Services
There are a lot of challenges to delivering efficient
power conversion in high-voltage applications. However,
component, topology and system-level innovations can
significantly increase the high-voltage power-conversion
system’s efficiency and density, while simplifying designs.

improve the efficiency and power density of power

At a glance supplies. At high voltages, these challenges become
more prominent.
This white paper examines the challenges of efficient
high-voltage power conversion and provides examples of Delivering efficient power conversion in high-voltage
component, topology and system-level innovations that systems requires an in-depth knowledge of high-
help simplify power-supply designs in automotive and voltage components, electrical and magnetic circuit
industrial applications. modeling techniques, an understanding of insulation
requirements for functional or safety isolation, expertise
in electromagnetic compatibility, power-converter control

1
Optimizing wide-bandgap FET
performance with component techniques and more.
innovations Simplifying high-voltage power design is a challenging
Wide band-gap field-effect transistors (FETs)
task, but not an impossible one.
offer a higher-efficiency alternative to metal-oxide
semiconductor field-effect transistors (MOSFETs)
but require specialized companion devices such
Why high voltage?
as isolated gate drivers and digital controllers for As the worldwide electrification trend continues to gain
optimum performance. momentum, efficient energy transfer at higher power
levels becomes an important consideration in today’s

2
Maximizing power density with
topology innovations power electronic systems. Resistive loss (I2R) is the
Selecting the right topology can greatly influence central factor limiting how much power a power supply
the power density and efficiency of a high- can deliver. To improve system efficiency, increasing the
voltage power design. voltages used to transmit and deliver power reduces
the required current for the same power level and helps

3
Achieving extreme efficiency targets
minimize losses through heat.
with system-level innovation
System architecture innovations and control A few examples of high-voltage systems widely applied
system innovations can help designers achieve in today’s power networks include residential AC
higher efficiency and power density.
distribution power systems, telecommunication and
server power systems, DC microgrids in renewable
Power designers have their hands full. Not only do they energy systems, energy storage systems, and electric
need to keep up with constant increases in power levels, vehicle (EV) onboard and offboard chargers. As
they also need to find creative ways to continuously an example, EV batteries are currently 400 V but

Simplifying Power Conversion in High-Voltage Systems 2 November 2023

increasingly trending toward 800 V in order to enable In addition, almost all other parasitics including gate
more instantaneous power transfer to the traction charge (Qg) and output capacitance (Coss) are much
inverter for better acceleration performance. lower in wide band-gap FETs than silicon MOSFETs,
leading to much faster switching speeds: an over 150-
Although operating under a higher voltage brings
V/ns slew rate compared to a superjunction silicon
system efficiency benefits for power conversion, proper
MOSFET’s less than 80-V/ns slew rate. With faster
galvanic isolation and insulation are essential to
switching speeds, the time it takes for power switches
allow a safe human interface. Moreover, a closed-
to turn on or off is shorter, and switching losses are
loop system generally requires signal communication
reduced.
across the isolation boundaries. Add to this topology
selection, magnetic circuit design, electromagnetic
Selecting the right gate drivers
interference considerations, operating modes, thermal
Because of their electrical properties and the
management, and layout and control optimizations,
performance they enable, switching to wide band-
and you begin to understand some of the significant
gap technologies requires a thoughtful approach and
design challenges when working with high-voltage
careful companion component selection, presenting a
systems. Overall, innovations from three key areas
completely different set of challenges than designing with
– component innovations, topology innovations and
silicon. To further minimize switching losses, wide band-
system-level innovations – will increase high-voltage
gap FETs need an appropriate gate driver capable of
power-conversion system's efficiency and density, while
rapidly charging and discharging the gate capacitance,
simplifying designs.
since traditional silicon MOSFET gate drivers may not
Optimizing wide-bandgap FET performance offer proper voltage regulation or be able to handle the
with component innovations high common-mode voltage transient in a wide band-
Wide-bandgap FETs such as silicon carbide (SiC) gap design.
MOSFETs or gallium nitride (GaN) FETs offer a higher- As shown in Figure 2, when a switching event occurs,
efficiency alternative to silicon MOSFETs. Wide band-gap the voltage change on the switching node will generate
FETs have very low or even not reverse recovered charge a current flow through the parasitic capacitance of the
(Qrr), as well as lower on-resistance under the same driver. If the driver does not have enough common-mode
voltage levels as silicon MOSFETs, shown in Figure 1. transient immunity (CMTI), the common-mode current
could cause a gate-driver malfunction, as shown in
Figure 3.

Figure 1. Theoretical on-resistance vs. blocking voltage.

Simplifying Power Conversion in High-Voltage Systems 3 November 2023

 VCC VDD

VDC+
the connection copper. The total inductance on the
CByp CByp

ISOLATION BARRIER
Q1
driving loop will slow the GaN FET VDS transition,
IN
therefore limiting the switching losses that the GaN FET
OUT

GND
can reduce. This is why a TI GaN FET such as the
LMG3526R030 (see Figure 5) integrates a gate driver
into the same package. With the gate driver integrated,
- VCM +
there will be no PCB inductance (Lg_pcb and Ls_pcb). Also,
Q2 the Kelvin source connection is made for the gate-drive
loop (minimizing Lcs); therefore, the TI GaN FET can
switch at a high transient voltage, which will minimize
dV/dt
(V/ns)

VDC-

switching losses.
Figure 2. Common-mode current caused by a switching event. Drain

Driver GaN

Ldrv_Vdd Ld

Ldrv_out Lg_PCB Lg_GaN

In
1 2 3

⑥ Ldrv_gnd Lcs 4
Figure 3. Gate-driver CMTI failure example.
Ls_PCB

To address gate-driver challenges and CMTI concerns, 5

engineers can use new gate drivers with a Miller clamp,
Figure 4. A GaN FET with a discrete gate driver and parasitic
a high CMTI rating and adjustable slew-rate features inductance on the loop.
to avoid shoot-through or a gate-driver malfunction.
TI’s UCC5880-Q1 reinforced isolated gate driver has as DRAIN

much as 20 A of real-time variable gate-drive strength, Slew Direct-Drive

Rate GaN
SOURCE
a feature that enables you to increase power density RDRV

and reduce system design complexity and cost while IN

achieving your safety and performance goals. TI’s 300- VDD

VNEG
kW DC/AC High-Power, High-Performance Automotive
LDO, OCP, SCP, Current
SiC Traction Inverter Reference Design demonstrates LDO5V BB OTP, UVLO

how to balance efficiency and the challenges discussed TEMP

here by adjusting driving speeds under different load

FAULT
conditions.
OC
Faster switching means lower switching losses, but it
can also lead to unwanted voltage ringing and common- SOURCE

mode noise issues. Figure 4 shows a GaN FET with Figure 5. Simplified LMG3526R030 block diagram.
a discrete gate driver. There is not only parasitic
inductance of the two devices themselves, but also
the printed circuit board (PCB) trace inductance of

Simplifying Power Conversion in High-Voltage Systems 4 November 2023

Selecting the right controllers
Another real-time control challenge comes with the
In today’s high-voltage systems, magnetic components need for unique fault protection in a three-level inverter
occupy a large portion of the overall power-conversion topology. Instead of immediately switching all of the
stage. To reduce the size of magnetic components, you FETs off simultaneously in a two-level inverter, for
must increase the operational frequency. What follows a three-level inverter you must maintain the correct
is a need for dedicated digital control to manage the switch-off sequence in order to avoid damaging the
diverse high-performance requirements of high-voltage FETs. In the past, some designers have used external
systems. These controllers need to operate in real hardware circuits such as a field-programmable gate
time, accurately measuring system parameters (such array (FPGA) or complex programmable logic device
as voltage, current and temperature); applying control (CPLD) to achieve this level of protection, but these
algorithms to calculate the output commands; and circuits increase system costs and development efforts.
supporting the high frequencies needed to improve
To solve this problem, the C2000 configurable logic block
power density. The key to real-time control is to minimize
provides a mechanism for creating custom logic inside
the time between sensing, processing and control
the chip through software, offering a simpler option to
functions. Better real-time signal-chain performance
replace the functionality achieved by an external FPGA or
results in a faster transient response, more stable and
CPLD, and helping lower system costs and development
precise power conversion, and higher power density.
effort.
One challenge in real-time control is limiting cycling,
Wide band-gap devices can help greatly increase
which refers to the inability of the pulse-width
efficiency and power density – on paper. Without other
modulation (PWM) output to physically converge on the
component innovations such as the isolated gate driver
mathematical solution to the control law. This causes
and digital controller, you won’t be able to fully realize
the PWM output to oscillate around the true solution,
efficiency improvements in your designs.
resulting in instability in the control system. High-
resolution PWM (HRPWM) modules on microcontrollers
Maximizing power density with topology
(MCUs) such as TI’s C2000™ real-time MCUs have the innovations
ability to modulate the PWM edge in 150-ps increments.
In addition to component-level innovations, topology
This represents a sixtyfold improvement over traditional
innovations can help you simplify power conversion in
PWM creation techniques based off of the system clock
high-voltage systems. The AC/DC rectifier is a great
rate (see Figure 6) and can realize a higher order of
example of how wide band-gap technologies can elevate
accuracy in PWM edge placement. A waveform’s period,
well-known topologies to improve power density and
phase relationship to its complement, and deadband
reduce design weight. Historically, engineers used a
insertion time can all help realize this high-resolution
bridge diode rectifier with a capacitor to rectify the AC
technology.
voltage into the DC voltage, as shown in Figure 7.

VAC Load

Figure 6. HRPWM capability vs. traditional PWM generation

Figure 7. A full-bridge rectifier.
methods.

Simplifying Power Conversion in High-Voltage Systems 5 November 2023

The power factor of such a rectifier is generally lower
than 0.5, depending on the total impedance of output HFFET_HS LFFET_HS

capacitor and load. This is not energy-efficient, as such

a design generates too much unused power (reactive Load
VAC
power).

To solve the low-power-factor issue, engineers came

up with the idea of an active power factor correction
(PFC) circuit. Figure 8 shows a boost PFC circuit, which HFFET_LS LFFET_LS

generally takes a universal AC voltage (90 VAC to 264

VAC) and boosts the voltage to a regulated 400-V voltage
Figure 9. A totem-pole bridgeless PFC circuit.
at the output. With input voltage sensing, the controller
regulates the inductor current to follow the AC sinusoidal A continuous-conduction-mode (CCM) totem-pole
shape to get an almost unity power factor (0.99). bridgeless PFC is a hard-switching converter, which is
Vout widely applied in high-voltage rectifiers. Therefore, if
you apply a silicon MOSFET to a totem-pole bridgeless
PFC, the silicon MOSFET will suffer from high switching
VAC Load losses caused by Qrr. As shown in Figure 10, after
the top-left MOSFET body-diode current conduction, Qrr
will generate a reverse-recovery current to charge the
bottom-left MOSFET Coss during the dead time of the
Figure 8. Boost PFC circuit. left half bridge. Once the bottom-left MOSFET turns
on, the Qrr-induced energy will dissipate into the bottom-
This type of boost PFC rectifier is able to achieve
left MOSFET. The Qrr-related loss consumes the loss
really high efficiency (>98%) with a superjunction silicon
reduction on the full-bridge diode rectifier.
MOSFET and a SiC diode.
I

The full-bridge diode rectifier in the boost PFC rectifier irr

VDC
does consume more than 1% of overall efficiency losses
t
in kilowatt-level high-voltage systems. For example, a Qrr

more than 20-W loss on a full-bridge diode rectifier is HFFET_HS LFFET_HS

expected in a 2-kW rectifier. It is very difficult to dissipate
a 20-W loss from a single device. To reduce losses on + irr Load
VAC
the full-bridge diode rectifier, the totem-pole bridgeless –

PFC shown in Figure 9 presents a good alternative.

Because the rectifier function is integrated with the boost
converter and has only two additional MOSFETs (instead HFFET_LS LFFET_LS
0
of four diodes), the total rectifier loss (with the two low-
Figure 10. Switching losses caused by reverse-recovery charge
frequency FETs) is much lower than in the original bridge
in a totem-pole bridgeless PFC.
rectifier example.

Simplifying Power Conversion in High-Voltage Systems 6 November 2023

The existence of wide band-gap FETs can, for the most voltage power-conversion systems. Let’s continue using
part, help solve Qrr-related loss issues with the new PFC as an example. In high-power applications involving
totem-pole bridgeless PFC topology. A SiC MOSFET AC, a CCM PFC should be the first choice because
can achieve a 20 times smaller Qrr than a superjunction it allows a lower inductor ripple current; therefore,
MOSFET with the same on-resistance level – and a GaN you will need a smaller differential electromagnetic
FET can achieve zero Qrr. When combining component interference (EMI) filter. Compared to a CCM PFC,
and topology innovations in the rectifier example (in other a critical-conduction-mode (CRM) PFC has its PFC
words, applying wide band-gap FETs with a totem-pole inductor current always start from zero or even negative
bridgeless PFC), you can achieve over 99% efficiency with a smaller inductance, which enables much lower
(a >1% efficiency improvement), unlocking higher power switching losses and higher efficiency, as the current of
density and lighter weight in your designs. the power switches at the turnon instant is almost zero.
The inductor current ripple will be much higher than a
Achieving extreme efficiency targets with CCM PFC when delivering the same power, however,
system-level innovation
which can make EMI filter design difficult.
Today’s component and topology innovations enable
A third option offering the right balance between
power-conversion systems with much higher efficiency
efficiency and differential EMI noise levels is multimode
than ever before. An emerging DC grid system offers
operation – a combination of CCM and CRM operations
a much simpler, more efficient and more reliable high-
in every AC cycle. In multimode operation, the PFC
voltage solution over traditional centralized AC grid
inductor inductance should be smaller than the PFC
systems. For example, a photovoltaic (PV) power system
inductor used in CCM operation but larger than the PFC
requires only one power-conversion stage from the PV
inductor used in CRM operation in order to allow the PFC
panels to 120-V or 240-V AC grids. A distributed DC
to have both CCM and CRM operation over an AC cycle.
grid system could greatly simplify high-voltage power
Figure 11 illustrates the ripple current envelopes in these
conversion and increase system availability and reliability.
three modes.
Beyond system architecture innovations, control system
innovations are another way to simplify and improve high

Figure 11. PFC inductor currents (from left to right) under CCM, CRM and multimode operations.

Simplifying Power Conversion in High-Voltage Systems 7 November 2023

Figure 12 shows a loss comparison between a
multimode PFC and a CRM PFC (assuming that
zero voltage switching is guaranteed) with the same
specification. The multimode PFC design has a 150-µH
PFC inductor with an operational frequency ranging from
60 kHz to 250 kHz, while the CRM PFC design has a 25-
µH PFC inductor with an operational frequency ranging
from 75 kHz to 750 kHz. As a result, the CRM PFC
reduces FET losses over 40% at a half load, with a higher
operational frequency and a smaller inductor. This is an
indication of where highly efficient high-voltage power-
conversion systems should move – toward adopting soft-
switching topologies.

Figure 12. Frequency spectrum and FET losses in a multimode

PFC (left) and a CRM PFC in a 1.8-kW power-supply unit.

Addressing EMI challenges

Engineers can address EMI filter design challenges by
splitting the PFC inductor into two elements: one with
the higher-inductance inductor (Lg) connected to an AC
source, and the lower-inductance inductor (Lb) in series
with a capacitor and placed in parallel with the power
stage, as shown in Figure 13. The idea of splitting
inductor setup is to allow the large AC ripple current
to flow through the series inductor and capacitor (lower
total impedance) and to minimize the current ripple on
Lb (higher impedance) and the AC source. Therefore,
EMI filter design becomes easier, as the differential mode
noise is lower.

Simplifying Power Conversion in High-Voltage Systems 8 November 2023

 that the FET is already soft switching. Reducing the on-
time of HFFET_HS will minimize the root-mean-square
current for better efficiency. This way, the FET on-time is
HFFET_HS LFFET_HS
Lg no longer updated every cycle but is only adjusting when
soft switching isn’t occurring, which saves a lot on MCU
VAC Lb Load
resource usage.

Integrating the required soft-switching sensing circuit

with the FET could further simplify the system. As shown
in Figure 5, the LMG3526R030 device integrates a GaN
LFFET_LS
HFFET_LS
FET, driver, protections and FET drain-to-source voltage
sensing into one package. Whenever the GaN FET is
in third-quadrant conduction before channel conduction,
Figure 13. A modified totem-pole bridgeless PFC circuit.
the LMG3526R030 sends out a zero-voltage detection
Although the modified soft-switching CRM PFC does pulse as an indication of soft switching.
allow you to overcome EMI filter design challenges, the
Figure 14 shows example waveforms of the
CRM PFC itself requires additional sensing and control
LMG3526R030 with and without third-quadrant
efforts to determine PFC active switch turnon timing in
conduction.
order to ensure soft switching. One option is to add
current-sensing devices such as a current transformer
to detect the zero current point, which allows you to
then calculate active FET turnon timing based on the FET
Coss. Propagation delay in sensing and control systems
and component tolerance will result in active FET turnon
timing errors. Since this control scheme requires cycle-
by-cycle sensing and control, you should expect higher
MCU resource usage.

An alternative way is to calculate the required FET’s

on- and off-time based on the input and output voltage-
sensing results, along with the PFC inductance and
FET Coss. You can then use the FET drain-to-source
voltage sensing to determine whether you’ve achieved
soft switching. If the drain-to-source voltage doesn’t go
negative before the gate signal goes high, it means that
the FET is in hard switching.

Take the FETs shown in Figure 13 as an example, Figure 14. Waveform of the LMG3526R030 with (upper one) and
without third-quadrant conduction.
where extending the HFFET_HS on-time allows more
negative current to discharge HFFET_LS Coss in order
to achieve soft switching. If the drain-to-source voltage
goes negative before the gate signal goes high, it means

Simplifying Power Conversion in High-Voltage Systems 9 November 2023

Using the zero-voltage detection feature in
LMG3526R030, The Variable-Frequency, ZVS, 5-kW,
GaN-Based, Two-Phase Totem-Pole PFC Reference
Design has demonstrated over 99.1% peak efficiency
by combining component, topology and control system
innovations.

Conclusion
Today, it is much easier to design high-voltage power-
conversion systems than it was a decade ago, but
with new technologies come new challenges. There
won’t be a single-point breakthrough to bring us a
revolutionary high-voltage system – every piece of
the design has to evolve together to help engineers
maximize the efficiency, power density and performance
of high-voltage systems.

TI’s high-voltage power conversion technologies,

spanning GaN ICs, isolated gate drivers, isolated
DC/DC converters and modules and C2000 real-time
microcontrollers, take advantage of component, topology
and system-level innovations to simplify the design of
high-efficiency, high-power-density, high-voltage power
conversion systems. To learn more about TI’s high-
voltage technology, see the [Link]/highvoltage.

Additional resources
• Gallium nitride (GaN) ICs
• Isolated gate drivers
• Isolated DC/DC converters and modules
• C2000 real-time microcontrollers

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