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Analog IC Design Implementation and Verification

Week 1 – Introduction to Analog IC Design and Processes
Version IC 23.1 ISR11.29 with SPECTRE 24.1 ISR1
Revision 1.0

Estimated time: 1 Week

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Module Objectives
In this module, you
● Learn how to use NMOS and PMOS transistors to create basic circuit designs and analyze designs using
mathematical models of transistor behavior
● Explain the current and voltage characteristics of MOSFETs
● Use the different functional models to describe the performance of MOSFETs
● Explain the steps in the fabrication process for CMOS devices
● Explain the parameters that affect the switching performance of CMOS logic gates
● Describe the differences among various kinds of logic gates

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Introduction: MOSFETs Characteristics
● How does a MOSFET (metal-oxide-semiconductor field effect transistor) work?
● Current and voltage (I/V) characteristics
● Second-order effects

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Introduction: MOSFETs Applications

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MOSFET Modes: Cutoff
● How does a MOSFET work? Assume the MOSFET is an enhancement type. The first mode is called the
cutoff mode, and in this mode, the channel is not yet formed. (Actually, a small current that is called a
subthreshold current flows but can be ignored for now.)
● Electric-field strength is shown by the spacing of the arrows under the polysilicon layer.

VB = 0 VS = 0 VG < Vt VD ≥ 0
Bulk Source Gate Drain
Polysilicon
iD
;;;

p+ n+ Thin oxide (SiO2) n+

;; ;;;

p- substrate ;;;

Depletion region
;; ;;;

NMOS (n-channel metal oxide semiconductor) transistor

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MOSFET Modes: Active
● The second mode is called the active mode (also known as nonsaturated, linear, or triode mode).
● The region under the gate is inverted and current flows from drain to source.

VB = 0 VS = 0 VG > Vt 0 ≤ VD ≤ VGS - Vt
Bulk Source Gate Drain
Polysilicon
iD

p+ n+
;; ;;;; ;;;

n+
;;;

p- substrate;; ;;;; Channel current

;;;

;; ;;;

The arrow separation in the thin oxide represents the electric field strength.

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MOSFET Modes: Saturation
● The third mode is called the saturation mode (also known as the pentode mode). The drain voltage has
increased to the point where a depletion region is formed between the channel and the drain. The drain
voltage loses control over the drain current.

VB = 0 VS = 0 VG > Vt VD ≥ VGS - Vt
Bulk Source Gate Drain
iD
Polysilicon

p+ n+ n+
;;;

;; ;;;;

p- substrate
;; ;;;

;; ;;;

A depletion region forms between the drain and channel

The arrow separation in the thin oxide represents the electric-field strength.

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I/V Characteristics for Low vDS (Triode)
● iD is a function of the gate voltage.
● When vGS ≤ Vt, no current flows because no
channel is induced.
● As vGS increases, iD increases for a fixed vDS.
● For a fixed vGS, iD is proportional to vDS.
Therefore, the MOSFET acts like a variable
resistor.

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I/V Characteristics for Larger vDS
● For low vDS, the I/V curve is almost linear and
acts like a resistor.
● As vDS approaches vDSsat, the curve goes
nonlinear.
● Once vDS exceeds vDSsat, the depletion region
is formed, and the current is no longer a
function of vDS

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Derivation of the I/V Relationship
The MOSFET appears as a capacitor when biased such that a channel is induced below the gate,
enabling you to derive the I/V relationship:
● Gate: top plate
● Oxide: dielectric
● Channel: bottom plate

Gate

Oxide

Channel

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Derivation of the I/V Relationship (continued)

First calculate the capacitance of a strip dx wide:

Cstrip = CoxWdx where Cox is the capacitance per unit gate area

Because q = CV,
dq = −Cox (Wdx )(vGS − Vt ) − v( x)

= −CoxW (vGS − Vt ) − v( x) with the change in sign due to dq being a negative
dq

dx
charge.
The ultimate goal is to find i as a function of v(x), so
dq dq dx
i= =
dt dx dt

You can get dq/dx from the second set of equations, so you need to find dx/dt:
dv( x)
E ( x) = −
dx
dx dv( x)
= −  n E ( x) =  n where µn is the mobility of the electrons in the channel.
dt dx

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Derivation of the I/V Relationship (continued)

Now solve for iD , which is the drain current and the opposite of i:

= CoxW (vGS − Vt ) − v( x)  n

dq dx dv( x)
iD = −i = −
dx dt dx
 iD dx =  nCoxW (vGS − Vt ) − v( x)dv( x)

Integrating both sides and rearranging:

L v ( L ) = v DS

 iD dx =  C n ox W (vGS − Vt ) − v ( x )dv ( x)
0 v ( 0 ) =0
v ( L ) = v DS v ( L ) = v DS

iD L =  n CoxW  (v
v ( 0) =0
GS − Vt )dv ( x ) −  n CoxW  v( x)dv( x)
v ( 0 ) =0

 W  1 2 
 iD =  n Cox   (vGS − Vt )vDS − vDS 
(triode region)
 L  2 
W 
 iD =  n Cox  (vGS − Vt )
1 2
(saturation region, where vDS = vGS - Vt)
2  L

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Second-Order Effects
The iD equation from the previous slide gives a good first-order approximation to the performance of a
MOSFET. However, secondary effects have to be accounted for.
Some second-order effects include the following:
● Body effect
● Channel-length modulation
● Subthreshold conduction

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Body Effect
Definition: The effect on MOSFET
performance due to the voltage
difference between the source and the
substrate.
● Usually, the substrate is tied to the
lowest voltage (for NMOS) to avoid the
forward biasing of any pn junctions.
● The more reverse-biased the pn junction
becomes, the larger the depletion region
grows, which reduces the channel depth.
● When the channel depth is reduced,
more vGS is required to restore it to its
previous depth.
● The body effect is usually accounted for ● Vt0 is the threshold voltage for VSB = 0.
by modifying the equation for the ● Φf is a physical parameter approximately equal to 0.3V.
threshold voltage Vt:
● γ is a fabrication-process parameter typically around 0.4√V.
Vt = Vt 0 +   2 f + VSB − 2 f 
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Channel-Length Modulation
Definition: The reduction in the length of the conduction channel caused by increasing vDS past
vDSsat.
● Channel-length modulation occurs when vDS is increased past vDSsat.
● The channel shortens by ΔL, as shown in the figure.
● Going back to the derivation for iDS, substitute L - ΔL for L. Assuming that ΔL << L:
 W  L 
(vGS − VT )
1
iD =  nCox  1 + 2

2  L  L 

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Channel-Length Modulation (continued)
Making a substitution for ΔL Making another substitution
(and assuming that ΔL is '
L =  ' vDS proportional to vDS): =
L
W 
iD =  nCox  (vGS − Vt ) (1 + vDS )
Substituting this into the 1 2

previous equation gives 2 L

 W   '  where λ is a process-technology parameter with
 nCox  1 + vDS (vGS − Vt )2
1
iD =
2  L  L  units of V-1

Also known as the early voltage

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Subthreshold Conduction
Definition: The conduction of
current from drain to source even
though vGS is below Vt. Square law

log iD
● To a first order, there is no drain Exponential
current when vGS is below Vt.
● To a second order, however, this is
not strictly true.
● There is an exponential relationship
between this subthreshold current Vt
and vGS:
vGS

iD = i0 e Vt
where ζ>1 is a nonideality factor.

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Summary: MOSFET Characteristics
● Three MOSFET modes
▪ Cutoff
▪ Active (nonsaturated, linear, triode)
▪ Saturation (pentode)

● MOSFET I/V characteristic

▪ Different equations for different modes
▪ Derivation of the drain current equation for subthreshold and saturation regions

● Second-order effects
▪ Body effect
▪ Channel-length modulation
▪ Subthreshold conduction

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Introduction: MOSFET Device Models
● Models provide abstraction from the physics of the device.
● Simplified models are useful for basic understanding and hand calculations. Computer models can be far
more complex with hundreds of possible parameters.
● Models should be as simple as possible for hand calculations.
● Simulation programs also use simplifications of models where appropriate (for example, AC analysis versus
transient analysis).
● The main industry focus is now on very sophisticated models that enable covering the whole range from
linear analysis up to the inclusion of second- and third-order effects.

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Characterization of Models

Time dependence
Static Dynamic

Small-signal, midband: Small-signal

Rin, Av, Rout frequency response:
Linear poles and zeros

Linearity Cgs, Cgd

DC operating point: Large-signal

transient response:
iD = f(vD,vG,vS,vB)
Nonlinear slew rate

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MOSFET Large-Signal Models
The three regions of operation include: D
+
● Subthreshold
▪ vGS ≤ Vt iD
▪ Channel not yet fully formed
G B vDS
● Active (nonsaturation) + +
▪ vDS < vGS - Vt
vGS vBS
▪ Channel exists; current depends on vDS and vGS. - -
● Saturation S
▪ vDS > vGS - Vt
▪ Channel exists; current primarily a function of vGS.

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First-Order Large-Signal Model Equations
● Subthreshold (vGS ≤ Vt) Where:
● µo = zero field mobility (cm2/volt·sec)
vGS

iD = i0 e Vt ● Cox = gate oxide capacitance per unit area (F/cm2)

● λ = channel-length modulation parameter (volts-1)
● Vt0 = zero-bias threshold voltage
● Nonsaturation (vDS < vGS - Vt) ● γ = bulk threshold parameter (volts-0.5)
● 2Φf = strong inversion surface potential (volts)
WoCOX  vDS 
2
iD = (vGS − Vt )vDS − (1 + vDS )
L  2 

Note: For p-channel MOSFETs, use n-channel equations

with p-channel parameters and invert current.

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First-Order Large-Signal Model Equations (continued)
Saturation
WoCOX  vDS ( sat ) 
2
Where:
iD = (vGS − Vt )vDS ( sat ) −  (1 + vDS )
L  2 
● µo = zero field mobility (cm2/volt·sec)
WoCOX ● Cox = gate oxide capacitance per unit area (F/cm2)
iD = (vGS − Vt )2 (1 + vDS )
2L ● λ = channel-length modulation parameter (volts-1)

Vt = Vt 0 +   2 f + VSB − 2 f  ● Vt0 = zero-bias threshold voltage

● γ = bulk threshold parameter (volts-0.5)
VA where ID is the drain current without ● 2Φf = strong inversion surface potential (volts)
ro = channel-length modulation taken into
ID
account.

Note: For p-channel MOSFETs, use n-channel equations

with p-channel parameters and invert current.

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Large-Signal Model
The information from the previous slide
can be incorporated into a large-signal
model with the following assumptions:
● Input impedance is .
k 'n =  n Cox
● The transfer characteristic is modeled as a
voltage-controlled current source.
● ro is based on the early voltage, VA
(typically 2 to 50V, depending on the gate
length and technology).

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Example: Large-Signal Model
Find the DC operating point of the
RD = ID
NMOS transistor shown, assuming R2 =
10 kΩ
kn’ = 25 µA/V2, W/L = 10, VtN = 1V, and λ = 0. RS=1 kΩ 70 kΩ
+ 10V
VDS
+
+
R1 = VGS RL= vout
30 kΩ - - 10 kΩ -
Solution vin

30k
VGG = VGS =
R1
VDD = (10V )
R1 + R2 30k + 70k
VGG = 3V

Assume the MOSFET is in saturation and find ID:

Wk n
ID = (VGS − Vt )2 = 25 10 (3 − 1)2 = 500A
2L 2
Check to see if the transistor is in saturation:
VDS = VDD − I D 10k = 5V
VDS  VGS − Vt  5  (3 − 1)  5V  2V
(Transistor in saturation: )

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Small-Signal Frequency-Independent Models
Two possible frequency-independent models are:
● With ro
● Without ro
The choice of one over the other depends on
whether ro significantly changes the resistance at
the output.

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Small-Signal Models
The small-signal model is essentially the linear part of a power-series expansion
of the drain current dependence on gate, bulk, and drain voltages.

diD di di
id  vgs + D vbs + D vds +  = g m vgs + g mbs vbs + g ds vds + 
dvGS Q dvBS Q dvDS Q

Schematic model: id
D D
G B D
+ + +
G B G B vgs vbs rds vds
gmvgs gmbsvbs
- - -
S S
S S
Where:
diD iD
=  (vGS − VT ) = 2I D
diD g ds  =  i D
gm 
dvGS Q
dvDS Q
1 + vDS
iD  i  vGS   i  Vt  g m
g mbs = =  D   =  − D   = = g m
vBS Q  vGS  vBS  Q  Vt  vBS  Q 2 2  f − vBS
Engineering approximation:
  0Cox
W
= k n
W gm 10gmbs 100gds
L L
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Small-Signal Models for the Nonsaturated Region
● In the nonsaturated (triode) region, gm has to be calculated differently:
iD k nWv DS 
gm = = (1 + vDS )   knW vDS
vGS Q
L  L 
iD k nWvDS
g mbs = =
vBS Q
2 L 2 f − vBS
k nW 
g ds =
iD
= (vGS − Vt − vDS )(1 + vDS ) + I D   knW (vGS − Vt − vDS )
vDS Q
L 1 + vDS L

● The most obvious difference is that all of the transconductances are now functions of vDS not iD (as long iD
is small enough for VDS<VDsat).

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Frequency-Dependent Small-Signal Models
Inductance effects for devices in ICs are usually smaller than capacitance effects and are usually
neglected in the small-signal model.
There are two types of capacitance regarding MOSFETs:
● Charge storage: Caused by the gate and channel acting as capacitor plates with the gate oxide acting as
the dielectric.
● Depletion: Caused by the depletion layer formed by reverse-biased pn junctions.
Some models for very high frequencies also include delay effects.

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MOSFET Capacitances
Five primary parasitic capacitances must be accounted for in the small-signal
frequency-dependent model:
● Charge storage
▪ Cgs SiO2
▪ Cgd

● Depletion
▪ Cgb Gate
▪ Csb Source Drain

▪ Cdb Cgs
Cgd
Field Field
oxide Cgb oxide
Csb Cdb

Bulk

Note: For the designer, usually, the total of CGS and CGD is the most important.
The five capacitances cannot be easily separated, which is a problem for
parameter extraction. Consequently, special test structures are often used.
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MOSFET Charge-Storage Capacitances
In the triode region with the channel of uniform depth, the total capacitance can be
split between source and drain:
1
C gs = C gd = WLC ox
2
In the saturation region, the channel at the drain is pinched off so that most of the
capacitance is assigned to the source and none to the drain:
2
C gs = WLC ox Cgd = 0
3
When the MOSFET is cut off, there is no channel, and therefore no capacitance
between the gate and the source or drain. There is still a capacitance between the
gate and substrate:
Cgs = Cgd = 0 Cgb  WLCdepletion
For more accuracy, an additional capacitance should be added to the previous
values. This capacitance is caused because the source and drain diffusions exist
slightly under the gate oxide. Typically, Lov = 0.05 to 0.1L.

Cov = WL ovCox

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MOSFET Depletion Capacitances
The depletion capacitances can be found using the following formulas:
Csb 0 Cdb0
Csb = Cdb =
V V
1 + SB 1 + DB
V0 V0

Where:
● Csb0 and Cdb0 are the capacitances at zero reverse-bias voltage.
● VSB and VDB are the magnitudes of the reverse-bias voltages.
● V0 is the junction built-in voltage (typically, approximately 0.6V to 0.8V).

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Equivalent Small-Signal Models
Putting together the small-signal model with the
capacitors results in the equivalent small-signal
frequency-dependent model shown in figure (a).

In the common case when the source and bulk

are tied together, the slightly simpler model
shown in figure (b) can be used.

Note: This represents the so-called intrinsic MOSFET

device. Series resistors at each terminal should be
added for representing the complete device.

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Summary: MOSFET Models
Models
● Large signal
● Small signal
▪ Frequency independent
o Active mode
o Saturation mode
▪ Frequency dependent

MOSFET capacitances
● Charge storage
● Depletion

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Introduction: CMOS Fabrication
● Wafer preparation: Processing the raw semiconductor material to be of extremely high quality with few
defects and grown as a single crystal.
● Photolithography: Transferring the circuit layout to the wafer by the use of masks to reveal some parts of
the wafer and hide others.
● Oxidation: Forming a very uniform oxide layer on the silicon, which is used to insulate process layers from
one another.
● Ion implantation/diffusion: Doping specific parts of the wafer to be an n-type or p-type semiconductor.
● Deposition and etching: Depositing materials on the wafer and removing the unwanted material.

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Wafer Preparation: Materials
The wafer can be made of any of a number of different semiconductors:
● Silicon (Si)
● Gallium arsenide (GaAs)
● Silicon germanium (SiGe)
● Other exotic materials
The most common base material is silicon.

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Wafer Preparation: Czochralski Method
The silicon is grown by the Czochralski method:
● Starts with a single silicon seed.
● The seed is immersed in molten silicon and slowly rotated and pulled.
● The result is an ingot of single-crystal silicon with few defects.
The ingot is sliced into thin wafers that form the starting point for IC fabrication:

125-200 mm
(5"-8") 0.5-0.8mm

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Photolithography
● Photolithography is the process of using light to transfer an image to a surface (in this case, the silicon wafer)
by coating the surface of the wafer with an ultraviolet-light-sensitive material called photoresist.
● The photoresist is then developed with a chemical that removes the UV-processed areas, leaving a replica of
the pattern on the surface of the wafer.
● Depending on the type of photoresist used, either the photoresist exposed to UV radiation is removed
(positive photoresist), or the areas not exposed to UV radiation are removed (negative photoresist).

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Illustration of Photolithography

Photomask

UV light

Photomask

Photoresist
Polysilicon

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Positive and Negative Photoresist
Positive Photoresist Negative Photoresist

Polysilicon

1. Develop

Underlying layer
SiO2
Photoresist
Photoresist
Photoresist
Polysilicon

2. Etch

Underlying layer
SiO2

SiO2

Polysilicon 3. Remove
photoresist

Underlying layer

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Oxidation
Oxidation is the process by which a layer of silicon dioxide is grown on the surface of a silicon wafer:
● It protects the underlying material from contamination.
● It provides isolation between two layers.
● Its thicknesses can vary between 10Å to over 1000Å.
● MOS transistor oxide is the thinnest oxide layer. Field oxide is much thicker.

Original silicon surface tox

Silicon dioxide

0.44 tox Silicon substrate

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Ion Implantation
Ion implantation is the process by which impurity
ions are accelerated to a high velocity and
physically lodged into the target material: Path of impurity atom

● Annealing is required to activate the impurity

atoms and repair the physical damage to the Fixed atom
crystal lattice. This step is done at 500 to 800 C. Fixed atom

● Ion implantation is a lower-temperature process Impurity atom final

Fixed atom
resting place
compared to diffusion and enables more shallow
doping profiles, which are required for submicron
Concentration peak
devices. N(x)

● The process can be implanted through surface

layers. Thus, it is useful for field-threshold NB
adjustment.
0 Depth (x)
● Ion implantation can achieve unique doping
profiles, such as buried concentration peak.

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Diffusion
Diffusion is the movement of impurity atoms at High Low
the surface of the silicon into the bulk of the concentration concentration

silicon:
● Diffusion is always in the direction from higher ERFC
N0
concentration to lower concentration.
N(x) t1 < t2 < t3
● Diffusion is typically done at high temperatures of
NB
800 to 1400 C.
t3
t1 t2
Depth (x)
Infinite source of impurities at the surface

Gaussian
N0

N(x) t1 < t2 < t3

NB
t2 t3
t1
Depth (x)
Finite source of impurities at the surface

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Deposition
Deposition is the means by which various materials are deposited on the silicon wafer:
● Examples
▪ Silicon nitride (Si3N4)
▪ Silicon dioxide (SiO2)
▪ Aluminum
▪ Polysilicon

● There are various ways to deposit a material on a substrate:

▪ Chemical-vapor deposition (CVD)
▪ Low-pressure chemical-vapor deposition (LPCVD)
▪ Plasma-assisted chemical-vapor deposition (PECVD)
▪ Sputter deposition

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Etching
Etching is the process of selectively
removing a layer of material: Mask
Film

● When etching is performed, the etchant Underlying layer

might remove portions or all of the Portion of the top layer ready for etching

▪ Desired material a Selectivity

▪ Underlying layer Mask
Film c
▪ Masking layer b
Anisotropy
Selectivity Underlying layer
● Important considerations Horizontal etching and etching of underlying layer

▪ Anisotropy (A)
▪ Selectivity (S) (lateral _ etch _ rate )
A = 1−
▪ Ideally, A = 1 and S =  (vertical _ etch _ rate )

● There are two types of etches: ( film _ etch _ rate )

S=
▪ Wet etch ‒ uses chemicals (mask _ etch _ rate )
▪ Dry etch ‒ uses chemically active ionized
gases

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Process and Device Variability
All process parameters, such as temperatures used, doping levels, and so forth, vary slightly:
● There are global variations (between lots, between wafers in a lot, and so forth.) and local variations (for
example, between two devices close together).
● In the past people could assume that, within a wafer, the parameters would not vary much, but there were
significant variations from lot to lot. However, modern wafers are so large that across one wafer there are
also significant parameter gradients.
● Local variations are due to the atomic nature of the materials plus process imperfections.
Layer thickness and doping levels vary; therefore, the resistivity of the resistor layer varies or unit
capacitances, also transistor threshold voltage, breakdown voltages, and so forth, vary as well.

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Process and Device Variability (continued)
The length and width of components vary:
● Length and width are not 100% as defined by the mask.
● The mask is not 100% as defined by the designer or the software.
● Additional variations in resistances, and so forth.
Even devices that are close together and drawn in the mask, in the same way, do not have 100% of
the same characteristics:
● Matching is limited, which is one major problem in any analog design because systematic variations are
usually easier to compensate for than random imperfections.
● The most critical is limited matching for threshold voltage VTO of MOS transistors.

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Summary: CMOS Fabrication
● CMOS fabrication steps
▪ Wafer preparation: Preparing the silicon for use.
▪ Photolithography: Transferring the circuit layout to the wafer:
▪ Oxidation: Forming a very uniform oxide layer on the silicon.
▪ Ion implantation/diffusion: Doping specific parts of the wafer.
▪ Deposition and etching: Depositing materials on the wafer and removing the unwanted material.

● Processing variability

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Introduction: CMOS Switching Behavior
The switching performance of a CMOS logic gate can be specified with the following parameters:
● Noise margin
● Propagation delay, rise time, and fall time
● Power dissipation
● Delay-power product
● Fan-in/fanout

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Noise Margin
Definition: Parameter that indicates the susceptibility of a
circuit to noise.
● The static operation of a gate is given by its voltage transfer
characteristic (VTC).
● The VTC defines the output voltage as a function of the input
voltage.
● The VTC has five parameters:
▪ VOH
▪ VOL
▪ VIH (defined where slope = -1)
▪ VIL (defined where the slope = -1)
▪ VM or Vth (defined where vo = vi)

● Noise margin can be defined as

▪ NMH = VOH – VIH
▪ NML = VIL – VOL
Inverter curve showing noise margin measurements.
● The noise margin measures the robustness of a logic family.
The smaller the margins, the more susceptible the family is to
noise.

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Propagation Delay
Definition: The time it takes for a signal at
the input to affect the output signal.
Propagation delay characterizes the
dynamic performance of a logic circuit:
● The overall propagation delay is defined as
the average of the two specific delays:
t PD =
1
(t PLH + t PHL )
2
● Shorter delays equal faster overall
operation.
● Rise and fall times are asymmetric due to
different mobility, thresholds, and sizing of
NMOS and PMOS transistors.
Definition of low-to-high and high-to-low propagation delay.

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Power Dissipation
Definition: The amount of power dissipated in a circuit.
Low-power dissipation is important:
● Reduces heat
● Reduces power requirements (increases battery life)
● Increases circuit density
The two types are
● Static: Power that is dissipated when not switching.
● Dynamic: Power that is dissipated during switching.

Dynamic power dissipation can be calculated as PD = fCV DD .

2

CMOS advantage: Per gate, static power dissipation is virtually zero. However, for millions of gates,
the power dissipation might not remain negligible.

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Delay-Power Product
Definition: A figure of merit that is used to compare different logic families:
● High-speed and low-power dissipation are usually in conflict. Lower propagation delays usually
require more power.
● The delay-power product is a figure of merit that can be used to compare various logic
technologies:
DP = PD t P

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Fan-In and Fanout
● Fan-in: The number of inputs on a gate.
● Fanout: The maximum number of gates of similar size that the gate can drive while remaining within
specifications.
CMOS: Because static current is low, even a small gate can drive many others, but each additional
gate adds capacitance and reduces overall speed.

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Summary: CMOS Switching Behavior
CMOS switching parameters
● Noise margin
● Propagation delay, rise time, and fall time
● Power dissipation
● Delay-power product
● Fan-in/fanout

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Introduction: CMOS Logic Structures
Logic gate circuits
● Basic structure
▪ Symbols and conventions
▪ PUN (Pull-up network)/PDN (Pull-down network)
● Combinatorial circuits
▪ Inverter
▪ NOR gate
▪ NAND gate
▪ XOR gate
▪ More complex gates
● Sequential circuits
▪ Latches
▪ Flip-flops
● Non-CMOS logic circuits
▪ Pass-transistor logic circuits
▪ NMOS and CMOS switches
▪ Dynamic logic

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Circuit Symbols and Boolean Conventions
Introduction of symbols and conventions
● To reduce schematic complexity, a simpler MOSFET symbol is used for logic gates as shown.
● Boolean conventions:
▪ OR: Y = A + B
▪ AND: Y = AB

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Basic Structure of a CMOS Logic Gate
All CMOS gates are an extension of the basic
inverter. The CMOS logic gate can look at any other
CMOS gate as two networks:
● PUN (pull-up network): Consists of PMOS devices
and is connected to the upper voltage rail (usually
VDD).
● PDN (pull-down network): Consists of NMOS
devices and is connected to the lower voltage rail
(usually ground).
Because the PDN consists of NMOS devices, it is
activated when the inputs are high. Likewise, the
PUN is activated by low signals.

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Example: Pull-Up Networks

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Example: Pull-Down Networks

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Basic Circuits: CMOS Inverter
Inverter: Y = A

Design Procedure
● PUN: Notice that when vO is high,
the input is low. The PUN requires
only one PMOS device.
● PDN: Notice that when vO is low the
input is high. Therefore, the PDN
consists of only one NMOS device.

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Basic Circuits: CMOS NOR Gate
NOR Gates: Y = A + B = A  B

Design Procedure
● PUN: Using the second form of the equation, notice
that A and B must both be low to make Y high.
Therefore, the PUN consists of two series of PMOS
devices.
● PDN: Notice that Y is low when either A or B is high.
Therefore, the PDN consists of two parallel NMOS
devices.

Note: You should avoid having too many PMOS

devices in a series.

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Basic Circuits: CMOS NAND Gate
NAND Gates: Y = AB = A + B

Design Procedure
● PUN: Using the second form of the equation, notice
that either A or B must be low to make Y high.
Therefore, the PUN consists of two parallel PMOS
devices.
● PDN: Notice that Y is low when both A and B are
high. Therefore, the PDN consists of two series of
NMOS devices.

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Basic Circuits: CMOS XOR Gate
XOR Gates: Y = A  B + A  B

Design Procedure
● Because Y is given, it is easier to design
the PUN first. The design for the PUN is
shown.
● To generate the PDN, get an expression
for Y and then synthesize:

Y = A B + A B
= A B  A B

(
= A+ B  A+ B )( )
= A B + A B

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Basic Circuits: More Complex Gates
General PUP/PDN approach: Y = A  (B + C  D )
Find expressions for Y and Y using
DeMorgan’s law:
Y = A  (B + C  D )
Design Procedure
● PDN: Notice that the PDN network can be
created by inspection.
● PUN: Using DeMorgan’s law:
Y = A  (B + C  D )
= A+ B +CD
= A + B  (C  D )
= A+ B C + D ( )
● Now the PUN can be created.

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Sequential Logic
● Combinatorial logic changes whenever the inputs change. Sequential logic only changes at discrete times,
usually through the use of a periodic signal called a clock.
● Sequential logic is useful for applications where information must be stored. The most common circuits are
latches and flip-flops, which are capable of storing one bit of information until commanded to change.

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Latches
● The latch is the basic memory element. The inverters shown are connected in a positive feedback loop
so that the output ends up at either VOH or VOL because any other point is unstable.
● Based on external excitation, the latch achieves one of the two states and then holds that output
indefinitely. Without inputs, it is not particularly useful, but the structure forms the basis of something far
more useful flip-flops.

Basic Latch with Determining the operating

latch feedback loop points of the latch
opened

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Setting and Resetting Flip-Flops
● The simplest flip-flop (the set/reset ‒ SR‒ flip-flop) uses the positive feedback principle of the latch to hold
data. A schematic and truth table are shown.
● Improving the design means incorporating the ability to also clock the flip-flop, as shown in the right-most
figure. The clock signal is denoted by φ.

SR flip-flop SR flip-flop CMOS implementation of

truth table clocked SR flip-flop

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Data Flip-Flops
● The data (D) flip-flop is an example of an edge-triggered design. When the clock is low, the flip-flop holds the
output data. When the clock goes high, the output changes state to whatever the input signal was just prior to
the rising edge of the clock.
● In the simple implementation of the D flip-flop shown, notice that the two clock phases must be
nonoverlapping. In other words, proper operation requires that the two clock phases are never high at the
same time.

Circuit with two-phase Waveforms of D

nonoverlapping clock flip-flop circuit

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Data Flip-Flops (continued)
The previous design has one flaw: When φ is high, the output follows the input which can create
problems in some designs. The following design, called a master-slave D flip-flop, fixes that flaw. The
switches can be, and usually are, implemented with CMOS transmission gates.

Master-slave D Waveforms of the two-phase

flip-flop nonoverlapping clock required

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Nonstandard Logic Structures
Nonstandard logic structures are gates that are not considered true CMOS. The reasons for choosing
one include:
● The need for very high density.
● The need for very high speed or very low power.
Some logic types are particularly good for specific circuits. An example of this is the use of pass-
transistor logic for multiplexers.

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Pass-Transistor Logic Circuits
Pass-transistor logic circuits (PTL) use
CMOS transmission gates in series and/or
parallel to realize various gates:
● Depending on the application, one of two
types of transmission gate can be used:
▪ Single NMOS T-gate
▪ CMOS T-gate Y = A  (B + C ) Y = A B  C
● In the CMOS T-gate, notice the need to
provide complementary control inputs.
● PTL has no buffering, that is, the load
current has to be delivered from the driving
source and the output swing does not
recover (at best equal to input swing).

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Low-Resistance PTL Paths

Note: To satisfy static logic requirements every circuit node must have at all times a
low-resistance path to ground or VDD available. Otherwise, a dynamic logic circuit is
created that needs constant refreshing of the gate charge similar to DRAM bits.

With S1 open, node Y floats and Providing a complementary

output of Q3/Q4 is indeterminate. switch S2 solves floating node
problem.

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NMOS Switches
Advantages Disadvantages
● Small area ● Slow rise and fall times.
● Small node capacitances ● Output voltage is not VDD but VDD-Vt.
● Reduced gate noise immunity.
● Can have static current/power dissipation.

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Modified NMOS Switches
The following are two possible improvements to NMOS switches:
● Circuit-based approach: Use of a second transistor to restore the level to VDD.
● Process technology approach: Use devices that have zero threshold voltage. Fabricated by ion
implantation and called natural devices.

Note: These devices have higher than

normal leakage because when off Vgs = Vt.
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CMOS Switches
Advantages Disadvantages
● Good static and dynamic performance ● Larger than NMOS switch
● Bidirectional current flow ● Need for additional inverted drive
● Good for analog applications also

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CMOS Switch Examples

2:1 Multiplexer XOR

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Dynamic Logic Gates
● Store signals on parasitic capacitances on open nodes.
● Require a clock to periodically refresh the data.
● Have a low-device count, higher speed, and lower power at the expense of increased complexity
and loss of robustness.

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Dynamic Logic Gates (continued)

● When Φ is low, the storage node with load CL is charged to VDD. Inputs are allowed to change and settle.
● When Φ is high, the PDN network evaluates the inputs and either conduct (Y=0) or does not (Y= VDD).
● The output is valid only when the clock is high (evaluate), because Y is always forced to V DD when the clock
is low (precharge).

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Summary: Logic Gate Circuits
● Basic logic gate structure
▪ Symbols and conventions
▪ PUN (pull-up network)/PDN (pull-down network)

● Standard CMOS circuits

▪ Combinatorial circuits (NAND, NOR, and so forth)
▪ Sequential circuits (flip-flops)

● Other logic structures

● Pass-transistor logic circuits
● NMOS and CMOS switches
● Dynamic logic

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