1].

Von Neumann Architecture – (10 Marks Answer)

The Von Neumann architecture is one of the fundamental computer architectures

proposed by mathematician and computer scientist John Von Neumann. It is based on
the concept of the stored program machine, where both program instructions and data
are stored in the same memory.
Diagram of Von Neumann Architecture

Explanation:
1. Stored Program Concept
In Von Neumann machine, the program (instructions) and data are stored together in
the same memory unit.
The CPU fetches instructions from memory one after another and executes them
sequentially unless altered by a branch/jump.

2. Main Units of Von Neumann Architecture

(a) Central Processing Unit (CPU)
CPU contains two main units:

i. Arithmetic and Logic Unit (ALU)

Performs arithmetic operations like addition, subtraction, multiplication, division.
Performs logic operations like AND, OR, EXOR, NOT.
Receives operands from registers and returns results to memory or registers.

ii. Control Unit (CU / Program Control Unit – PCU)

Controls all internal and external operations of the computer.
 Sends control signals for memory read/write, instruction execution, and data
movement.
Coordinates ALU, memory, and I/O operations.
(b) Memory Unit
Stores the program instructions and data in the same memory (common memory).
Each memory location has a unique address.
CPU fetches instructions/data from memory using the address bus and returns results
through the data bus.

(c) Input Unit

Takes input from user through keyboard, mouse, scanner, joystick, etc.
Converts the input into a form understood by the computer.

(d) Output Unit

Sends results to output devices such as monitor, printer, speakers, plotters, etc.

3. CPU Internal Registers (as per textbook diagram)

i. Accumulator (AC)
Temporary storage for operands and results from ALU.

ii. Memory Address Register (MAR)

Holds the address of the memory location from where data/instruction is to be fetched
or stored.

iii. Data Register (DR)

Acts as a buffer between memory and CPU.
Stores data fetched from memory temporarily.

iv. Program Counter (PC)

Always contains the address of the next instruction to be executed.

v. Instruction Register (IR)

Holds the current instruction being executed.

4. Working / Execution of a Program in Von Neumann Machine

Step 1: Fetch Cycle
1. The address of instruction is copied from PC to MAR.
MAR ← PC
2. MAR places the address on the address bus to select the memory location.
3. Control Unit issues Read (RD) signal.
4. Instruction is fetched from memory and loaded into the DR.
5. From DR, instruction is moved to Instruction Register (IR).
6. PC is incremented to point to the next instruction.
Example: `PC = PC + 1`

Step 2: Decode and Execute Cycle

CU interprets the opcode present in IR.
It generates necessary control signals to:
Perform ALU operations.
Transfer data between CPU and memory.
Transfer data between CPU and I/O devices.

Key Features of Von Neumann Architecture:

Uses stored program concept.
Common memory for instructions and data.
Each memory location has a unique address.
Execution is sequential, unless a branch instruction changes the flow.
Needs two clock cycles per instruction:
One for instruction fetch.
One for data fetch (if required).

Advantages:
Simpler design and easier to implement.
Lower cost because program and data share the same memory.
Flexible since memory can be used by both data and instructions as needed.

Limitations (Von Neumann Bottleneck):

Only one memory bus for both instruction and data → causes delay.
CPU cannot access instruction and data simultaneously.

Conclusion:
Von Neumann architecture is the foundation of most generalpurpose computers. With a
single shared memory for program and data, and sequential instruction execution, it
provides a simple yet powerful computing model that forms the basis of modern digital
systems.
2] Explain Flynn’s Classification
Flynn’s Classification is a method that classifies computer architectures based on the
number of instruction streams and data streams being processed. According to Flynn, a
computer system may have a single or multiple instruction streams, and it may operate
on single or multiple data streams. Based on this combination, he identified four types of
computer organizations: SISD, SIMD, MISD, and MIMD.

1. SISD – Single Instruction Single Data:

In SISD systems, there is one processor, which executes one instruction at a time and
operates on one data stream. It contains a single control unit and a single processing
element. All operations take place sequentially, which makes SISD the traditional
uniprocessor model.

2. SIMD – Single Instruction Multiple Data

In SIMD, a single control unit issues one instruction, and this instruction is executed
simultaneously by multiple processing elements on different data items. The processing
elements work in parallel, each using its own local memory. This organization is suitable
for operations on large arrays, such as in vector or array processors.
 3. MISD – Multiple Instruction Single Data
In MISD systems, multiple instruction streams operate on the same data stream. Each
processing element has its own control unit and executes a different instruction, but all
use the same data. This type of architecture is uncommon, but it can be used in
systems where the same data needs to go through multiple operations for reliability and
fault tolerance.

4. MIMD – Multiple Instruction Multiple Data

In MIMD, each processor has its own control unit, own instruction stream, and own data
stream. Different processors can execute different instructions on different data
simultaneously. This architecture is used in modern multiprocessor and multicomputer
systems, including clusters and distributed systems.
 Computer Architecture Computer Organization

Deals with the functional design and Deals with the physical
structure of the computer system. implementation of components and
their interconnections.

Focuses on what the computer system Focuses on how the system is

does. implemented internally.

Includes instruction set architecture Includes hardware details like control

(ISA), addressing modes, data types, signals, data paths, ALU operation,
memory models, etc. microinstructions.

More related to logical/abstract design More related to hardware-level design

and system behavior. and signal-level operations.

Example: Size of registers, type of Example: ALU design, control unit

processor (RISC/CISC), number of bits in design (hardwired/microprogrammed),
instruction. timing and sequencing.

Architecture is visible to the Organization is visible to the hardware

programmer. engineer.

Specifies the performance parameters Determines the actual performance

such as instruction format and memory through pipeline, cache organization,
hierarchy. and bus structure.

Involves high-level design decisions Involves low-level design decisions

used by assembly language used in hardware implementation.
programmers.

Architecture remains mostly constant for Organization may vary between

a processor family. different models of the same
architecture (e.g., Intel i3, i5, i7 use
same x86 architecture).
 Encoder Decoder

Converts 2ⁿ input lines into an n-bit Converts n-bit binary input into 2ⁿ
binary code. output lines.

Performs encoding of active input into a Performs decoding, activating exactly

binary representation. one corresponding output line.

Reduces multiple inputs into fewer bits. Expands binary input into a larger
number of outputs.

Has fewer output lines than input Has more output lines than input
lines. lines.

Example: 8-to-3 encoder, priority Example: 3-to-8 decoder, 2-to-4

encoder. decoder.

Used in keyboard encoding, data Used in memory address decoding,

compression, priority systems. instruction decoding, demultiplexing.

Works properly when only one input is For a given binary input, only one
active at a time (except priority output will be HIGH (one-hot output).
encoder).

May need priority logic to resolve Often uses Enable (EN) signal to control
multiple active inputs. the decoding operation.

Outputs are binary codes. Outputs are one-hot signals.

Encoding usually reduces hardware Decoding generally increases hardware

complexity. complexity because of more outputs.
 Interleaved Memory Associative Memory

Divides memory into multiple modules Stores data based on content (value)
that can be accessed in parallel. rather than address.

Used to increase memory access speed Used to search data by content, not by
by overlapping accesses. address.

Access is address-based (normal Access is content-based (match logic).

memory address).

Helps reduce memory bottleneck by Helps in fast lookup, especially in

providing simultaneous access paths. cache (tag match).

Example: 2-way, 4-way, 8-way Example: CAM – Content Addressable

interleaving. Memory.

Mainly used in high-performance CPU Mainly used in cache memory, TLB,

memory systems, main memory. associative lookup tables.

Improves bandwidth, not searching Improves search speed but memory is

capability. more expensive.

Data stored in consecutive addresses is Data is stored with key-value pair,

distributed across memory banks. where matching key returns data.

Access time depends on parallelism Access time is constant, as comparison

(number of banks). happens in parallel for all cells.

Cheaper and simpler to implement More complex and costlier due to

compared to associative memory. parallel comparators.