Module-II

The Cortex - M processor: Simplified view block

diagram, programming model – Registers,
Operation modes, Exceptions and Interrupts, Reset
Sequence, Instruction Set, Pipeline, Bus, Priority,
Vector Tables, Interrupt Inputs and Pending
behavior, Fault Exceptions, Supervisor and
Pendable Service Call, Nested Vectored Interrupt
Controller.
 ARM Cortex Processor Series

• Cortex-M Series : For microcontrollers (low power, real-time control)

• Cortex-R Series : For real-time systems (e.g., automotive, robotics)

• Cortex-A Series : For application processors (e.g., smartphones, tablets)

• Neoverse : For infrastructure and cloud computing

• Apple Silicon (e.g., M1, M2) : Custom ARM-based processors for Macs

• Cortex-M0, Cortex-M0 , and Cortex-M1 processors only support a small

instruction set (56 instructions)

• Most of these instructions are 16 bit, thus provide a very good code
density which means it need a smaller program memory require for the
same task compared to many architecture.
ARM Processor family
Applications for various Cortex-M
Processors
 Quick Glance on the ARM Cortex-M0 and
Cortex-M0+ Processor
• Are 32-bit Reduced Instruction Set Computing (RISC) processor, based on an
architecture specification called ARMv6-M Architecture. The bus interface
and internal data paths are 32-bit width.

• Have 16 32-bit registers in the register bank (r0 to r15). However, some of
these registers have special purposes (e.g., R15 is the Program Counter, R14 is
a register called Link Register, and R13 is the Stack Pointer).

• The instruction set is a subset of the Thumb Instruction Set Architecture. Most
of the instructions are 16 bit to provide very high code density.

• Support up to 4 GB of address space. The address space is architecturally

divided into a number of regions.

• Based on Von Neumann bus architecture (although arguably the Cortex-M0 þ

processor have a hybrid bus architecture because of an optional separate bus
interface for fast peripheral register accesses
• Includes an interrupt controller called NVIC. The NVIC provides very
flexible and powerful interrupt management.

• The system bus interface is pipelined, based on a bus protocol called

Advanced High performance Bus (AHB ) Lite. The bus interface supports
transfers of 8-bit, 16-bit, and 32-bit data, and also allows wait states to be
inserted.

• Support various features for the OS (Operating System) implementation

such as a system tick timer, shadowed stack pointer, and dedicated
exceptions for OS operations.

• Includes various debug features to enable software developers to create

applications efficiently.

• Designed to be very easy to use. Almost everything can be programmed in

C and in most cases no need for special C language extension for data types
or interrupt handling support.

• Provide good performance in most general data processing and I/O

control applications.
Block diagram of the Cortex -M0 Processor
• The processor core contains the register banks, ALU, data path, and
control logic. It is a three-stage pipeline design with fetch stage, decode
stage, and execution stage.

• The register bank has sixteen 32-bit registers. A few of the registers in
the register bank have special usages (e.g., PC). The rest are available
for general data processing.

• The NVIC accepts up to 32 interrupt request signals and a NMI input. It

contains the functionality required for comparing priority between
interrupt requests and current priority level so that nested interrupts
can be handled automatically.

• If an interrupt is accepted, the NVIC communicates with the processor

so that the processor can execute the correct interrupt handler.

• The WIC is an optional unit. In low-power applications, the

microcontroller can enter standby state with most parts of the processor
powered down. Under this situation, the WIC can perform the function
of interrupt masking while the NVIC and the processor core are
inactive.
• The debug subsystem contains various functional blocks to handle
debug control, program breakpoints, and data watch points.

• When a debug event occurs, it can put the processor core in a halted
state so that embedded developers can examine the status of the
processor at that point.

• The internal bus system, data path in the processor core, and the
AHB-Lite bus interface are all 32-bit wide. AHB-Lite is an on-chip
bus protocol used in many ARM processors.

• This bus protocol is part of the AMBA (Advanced Microcontroller

Bus Architecture) specification, which is a bus architecture
developed by ARM and widely used in the IC design industry.

• The JTAG or Serial Wire interface units provide access to the bus
system and debugging functionalities.
A simple system with the Cortex -M0
Processor.
 Memory
Organization
Processor Registers
 MSP (Main Stack Pointer) – used by default
after reset and during interrupts
 PSP (Process Stack Pointer) – used by user
tasks in operating systems

 R14 is called the Link Register. It stores the

return address when a function is called.
Program status register APSR, EPSR, and
IPSR
• R0 to R3 – Low Registers (store Parameter and Return Registers)
• R4 to R7 – Low Registers (stores Local Variables and Temporary Data).
• R8 -R12 are called high registers. Stores intermediate results in large
programs.
• R13 is the Stack Pointer, and it points to the top of the stack in memory.
• In Cortex-M, there are two stack pointers: MSP (Main Stack Pointer) –
used by default after reset and during interrupts. PSP (Process Stack
Pointer) – used by user tasks in operating systems.
• R14 is called the Link Register. It stores the return address when a function
is called.
• R15 is the Program Counter. It always holds the address of the next
instruction to be executed.
• xPSR – Program Status Register. xPSR is a combination of: APSR
(Application PSR) IPSR (Interrupt PSR) EPSR (Execution PSR).
• PRIMASK is a 1-bit interrupt mask register. When PRIMASK = 1: All
maskable interrupts are disabled.
• BASEPRI is used to set priority threshold. It masks all interrupts with
priority equal to or lower than the value in BASEPRI.
• FAULTMASK is used to Disable all interrupts including HardFault.
• The CONTROL register controls Privileged or unprivileged mode and
Selection of MSP or PSP as stack pointer.
ARM Instruction Set
Architecture
ARM processors support mainly four different assembly instruction sets:
Thumb, Thumb-2, ARM32, and ARM64.

1) Thumb: The objective of the Thumb instruction set is to improve the

code density. Because an instruction in Thumb has only 16 bits in
length, the size of their executable files is small.

1) ARM32: Each instruction in ARM32 has 32 bits and provides more

coding flexibility than a Thumb instruction. More operand options,
more flexible memory addressing schemes, larger immediate numbers,
and more addressable registers can be encoded in a 32-bit word.

1) Thumb-2: It provides an outstanding compromise between ARM32

and Thumb. It optimizes the tradeoff between code density and
processor performance. It consists of 16-bit Thumb instructions and a
subset of 32-bit ARM32 instructions.

1) ARM64: ARM 64-bit processors are often used in desktops and

servers. These processors have a set of 64-bit assembly instructions.
• The Cortex-M0, Cortex-M0 +, and Cortex-M1 Processors are based on the ARMv6-M
Architecture, whereas the Cortex-M3, Cortex-M4, and the Cortex-M7 Processors are
based on the ARMv7-M Architecture.

• The Cortex-M0 and Cortex-M0+ Processors have the exact same instruction set and
similar programmer’s model (Cortex-M0+ Processor have optional support for
unprivileged execution level and MPU, whereas Cortex-M0 processor does not).

• However, they have different physical characteristics like instruction timing and
have different system features.

• The Cortex-M3 and Cortex-M4 Processors are based on the ARMv7-M architecture
and its Thumb -2 instruction set is a superset of the instruction set used in ARMv6-M.

• The programmer’s model is also similar to ARMv6-M. As a result, in most cases

software developed for the Cortex-M0 and Cortex-M0+ can run on the Cortex-M3
and Cortex-M4 Processors without changes, assuming the system has same memory
maps and peripherals.
 Going from C to Assembly
• C, like many other high-level programming languages, makes
powerful abstraction of computer hardware to hide from
programmers the details of how computation is implemented.
• High-level languages make program codes more concise, more
portable, and easier to develop and debug.
In general, there are three types of instruction set architecture (ISA)

1) Accumulator-based instruction set. One of the ALU source operands

is implicitly stored in a special register called accumulator, and the
ALU result is saved into the accumulator. The programmer does not
have to specify this operand and the destination register in the
program. The accumulator-based instruction set was popular in the
1950s.

2) Stack-based instruction set: All ALU operands are assumed to be on

top of the stack, and the ALU result is also placed on top of the stack.
The stack is a special region of memory. Thus, programmers need to
push the value of operands onto the stack before an ALU operation is
called. The stack-based instruction set was used in the 1960s.

3) Load-store instruction set: ALU source or destination operands can be

any general-purpose registers. ALU cannot directly use data stored in
memory as operands. ALU can only access data in memory by using
load or store instructions. Most modern processors are based on a
load-store instruction set.
Skeleton of program
• The AREA directive indicates to the assembler the start of a new data or
code section.

• The ENTRY directive marks the first instruction to be executed within an

application. There must be one and only one entry directive in an
application, no matter how many source files the application has.

• The END directive indicates the end of a source file. Each assembly
program file must end with this directive.

• PROC and ENDP mark the beginning and the end of a function (also called
a subroutine or procedure), respectively. PROC stands for "procedure" and
ENDP means "end of procedure."
 Arithmetic Instructions
S. No Mnemonic Instruction Format Description
1 ADD ADD Rd, Rn, Rm Rd = Rn + Rm
2 ADD ADD Rd, Rn, #imm Rd = Rn + immediate
3 ADC ADC Rd, Rn, Rm Rd = Rn + Rm + Carry
4 SUB SUB Rd, Rn, Rm Rd = Rn − Rm
5 SUB SUB Rd, Rn, #imm Rd = Rn − immediate
6 SBC SBC Rd, Rn, Rm Rd = Rn − Rm − (1 − Carry)
7 RSB RSB Rd, Rn, #0 Rd = 0 − Rn
8 MUL MUL Rd, Rn, Rm Rd = Rn × Rm

• Cortex-M0 does NOT have a division instruction.

• Division is performed using: Repeated subtraction and

Shift and subtract algorithms
• ADD R0, R1, R2 ; R0 = R1 + R2
• ADD R3, R3, #10 ; R3 = R3 + 10
• SUB R4, R5, R6 ; R4 = R5 − R6
• MUL R7, R0, R1 ; R7 = R0 × R1

• In Cortex-M0, RSB is available only with immediate #0.

• RSB R0, R1, #0
R0 = 0 − 25 = −25 if R1=25
 Logical Instructions
S. No Mnemonic Instruction Format Description
9 AND AND Rd, Rn, Rm Rd = Rn AND Rm
10 ORR ORR Rd, Rn, Rm Rd = Rn OR Rm
11 EOR EOR Rd, Rn, Rm Rd = Rn XOR Rm
12 BIC BIC Rd, Rn, Rm Rd = Rn AND NOT Rm
13 MVN MVN Rd, Rm Rd = NOT Rm
14 TST TST Rn, Rm Test bits (Rn AND Rm)
15 CMP CMP Rn, Rm Compare Rn with Rm
16 CMP CMP Rn, #imm Compare Rn with immediate
17 CMN CMN Rn, Rm Compare negative
• AND R0, R1, R2 ; R0 = R1 AND R2
• ORR R3, R3, R4 ; R3 = R3 OR R4
• EOR R5, R6, R7 ; R5 = R6 XOR R7
• MVN R0, R1 ; R0 = NOT R1
• CMP R0, R1 ; Compare R0 with R1
• CMP R2, #100 ; Compare R2 with immediate
• CMN R3, R4 ; Compare negative
• TST R5, R6 ; Bitwise test
• Rd = Rn AND (NOT Rm)
– BIC clears (sets to 0) the bits in Rn wherever the corresponding bit in Rm is 1.
R1 = 1101 1111
R2 = 0000 1111
R0 = 1101 0000
 Shift and Rotate
• There are five types of shift and rotate operations: LSL, LSR, ASR, ROR, and
RRX.

• LSL (logical shift left) moves all bits of a register value left by n bits and zeros
are shifted in at the right end. LSL is equivalent to multiplication by 2n .

• LSR (logical shift right) moves all bits of a register value right by n bits and
zeros are shifted in at the left end. LSR is equivalent to unsigned division by 2n .

• ASR (arithmetic shift right) moves all bits right by n bits and copies of the left
most bit (the sign bit) are shifted in at the left end. ASR is equivalent to signed
division by 2n .

• ROR (rotate right) is the circular shift, in which all 32 bits are shifted right
simultaneously as if the right end of the register is joined with its left end. The
bit shifted out from the right end of the register is copied into the carry bit. The
carry bit can be optionally used to update the carry flag of the processor status
register.

• RRX (rotate right with extend) works similarly to ROR except that the carry bit
joins the rotating circle, and RRX can rotate the data by only one bit.
S.
No Mnemonic Instruction Format Description
18 LSL LSL Rd, Rm, #imm Logical shift left
19 LSR LSR Rd, Rm, #imm Logical shift right
20 ASR ASR Rd, Rm, #imm Arithmetic shift right
21 ROR ROR Rd, Rm, #imm Rotate right

LSL R0, R1, #2 ; Logical left shift R1 by 2 → R0

LSR R2, R3, #1 ; Logical right shift R3 by 1
ASR R4, R5, #3 ; Arithmetic right shift
ROR R6, R7 ; Rotate R7 right by 1 → R6
Data Transfer (Load / Store) Instructions
Instructions
S. No Mnemonic Instruction Format Description
22 LDR LDR Rt, [Rn, #imm] Load word from memory
23 LDRB LDRB Rt, [Rn, #imm] Load byte from memory
24 LDRH LDRH Rt, [Rn, #imm] Load halfword from memory
25 LDRSB LDRSB Rt, [Rn, #imm] Load signed byte
26 LDRSH LDRSH Rt, [Rn, #imm] Load signed halfword
27 STR STR Rt, [Rn, #imm] Store word to memory
28 STRB STRB Rt, [Rn, #imm] Store byte to memory
29 STRH STRH Rt, [Rn, #imm] Store halfword to memory
30 LDM LDM Rn!, {Rlist} Load multiple registers
31 STM STM Rn!, {Rlist} Store multiple registers
32 PUSH PUSH {Rlist} Push registers to stack
33 POP POP {Rlist} Pop registers from stack
34 ADR ADR Rd, label Load address
35 REV REV Rd, Rm Reverse byte order
36 REV16 REV16 Rd, Rm Reverse bytes in halfwords
37 REVSH REVSH Rd, Rm Reverse signed halfword
38 SXTB SXTB Rd, Rm Sign extend byte
39 SXTH SXTH Rd, Rm Sign extend halfword
40 UXTB UXTB Rd, Rm Zero extend byte
41 UXTH UXTH Rd, Rm Zero extend halfword
LDR R0, [R1, #4] ; Load word from memory
STR R2, [R3, #0] ; Store word to memory
LDRB R4, [R5, #1] ; Load byte
STRH R6, [R7, #2] ; Store half word

PUSH {R4, R5, LR} ; Push registers onto stack

POP {R4, R5, PC} ; Pop registers from stack
LDM R0!, {R1, R2} ; Load multiple registers
STM R3!, {R4, R5} ; Store multiple registers
Branch and Control Instructions
S. No Mnemonic Instruction Format Description
42 B B label Unconditional branch
43 BL BL label Branch with link
44 BX BX Rm Branch and exchange
45 CBZ CBZ Rn, label Branch if zero
46 CBNZ CBNZ Rn, label Branch if not zero
47 IT IT cond If-Then conditional block

B LOOP ; Unconditional branch

BL FUNC ; Branch with link (function call)
BX LR ; Return from function
CBZ R0, EXIT ; Branch if R0 == 0
 System Instructions
S. No Mnemonic Instruction Format Description
48 NOP NOP No operation
49 BKPT BKPT #imm Breakpoint
50 SVC SVC #imm Supervisor call
51 CPS CPSIE / CPSID Enable/disable interrupts
52 MRS MRS Rd, special_reg Move from special register
53 MSR MSR special_reg, Rn Move to special register
54 SEV SEV Send event
55 WFE WFE Wait for event
56 WFI WFI Wait for interrupt

NOP ; No operation
WFI ; Wait for interrupt (low power)
SVC #0 ; Supervisor call
BKPT #1 ; Breakpoint for debugger
Operation modes of CORTEX M0
 An M-profile processor supports two operating modes:

1) Thread Mode
• This is the normal execution mode for application code.
• All user tasks, main program, and non-exception functions run in this
mode.
• Thread mode can execute in either privileged or unprivileged state:
• Privileged Thread Mode: Can access all processor resources and system
registers.
• Unprivileged Thread Mode: Limited access, cannot execute privileged
instructions or access certain system registers.
• Code in thread mode can trigger exceptions (like SVC) to request privileged
services.
2) Handler Mode
• This mode is entered automatically when an exception or interrupt occurs.
• Cortex-M0 saves minimal context (R0–R3, LR, PC, xPSR) to handle the
exception efficiently.
• All exception handlers, including SVC, PendSV, SysTick, and external
interrupts, execute in this mode.
• Handler mode always runs in privileged state, allowing full access to
system resources.
 Exception And Interrupts
• An interrupt leverages a combination of software and hardware to force the
processor to stop its current activity and begin to execute a particular piece
of code called an interrupt service routine (ISR).

• An ISR responds to a specific event generated by either hardware or

software. When an ISR completes, the processor automatically resumes the
activity that. An interrupt is simply a hardware-invoked function call had
been halted.

• Interrupts also allow a processor to perform multiple tasks simultaneously.

At any given time, the microcontroller is serving only one program activity.

• However, interrupts enable the processor to serve multiple computation

tasks alternately in a multiplexing fashion.

• In Cortex-M0, interrupts are treated as a type of exception. The processor

uses a fixed exception model that ensures fast and deterministic response.
1) Normal Program Execution
– Cortex-M0 executes instructions in Thread Mode using the current stack pointer.

2) Interrupt / Exception Occurs

– An interrupt request (IRQ), NMI, or HardFault is asserted.

3) Instruction Completion
– The processor completes the currently executing instruction before servicing the
interrupt.

4) Automatic Context Saving (Stacking)

– Hardware automatically pushes the following registers onto the stack:
• R0, R1, R2, R3
• R12
• LR
• PC
• xPSR

5) Stack Pointer Selection

– Cortex-M0 switches to Main Stack Pointer (MSP).
– Handler mode always uses MSP.
6) Mode Switching
– Processor switches from Thread Mode to Handler Mode.
– Handler mode is always privileged.

7) Vector Table Access

– Processor reads the ISR address from the vector table.

8) ISR Execution
– The corresponding Interrupt Service Routine starts execution.

9) Interrupt Exit
– ISR ends with BX LR, where LR contains EXC_RETURN value.

10) Automatic Context Restoration (Unstacking)

– Saved registers are popped from the stack automatically.

11) Return to Thread Mode

– Execution resumes from the interrupted instruction.
1. Vector Table Location
Located at address 0x00000000 (by default).

2. Initial Stack Pointer

Address 0x00000000 holds the initial MSP value.
Loaded immediately after reset.

3. Reset Handler
Address 0x00000004 contains the address of the Reset Handler.
First code executed after power-on or reset.

4. NMI Handler
Address 0x00000008 contains the Non-Maskable Interrupt handler.
Highest priority interrupt.

5. HardFault Handler
Address 0x0000000C stores the HardFault handler address.
Cortex-M0 supports only HardFault (no MemFault, BusFault).
6) External Interrupts (IRQs)
Start from address 0x00000040.
Each IRQ has a fixed offset of 4 bytes.

7) IRQ Handler Mapping

IRQ0 → 0x00000040
IRQ1 → 0x00000044
IRQ2 → 0x00000048
… up to the last supported IRQ.

8) Vector Entries
Each vector entry stores only the handler address, not instructions.

9) Direct ISR Jump

On interrupt, Cortex-M0 directly loads PC from the vector table.
No polling or software branching required.
 Interrupt Inputs and Pending behavior
• Interrupt inputs are external signals from peripherals that request CPU
attention.

• Interrupt Sources
– Generated by on-chip peripherals such as:
• Timers
• UART
• GPIO
• ADC, SPI, etc.
• IRQ Lines
– Each peripheral connects to the processor via an IRQ line.
– IRQs are numbered as IRQ0, IRQ1, IRQ2, …
• Connection to NVIC
– All IRQ inputs are connected to the Nested Vectored Interrupt Controller
(NVIC).
• NVIC handles:
– Interrupt enable/disable
– Priority selection
– Pending status
• Edge- or Level-Sensitive Inputs
– Interrupt inputs can be:
– Level-sensitive (active high/low)
– Edge-triggered (rising or falling edge)
– Configuration is MCU-specific.
• Synchronization
– External interrupt inputs are synchronized to the processor clock before being processed.

• An interrupt becomes pending when it has been requested but not yet serviced.
• An interrupt is pending when the request is registered by NVIC but execution has
not yet jumped to its ISR.

• An interrupt enters pending state when:

1. IRQ signal becomes active
2. Interrupt is enabled
3. Higher-priority interrupt is currently executing or
4. Interrupts are temporarily masked
• NVIC maintains pending status bits for each IRQ.
• Once pending, Interrupt waits until it is allowed to execute.
 Supervisor and Pendable
Service Call
Supervisor Call (SVC)

 The Supervisor Call (SVC) is used in ARM Cortex-M0 to switch

from unprivileged mode to privileged mode, or to request
operating system services. Essentially, it’s a way for user code to
ask the system (or OS) to perform tasks that require higher
privileges.

• Executed via the SVC instruction (previously called SWI in older

ARM architectures).

• Generates an SVC exception, which triggers the SVC handler in the

vector table.

• The processor automatically switches to Handler mode, saves

context, and jumps to the SVC ISR (Interrupt Service Routine).
Pendable Service Call (PendSV)

• PendSV is a special exception designed for context switching in

operating systems. It is pendable, meaning it can be delayed until
all higher-priority exceptions are handled.

• Triggered by setting the PENDSVSET bit in the ICSR register

(SCB->ICSR).

• Used by the RTOS scheduler to switch tasks without interfering

with higher-priority interrupts.

• Has lowest priority by default, ensuring it runs after all active

interrupts complete.
• Normal Execution in User Mode:
• The processor executes regular application code in thread mode.
• Supervisor Call (SVC) Instruction:
• User code triggers an SVC instruction to request a privileged operation or OS service.
• SVC Handler Execution:
• The processor switches to handler mode.
• The SVC Handler executes, performing privileged operations or OS routines.
• Interrupt Occurrence (IRQ):
• High-priority interrupts can preempt normal execution or the SVC handler.
• The corresponding Interrupt Service Routine (ISR) handles the interrupt.
• Scheduler Decision:
• After handling interrupts, the scheduler may determine that a task switch is required.
• PendSV Request Generation:
• The scheduler sets the PENDSVSET bit in the system control register to trigger PendSV.
• PendSV is pendable, meaning it executes only after all higher-priority interrupts are
completed.
• PendSV Handler Execution:
• PendSV performs the context switch, saving the current task context and loading the
next task’s context.
• Return to Thread Mode:
• After all exception handling and context switching, the processor returns to thread mode.
• The next task resumes execution, completing the multitasking cycle.
 Nested Vectored Interrupt Controller

 The Nested Vectored Interrupt Controller (NVIC) is a hardware component in ARM

Cortex-M processors, including the Cortex-M0, that manages interrupts efficiently.
 It is tightly integrated with the processor to handle multiple interrupt sources with
minimal software overhead.
• NVIC allows the processor to:
• Prioritize interrupts
• Handle nested interrupts (higher-priority interrupts can preempt lower-priority
ones)
• Vector directly to the appropriate interrupt service routine (ISR)
• Support low-latency interrupt response, which is critical for real-time
applications.

• Key Registers in NVIC (Cortex-M0)

• ISER (Interrupt Set-Enable Register): Enables specific interrupts.
• ICER (Interrupt Clear-Enable Register): Disables interrupts.
• ISPR (Interrupt Set-Pending Register): Sets interrupts as pending.
• ICPR (Interrupt Clear-Pending Register): Clears pending interrupts.
• IPR (Interrupt Priority Register): Assigns priority levels.
• Interrupt Occurs:
• An event from external IRQs (e.g., GPIO, Timer, UART) or
internal exceptions triggers an interrupt.
• The interrupt is signaled to the NVIC.
• NVIC Checks Pending Status:
• NVIC sets the interrupt as pending in the Pending Register.
• The NVIC also checks if the interrupt is already active or
blocked by a higher-priority interrupt.
• Priority Evaluation:
• NVIC compares the priority level of the pending interrupt with
currently active interrupts using the Priority Registers.
• Only higher-priority interrupts can preempt lower-priority ISRs.
• Vectoring to ISR:
• Once the NVIC selects the interrupt to handle, it fetches the ISR
address from the Vector Table.
• The processor automatically saves context (R0–R3, LR, PC,
xPSR) and jumps to the ISR.
• Interrupt Service Routine (ISR) Execution:
• The ISR executes the required service (e.g., reading GPIO,
handling UART data).
• The NVIC maintains the interrupt as active during ISR
execution.
• Return from ISR:
• After ISR execution, the processor restores the saved context.
• The NVIC clears the active status of the interrupt.
• Pending Interrupts Check:
• NVIC checks for any other pending interrupts.
• If there are lower-priority pending interrupts, they will execute
in order of priority.
• This ensures nested interrupts are handled efficiently.
• Resume Normal Execution:
• Once all pending and active interrupts are serviced, the
processor returns to thread mode, resuming the previous task or
user code.