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Risc & Cisc

RISC (Reduced Instruction Set Computer) is a computer architecture that utilizes a small set of simple instructions for fast execution, typically within a single clock cycle, emphasizing speed and efficiency. In contrast, CISC (Complex Instruction Set Computer) employs a large set of complex instructions that can perform multiple operations, often taking multiple clock cycles to execute, aiming to reduce the number of instructions per program. Both architectures have distinct characteristics, with RISC focusing on simplicity and performance, while CISC prioritizes functionality and memory efficiency.

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11 views3 pages

Risc & Cisc

RISC (Reduced Instruction Set Computer) is a computer architecture that utilizes a small set of simple instructions for fast execution, typically within a single clock cycle, emphasizing speed and efficiency. In contrast, CISC (Complex Instruction Set Computer) employs a large set of complex instructions that can perform multiple operations, often taking multiple clock cycles to execute, aiming to reduce the number of instructions per program. Both architectures have distinct characteristics, with RISC focusing on simplicity and performance, while CISC prioritizes functionality and memory efficiency.

Uploaded by

Bhola Singh
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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RISC (Reduced Instruction Set Computer) – Definition

RISC is a computer architecture that uses a small and highly optimized set of simple instructions,
each designed to execute very quickly — typically within a single clock cycle.
The main idea is to simplify the instruction set so that the hardware can execute instructions faster
and enable efficient pipelining.

Key points:

• Emphasizes speed and efficiency.

• Each instruction performs a simple operation.

• Most operations are performed using registers.

• Common in modern processors like ARM, MIPS, and RISC-V.

Example: ARM processors used in smartphones follow the RISC architecture.

Characteristic of RISC:

• Simpler instruction, hence simple instruction decoding.

• Instruction come under size of one word.

• Instruction take single clock cycle to get executed.

• More number of general-purpose register.

• Simple Addressing Modes.

• Less Data types.

• Pipeline can be achieved.


CISC (Complex Instruction Set Computer) – Definition

CISC is a computer architecture that uses a large and complex set of instructions, where each
instruction can perform multiple low-level operations (such as load, computation, and store) within
a single instruction.
The goal is to reduce the number of instructions per program, making assembly programming
easier and minimizing memory usage.

Key points:

• Emphasizes doing more with fewer instructions.

• Each instruction can take multiple clock cycles to execute.

• Uses many addressing modes and complex instruction formats.

• Common in traditional desktop processors like Intel x86 and AMD.

Example: Intel Core i7 processors use the CISC architecture.

Characteristic of CISC:

• Complex instruction, hence complex instruction decoding.

• Instruction are larger than one word size.

• Instruction may take more than single clock cycle to get executed.

• Less number of general-purpose register as operation get performed in memory itself.

• Complex Addressing Modes.

• More Data types.


RISC (Reduced Instruction Set
Feature CISC (Complex Instruction Set Computer)
Computer)

Full Form Reduced Instruction Set Computer Complex Instruction Set Computer

Instruction Set Small and simple instruction set Large and complex instruction set

Instruction
All instructions are of fixed length Instructions are of variable length
Length

Each instruction takes one clock


Execution Time Instructions may take multiple clock cycles
cycle (usually)

High performance due to pipeline


Performance Slower due to complex instructions
and simplicity

Requires more memory for storing Requires less memory as single instruction
Memory Usage
more instructions can perform multiple tasks

Addressing
Few addressing modes Many addressing modes
Modes

Instruction
Simple and fast Complex and slower
Decoding

Use of Registers Uses more registers for operations Uses memory more frequently

Hardware
Simple hardware Complex hardware
Complexity

Easy to implement due to uniform Difficult to implement due to variable


Pipelining
instruction size instruction size

Example
ARM, MIPS, SPARC, RISC-V Intel x86, AMD, VAX, Motorola 68k
Processors

Focus Software (compiler optimization) Hardware (complex instruction handling)

Instruction One instruction per cycle One instruction performs multiple low-level
Execution (load/store architecture) operations

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