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Interrupt Controller

The 8259 Programmable Interrupt Controller (PIC) is essential for managing multiple hardware interrupts from microprocessors, allowing for the handling of up to 8 interrupts with priority resolution. It accepts interrupt requests from peripheral devices, determines their priority, and issues interrupts to the CPU while providing the location of the corresponding service routines. The PIC features include individual interrupt masking, status reading of interrupts, and the ability to cascade multiple controllers for expanded interrupt management.

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18 views11 pages

Interrupt Controller

The 8259 Programmable Interrupt Controller (PIC) is essential for managing multiple hardware interrupts from microprocessors, allowing for the handling of up to 8 interrupts with priority resolution. It accepts interrupt requests from peripheral devices, determines their priority, and issues interrupts to the CPU while providing the location of the corresponding service routines. The PIC features include individual interrupt masking, status reading of interrupts, and the ability to cascade multiple controllers for expanded interrupt management.

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Kavida A
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© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

PROGRAMMABLE INTERRUPT

CONTROLLER(8259)
Need for 8259 PIC
 Microprocessor has 5 hardware
interrupts(TRAP, RST7.5, RST6.5, RST 5.5,
INTR)
 PIC is needed to interface more number of
interrupts
 PIC manages 8 interrupts and services the
interrupts one by one depending upon the
priority.
 More than 8 interrupts can be managed by
using CAS lines of PIC
Programmable Interrupt Controller
(8259)
 Accepts interrupt requests from peripheral devices
 Determines which of the request is of highest priority
 Checks whether the incoming request has highest
priority than the level being currently serviced.
 Issues an interrupt to the CPU based on this
determination
 Each peripheral device has a special programme
(routine) that is referred to as service routine
 The PIC after issuing interrupt to CPU must provide
information into CPU about the location of service
routine of the specific peripheral device.
Programmable Interrupt Controller
(8259)
Features of PIC:
 Handle eight interrupt inputs.
 This is equivalent to providing eight interrupt pins on
the processor in place of one INTR/INT pin.
 Vector an interrupt request anywhere in the memory
map.
 Resolve eight levels of interrupt priorities in a variety of
modes.
Programmable Interrupt Controller
(8259)
Features of PIC:
 Mask each interrupt request individually.
 Read the status of pending interrupts, in service
interrupts, and masked interrupts.
 Be set up to accept either the level triggered or edge
triggered interrupt request.
 Nine 8259 as can be cascade in a master slave
configuration to handle 64 interrupt inputs
Programmable Interrupt Controller
(8259)
Programmable Interrupt Controller
(8259)
Programmable Interrupt Controller
(8259)
IRR(Interrupt Request Register):
 Stores all interrupts which requires
service.
 Keep track of which interrupts are asking
for service
 If an interrupt input has an interrupt
signal on it the corresponding bit in the
IRR will be set
Programmable Interrupt Controller
(8259)
Interrupt Mask Register(IMR):
 IMR is used to mask (disable) or unmask
(enable) individual interrupt inputs.
 IMR operates on IRR
 Masking of highest priority interrupt will
not affect other interrupt requests
 To unmask any interrupt the
corresponding bit is set as 0
Programmable Interrupt Controller
(8259)
In-service Register(ISR):
 Keeps track of which interrupts inputs are
currently being serviced.
 For each input that is currently being
serviced the corresponding bit will be set
in the in-service register.
Programmable Interrupt Controller
(8259)
Priority Resolver(PR):
 Determine the priorities of the bits set at
IRR.
 The highest priority is selected and
strobed into the corresponding bit of ISR
during pulse

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