Chapter 3
Programmable Logic Devices
Section: 9.3, 9.5, 9.6, 9.7, 9.8
3.1. Introduction
This chapter discusses:
Three-State Buffers
Read-Only Memory (ROM
Programmable Logic Devices (PLA, PAL)
Complex Programmable Logic Devices (CPLD)
Field Programmable Gate Array (FPGA)
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3.2. Three State Buffer
A gate output can only be connected to a limited
number of other device inputs without degrading
the performance of a digital system.
A simple buffer may be used to increase the
driving capability of a gate output.
3.2. Three State Buffer
The logical equivalent of the three-state buffer:
When the enable input B is 1, the output C equals A.
When B is 0, the output C acts like an open circuit.
The output C is effectively disconnected from the
buffer output so that no current can flow.
This is often referred to as a Hi-Z (high-impedance)
state of the output.
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3.2. Three State Buffer
Different types of Three (Tri) State Buffer:
3.3. Read-Only Memory (ROM)
A read-only memory (ROM) consists of an array of
semiconductor devices that are interconnected to
store an array of binary data.
Once binary data is stored in the ROM, it can be read
out whenever desired, but the data that is stored
cannot be changed under normal operating
conditions. 6
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3.3. Read-Only Memory (ROM)
Example: Implement Four three-input Functions.
3.3. Read-Only Memory (ROM)
A ROM basically consists of a decoder and a memory array.
When a pattern of n 0’s and 1’s is applied to the decoder
inputs, exactly one of the 2n decoder outputs is 1.
This decoder output line selects one of the words in the
memory array, and the bit pattern stored in this word is
transferred to the memory output lines.
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3.3. Read-Only Memory (ROM)
Example 1: Implement Four three-input Functions.
3.3. Read-Only Memory (ROM)
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3.3. Read-Only Memory (ROM)
Example 2:
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3.3. Read-Only Memory (ROM)
Example 2:
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3.4. Programmable Logic Arrays
A PLA with n inputs and m outputs can realize m
functions of n variables.
It implements sum-of-product.
AND array and OR array are programmable.
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3.4. Programmable Logic Arrays
Example 1: Implement Four three-input Functions.
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3.4. Programmable Logic Arrays
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3.4. Programmable Logic Arrays
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3.4. Programmable Logic Arrays
Example 2: Implement the following functions.
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3.5. Programmable Array Logic
The PAL (programmable array logic) is a special case
of the PLA in which the AND array is programmable
and the OR array is fixed.
The PAL is less expensive than the PLA.
The PAL is easier to program.
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3.5. Programmable Array Logic
Example: Implement Full-adder using PAL
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3.6. Complex Programmable
Logic Devices (CPLD)
Instead of a single PAL or PLA on a chip, many
PALs or PLAs can be placed on a single CPLD chip
and interconnected.
When storage elements such as flip-flops are also
included on the same IC, a small digital system can
be implemented with a single CPLD.
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3.6. Complex Programmable
Logic Devices (CPLD)
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3.6. Complex Programmable
Logic Devices (CPLD)
The basic architecture of a Xilinx XCR3064XL CPLD.
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3.6. Complex Programmable
Logic Devices (CPLD)
The basic architecture of a Xilinx XCR3064XL CPLD
Four function blocks, and each block has 16 associated
macrocells (MC1, MC2, . . .).
Each function block is a programmable AND-OR array that is
configured as a PLA.
Each macrocell contains a flip-flop and multiplexers that route
signals from the function block to the input-output (I/O) block or
to the interconnect array (IA).
The IA selects signals from the macrocell outputs or I/O blocks
and connects them back to function block inputs. Thus, a signal
generated in one function block can be used as an input to any
other function block.
The I/O blocks provide an interface between the bi-directional I/O
pins on the IC and the interior of the CPLD 23
3.6. Complex Programmable
Logic Devices (CPLD)
The basic architecture of a Xilinx XCR3064XL
CPLD.
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3.7. Field Programmable Logic
Array (FPGA)
An FPGA is an IC that contains an array of identical
logic cells with programmable interconnections.
The user can program the functions realized by each
logic cell and the connections between the cells.
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3.7. Field Programmable Logic
Array (FPGA)
The interior of the FPGA consists of an array of logic
cells, also called configurable logic blocks (CLBs).
The array of CLBs is surrounded by a ring of input-
output interface blocks.
These I/O blocks connect the CLB signals to IC pins.
The space between the CLBs is used to route
connections between the CLB outputs and inputs.
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3.7. Field Programmable Logic
Array (FPGA)
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3.7. Field Programmable Logic
Array (FPGA)
Simplified CLB
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3.7. Field Programmable Logic
Array (FPGA)
This CLB contains two function generators, two flip-flops,
and various multiplexers for routing signals within the CLB.
The H multiplexer selects either F or G depending on the
value of H1.
The CLB has two combinational outputs (X and Y) and two
flip-flop outputs (XQ and YQ).
The X and Y outputs and the flip-flop inputs are selected by
programmable multiplexers.
The select inputs to these MUXes are programmed when the
FPGA is configured.
For example, the X output can come from the F function
generator, and the Y output from the H multiplexer.
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3.7. Field Programmable Logic
Array (FPGA)
Each function generator has four inputs and can
implement any function of up to four variables.
The function generators are implemented as lookup
tables (LUTs).
A four-input LUT is essentially a reprogrammable
ROM with 16 1-bit words.
This ROM stores the truth table for the function
being generated.
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3.7. Field Programmable Logic
Array (FPGA)
Implementation of LUT
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3.7. Field Programmable Logic
Array (FPGA)
A section of a programmed FPGA
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