Tech 408 Notes

Chapter 7– Field-Effect Transistors (FETs)

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VII. Field-Effect Transistors (FETs)

7.0 Introduction
– FETs are unipolar devices.
– Only one type of carrier is used per transistor (either holes or electrons).
– Two main types:
i) Junction field-effect transistor (JFET).
ii) Metal oxide field-effect transistor (MOSFET).
– While the BJT is a current-controlled device (base current controls the collector
current), the FET is a voltage-controlled device (voltage between two of the
terminals controls the current through the device).
– FETs have very high input resistance.

7.1 The Junction Field-Effect Transistor (JFET)

– The JFET is a type of FET that operates with a reverse-biased pn junction.
– The pn junction controls current in a channel.
– If the channel may be either of n or p type material.
– It has three leads:
i) Drain
ii) Gate
iii) Source

– In the n-channel JFET, the gate is connected to both p regions.

– In the p-channel JFET, the gate is connected to both n regions.
– Only one gate lead is shown for simplicity.
– Let’s look at an n-channel JFET.
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Chapter 7– Field-Effect Transistors (FETs)
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– VDD provides a drain-to-source voltage, thus supplying a current from the drain to
the source.
– VGG sets the reverse-bias voltage between the gate and the source.
– Note that the gate-source pn junction should ALWAYS be reverse biased.
– The reverse biasing of the gate source junction produces a depletion region along
the pn junction.
– The depletion formed extends into the n channel.
– By increasing the depletion region, the width of the n channel becomes thinner.
– Making the channel thinner creates more resistance against current flow.
– Reverse-bias between the gate and the drain is larger than the reverse bias
between the gate and the source.

– The symbol for the JFET is:

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Chapter 7– Field-Effect Transistors (FETs)
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7.2 JFET Characteristics and Parameters

– The JFET is a voltage-controlled, constant-current device.
– To understand this, consider the case when the gate-to-source voltage is zero
(VGS=0).
– To get this, we need to short the gate to the source.
– As VDD increases, VDS increases as well.
– ID, the drain current, will also increase proportionally to increases in VDD.
– This increase in drain current is linear, because the depletion region is NOT large
enough to have significant effect.
– This is shown between points A and B.
– The region between points A and B is called the ohmic region.
– At point B, ID becomes essentially constant.
– This occurs because the reverse bias voltage from gate to drain (VGD) produces a
depletion region large enough to offset the increase in VDS.
– The offset is enough to keep ID constant.
– ID will remain constant until point C, where we reach breakdown.
– The region between points B and C is called the constant-current area.
– The drain-to-source (VDS) voltage at point B is called the pinch-off voltage (VP).
– The graph below has the ordinate labeled IDSS. This stands for drain-to-source
current with gate shorted).
– Both the VP and IDSS values are specified in data sheets.
– IDSS is the maximum drain current that a given JFET can produce, regardless of
the external circuit. It is always specified for the condition VGS = 0.
– Increasing VDS too much will cause the device to enter the breakdown region.
– This will damage the device, thus a JFET should never be operated in the
breakdown region.

– Connecting a bias voltage, VGG, to the gate produces a family of curves as shown
next.
– Notices that ID decreases as VGS is made more negative.
– This occurs because the channel is narrowing.
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Chapter 7– Field-Effect Transistors (FETs)
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– Also notice that pinch-off occurs at different VP’s for different VGS values.
– Thus, the drain current is controlled by VGS.

– The value of VGS that makes ID approximately zero is called the cutoff voltage,
VGS(off).
– Note that the value of VGS that sets ID to zero (i.e. widening the depletion region
to a point where the channel is completely closed) is the most negative value VGS
can take
– The operation of a p-channel is the same as the n-channel, but requires a negative
VDD and a positive VGS.

Relation between Pinch-Off and Cutoff voltages

– VP is the value of VDS at which the drain current becomes constant.
– It is always measured at VGS = 0.
– Pinch-off occurs for VDS values less than VP, when VGS is nonzero.
– So, although VP is a constant, the minimum value of VDS at which ID becomes
constant varies with VGS.
– VGS(off) and VP are always equal in magnitude, but opposite in sign.
– Thus, knowing one, we have the other.
– Data sheets will generally list only one of the two.
– For example, if VGS(off) = -5 V, then VP = +5 V.

Example
Determine the minimum vale of VDD required to put the JFET below in the constant-
current region of operation.
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Solution
Since VGS(off) = –4 V, VP = 4 V. The minimum value of VDS for the JFET to enter the
constant current region is
VDS = VP = 4 V

In the constant current area with VGS = 0 V,

ID = IDSS = 12 mA

The drop across the drain resistor is

VR(D) = IDRD = (12 mA)(560 Ω) = 6.72 V

Using KVL around the drain circuit

VDD = VDS + VR(D) = 4 V + 6.72 V = 10.72 V

Thus, VDD must be 10.72 V for the device to enter the constant current area, i.e. to
make VDS = VP.

Example
A particular p-channel JFET has a VGS(off) = +4 V. What is ID when VGS = +6 V?

Solution
Recall a p-channel JFET requires a positive gate-to-source voltage. The more
positive VGS, the less the drain current. When VGS = 4 V, ID = 0 (cutoff). Any further
increase in VGS keeps the JFET cut off, so ID remains at 0.

JFET Transfer Characteristic

– A range of VGS values between 0 and VGS(off) controls the drain current.
– For an n channel JFET, VGS(off) is negative.
– For a p channel JFET, VGS(off) is positive.
– The relation between VGS and ID is shown below:

– The voltage ranges from VGS = VGS(off) to zero.

– The current ranges from 0 to IDSS.
– The curve shows the operational limits of the transistor.
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Chapter 7– Field-Effect Transistors (FETs)
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– The characteristic curve is taken from the ID vs. VDS curve.

– The equation for the JFET characteristic curve is:

ID = IDSS(1 – VGS/VGS(off))2

– Thus, if IDSS and VGS(off) are known, ID can be determined for any VGS.
– Notice that the characteristic curve is parabolic.
– Because of this, JFET and MOSFET are often referred to as square-law devices.

Example
Determine the drain current for VGS = 0 V, -1 V and –4 V for a 2N5459 JFET.

Looking at the data sheet we find that IDSS = 9 mA and VGS(off) = -8 V(maximum).
Thus, we can say that for VGS = 0
ID = IDSS = 9mA

For VGS = –1 V we use the equation shown above:

ID = IDSS(1 – VGS/VGS(off))2
= (9 mA)(1 – (-1 V/-8 V))2
= 6.89 mA

For VGS = –4 V :
ID = IDSS(1 – VGS/VGS(off))2
= (9 mA)(1 – (-4 V/-8 V))2
= 2.25 mA
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Chapter 7– Field-Effect Transistors (FETs)
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JFET Forward Transconductance (gm, gfs, yfs)

– It is the change in drain current (∆ID) for a given change in gate-to-source voltage
(∆VGS).
gm = ∆ID/∆VGS
– It is used to calculate the voltage gain in an amplifier.
– Data sheets normally show the value of gm at VGS = 0 V (gm0).
– This value is enough to calculate it for all values of VGS:
gm = gm0(1 – VGS/VGS(off))

– If the gm0 value is not available, we can calculate it with

gm0 = 2 IDSS/|VGS(off)|
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Chapter 7– Field-Effect Transistors (FETs)
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Input Resistance
– Since the JFET operates with the gate-source junction reverse-biased, the input
resistance is very high.
– This is one advantage of JFET over BJTs.
– The input resistance can be calculated by:
RIN = |VGS/IGSS|

7.3 JFET Biasing

– Just as with the BJTs, we need to establish the right dc gate-to-source voltage to
get the desired value of drain current.
– We will study to biasing methods:
i) Self Bias
– Most common biasing method for JFETs.
– We need a negative VGS for an n channel JFET.
– We need a positiveVGS for a p channel JFET.
– We achieve that with the circuit shown below.
– The gate resistor, RG, does NOT affect the bias since there is almost no
drop across it.
– Thus, the gate remains at zero.
– RG is used to isolate an ac signal from ground in amplifier applications.

– Consider the n-channel JFET circuit.

– IS produces a voltage drop across RS.
– This makes the source positive with respect to ground.
– Since IS = ID and VG = 0, then VS = IDRS.
– Thus:
VGS = VG – VS = 0 – IDRS = – IDRS

– For the p-channel JFET, the current through RS produces a negative

voltage at the source.
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Chapter 7– Field-Effect Transistors (FETs)
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– This makes the gate positive with respect to the source.

– Thus IS = ID, and
VGS = +IDRS

– Consider again the n-channel transistor.

VD = VDD – IDRD

– Since VS = IDRS, the drain-to-source voltage is

VDS = VD – VS
= VDD – ID(RD + RS)

Example
Find VDS and VGS in the circuit shown below. For the particular JFET in this
circuit, the internal parameter values such as gm, VGS(off), and IDSS are such
that a drain current (ID) of approximately 5 mA is produced. Another JFET,
even of the same type, may not produce the same results when connected in
this circuit due to the variations in parameter values.

Solution
VS = IDRS = (5 mA)(220 Ω) = 1.1 V

VD = VDD – IDRD = 15 V – (5 mA)(1.0 kΩ) = 10 V

Thus,

VDS = VD – VS = 10 V – 1.1 V = 8.9 V

Since VG = 0 V:
VGS = VG – VS = 0 V – 1.1 V = –1.1 V
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Chapter 7– Field-Effect Transistors (FETs)
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Setting the Q-point of a Self-Biased JFET

– Determine ID for a desired value of VGS or viceversa.
– Then, calculate the value of RS by using:
RS = |VGS/ID|

Example
Determine the value of RS (at VGS = -5 V) required to self-bias an n-channel
JFET that has the transfer characteristic curve shown next.

Solution
From the graph, ID = 6.25 mA at VGS = - 5 V. Then
RS = |VGS/ID| = 5 V/6.25 mA = 800 Ω

Example
Determine the value of RS required to self-bias a p-channel JFET with
IDSS=25 mA and VGS(off) = 15 V. VGS is to be 5 V.

Solution
Use the square-law equation:
ID = IDSS(1 – VGS/VGS(off))2 = (25 mA)(1–5V/15V)2 = 11.1mA

Now determine RS:

RS = | VGS/ID| = 5 V/11.1 mA = 450 Ω

NOTE
– It is generally desirable to bias a JFET near the midpoint of its transfer
characteristic, that is, where ID = IDSS/2.
– At this point we allow the maximum amount of drain current swing
between IDSS and 0.
– It can be shown that we get approximately that value for ID when
VGS=VGS(off)/3.4.
– To select a drain voltage at midpoint (VD = VDD/2), select a value of RD to
produce the desired voltage drop.
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Graphical Analysis of a Self Biased JFET

– Consider the circuit shown below.

– From data sheet, plot the characteristic curve.

– To determine the Q-point of the circuit, find VGS at ID = 0.
VGS = -IDRS = (0)(470 Ω) = 0 V

– Now, using IDSS, calculate VGS when ID = IDSS:

VGS = -IDRS = -(10 mA)(470 Ω) = -4.7 V

– Draw a line connecting the two points.

– This line is the load line.
– Wherever the load line intersects the characteristic curve, we have the Q-
point of the circuit.
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Chapter 7– Field-Effect Transistors (FETs)
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ii) Voltage-Divider Bias

– Voltage at source needs to be more positive than voltage at gate to keep
the gate-source junction reverse biased.
– Source voltage is VS = ISRS.

– The voltage at the gate is:

VG = VDD(R2/(R2 + R1))

– Thus, VGS = VG - VS
– Combining these equations we get:
ID = (VG - VGS)/RS

Example
Determine ID and VGS for the FET with voltage-divider bias shown below.
For this particular FET, the internal parameters are such that VD ≅ 7 V.

Solution
ID = (VDD – VD)/RD = (12 V – 7 V)/3.3 kΩ = 1.52 mA
VS = IDRS = (1.52 mA)(2.2 kΩ) = 3.34 V
VG = R2/(R1+R2)VDD = (1 MΩ)/(7.8 MΩ) 12 V = 1.54 V
VGS = VG – VS = 1.54 V – 3.34 V =–1.8V
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Notes
– Transfer characteristics of a JFET can differ considerably from one device
to another.
– The slope of the dc load line is much milder in a voltage-divider bias
circuit than in a self-biased circuit.
– Thus, a voltage-divider bias is more stable.
– Note that by stable we mean that the dependency of ID on the range of Q
points is reduced.

7.4 The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)

– The MOSFET differs from the JFET in that it has no pn junctions.
– Instead, the gate of the MOSFET is insulated from the channel by a silicon
dioxide (SiO2) layer.
– There are two basic types of MOSFETs:
i) Depletion (D) MOSFETs.
ii) Enhancement (E) MOSFETs.

i) Depletion MOSFET.
– Drain and source are diffused into the substrate material and then connected
by a narrow channel adjacent to the insulated gate.
– The D MOSFET can operate both in the enhancement and depletion modes.
– Since the gate is insulated from the channel, either a positive or a negative
gate voltage can be applied.
– An n-channel MOSFET operates in depletion mode when a negative gate-to-
source voltage is applied.
– It operates in an enhancement mode when a positive gate-to-source voltage is

applied.
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– Let’s look at both modes:

a) Depletion mode.
– The gate and the channel can be seen as the parallel plates of a
capacitor.
– The silicon dioxide is dielectric, or insulating layer.
– With a negative gate voltage, the negative charges on the gate repel
conduction electrons from the channel, leaving positive ions in their
place.
– Thus, the n channel is depleted of some of its conducting electrons.
– Conductivity is decreased.
– The greater the negative voltage on the gate, the greater the depletion
of n channel electrons.
– At a sufficiently large gate-to-source voltage, VGS(off), the channel is
completely depleted and ID becomes zero.
– Just like the n-channel FET, the n-channel D-MOSFET conducts drain
current for gate-to-source voltages between VGS(off) and zero.

b) Enhancement mode.

ii) Enhancement MOSFET.

– Operates ONLY in the enhancement mode. It has no depletion mode.
– It has no actual channel.
– The substrate extends completely to the SiO2 layer.
– For the n channel device, a positive gate voltage above a threshold value
induces a channel by creating a thin layer of negative charges in the substrate
region adjacent to the SiO2 layer.
– Conductivity is enhanced by increasing the gate-to-source voltage.
– This pulls more electrons into the channel area.
– For any voltage below the threshold value, there is no channel.
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Chapter 7– Field-Effect Transistors (FETs)
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– The symbol for an E-MOSFET is shown next.

– The dashed line indicates the absence of a channel.

7.5 MOSFET Characteristics and Parameters

– Most of the characteristics of the JFET apply to the MOSFET.
– Let’s look at the E-MOSFET
– It requires a positive gate-to-source voltage.
– There is no drain current when VGS = 0.
– The E-MOSFET does not have a significant IDSS parameter, as do the JFET and
the D-MOSFET.
– Ideally, there is no drain current until VGS reaches a certain non-zero value called
the threshold voltage, VGS(th).

– The square law equation for the drain current, thus, becomes:
ID = K(VGS – VGS(th))2

– The constant K depends on the particular MOSFET.

– It can be found from the data sheet by looking at the specified value of ID, called
the on-state value or ID(on), at the given value of VGS.
– Substitute the two parameters into the equation above and solve for K.

Handling precautions!!
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– ALL MOS DEVICES ARE SUBJECT TO DAMAGE FROM

ELECTROSTATIC DISCHARGE (ESD).
– Since the gate of a MOSFET is insulated form the channel, the input resistance is
very high.
– The gate leakage current (IGSS) is in the pA range.
– The gate reverse current for a JFET is in the nA range.
– The input capacitance results from the insulated gate structure.
– Excess static charge can be accumulated because the input capacitance combines
with the very high input resistance.
– This can result in damaging the device.
– Precautions for handling a MOS device (such as a computer) include:
i) MOS devices should be shipped and stored in conductive foam.
ii) All instruments and metal benches used in assembly or testing should be
connected to earth ground (third prong on 110 V wall outlets).
iii) Assembler’s or handler’s wrist must be connected to earth ground with a
length of wire and a high value series resistor,
iv) Never remove a MOS device (or any other device, for that matter) from the
circuit while the power is on.
v) Do not apply signals to a MOS device while the dc power supply is off.
– Since most of us handle computers on a daily basis, and do not constantly carry a
wrist connection to ground, it is safe to discharge (i.e. touch a metal connected to
ground) before handling a computer.

7.6 E-MOSFET Biasing

– VGS must be greater than the threshold value VGS(th).
– Thus, zero bias cannot be used.
– We use either a voltage-divider or a drain-feedback bias arrangement.
– The goal is to make the gate voltage more positive than the source by an amount
exceeding VGS(th).

– The drain-feedback bias circuit has a negligible gate current.

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Chapter 7– Field-Effect Transistors (FETs)
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– Thus, there is no drop across RG.

– Thus, VGS = VDS.
– For the voltage-divider bias, we get:
VGS = R2/(R2 + R1)VDD

VDS = VDD - IDRD

Example
Determine VGS and VDS for the E-MOSFET circuit in figure below. Assume this
particular MOSFET has minimum values of ID(on) = 200 mA at VGS = 4 V and
VGS(th)=2 V.

Solution
Find K using the minimum value of ID(on).
K = ID(on)/(VGS – VGS(th))2 = 200 mA/(4 V – 2 V)2
= 50 mA/V2

Now calculate ID for VGS = 3.13 V.

ID = K(VGS - VGS(th))2 = (50 mA/V2(3.13 V – 2 V)2
= 63.8 mA

Finally, calculate VDS.

VDS = VDD – IDRD = 24 V – (63.8 mA)(200 Ω) = 11.2 V

Homework 7 (All from chapter 7 problems)

7: 6, 8, 14, 18, 22, 32, 34, 36, 38, 40.

Reading: Chapter 8 and 9