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Module 3

DIGITAL SYSTEM DESIGN USING VERILOG

B.E., VI Semester (Open Elective)
[As per Choice Based Credit System (CBCS) Scheme]
Course Code: 18EC644 CIE Marks: 40
Number of Lecture Hours/Week: 04 SEE Marks: 60
Total Number of Lecture Hours: 40 (08 Hrs per module) Exam Hours: 03
CREDITS – 03

MODULE 3
Syllabus:
Implementation Fabrics: Integrated Circuits, Programmable Logic Devices, Packaging and
Circuit boards, Interconnection and Signal integrity (Chap 6 of Text).

RBT Levels: L1, L2, L3

Text Book: Peter J. Ashenden, ― Digital Design: An Embedded Systems Approach Using
VERILOG, Elesvier, 2010.

Course Objectives:
This course will enable students to
 Understand the concepts of Verilog Language.
 Design the digital systems as an activity in a larger systems design context.
 Study the design and operation of semiconductor memories frequently used in application
specific digital system.
 Inspect how effectively IC‘s are embedded in package and assembled in PCB‘s for
different application.
 Design and diagnosis of processors and I/O controllers used in embedded systems.

Course Outcomes:
After studying this course, students will be able to:
 Construct the combinational circuits, using discrete gates and programmable logic
devices.
 Describe Verilog model for sequential circuits and test pattern generation.
 Design a semiconductor memory for specific chip design.
 Design embedded systems using small microcontrollers, larger CPUs/DSPs, or hard or
soft processor cores.
 Synthesize different types of processor and I/O controllers that are used in embedded
system.

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IMPLEMENTATION FABRICS
The hardware of a digital system is implemented using integrated circuits (ICs)
connected together on printed circuit boards (PCBs). In this module, the range of ICs that are
used for digital systems are described. Some of the important characteristics of ICs and PCBs
that give rise to constraints on the designs are also discussed.

1. Integrated Circuits
 Early digital systems were constructed using discrete switching components, such as
relays, vacuum tubes, and transistors.
 Invention of the integrated circuit is credited to Jack Kilby at Texas Instruments in
1958.
 The techniques were refined by several developers, and the market for ICs grew rapidly
during the 1960s.
 Rapid growth since then, and ongoing.
 The history of development of digital IC technology must be reviewed for two reasons –
1. To deal with legacy systems
 Legacy systems: Systems designed some time ago but that are still in
operation and needing maintenance
2. To understand technology evolution and trends

Integrated Circuit Manufacture

 Implementation fabrics for digital systems are based on integrated circuits (ICs), which
are manufactured on the surface of a wafer of pure crystalline silicon using a sequence of
photographic and chemical process steps.
 A number of identical rectangular ICs are manufactured together, and then broken apart
for individual packaging.
(i) Wafer preparation:
 A cylindrical ingot of silicon is formed (Figure 1, left) and then sawn into wafers less
than a millimeter thick and finely polished (Figure 1, right).
 Early wafers were 50mm in diameter. Now, chips can be manufactured on 300mm
diameter wafers. This allows more chips to be manufactured at once, and reduces the
waste at the edges.

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Figure 1 An ingot of crystalline silicon (left), and sawn wafers (right).

(ii) IC Manufacture - Processing:
 There are several kinds of processing steps that can be applied to selected areas of the
wafer, including –
o Ion implantation: Exposing the surface to plasma of impurity ions that diffuse
into the silicon, thus altering its electrical properties in controlled ways.
o Etching: Chemically eroding an underlying film of material that has been
deposited onto the surface. Films include insulating materials, such as silicon
dioxide; semiconducting materials, such as polycrystalline silicon (also known as
polysilicon); and conducting materials, such as aluminum and copper.

resist
mask
film
wafer
(a)
(b)

(c) (d) (e)

Figure 2 Steps in photolithographic etching: (a) the wafer and film coated with resist;
(b) exposure through a photomask; (c) the resist developed; (d) etching of the
underlying film; (e) the remaining resist stripped.

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 The key to selecting which areas are affected is photolithography, which means using a
photographic process to draw on the surface (see Figure 2, showing selective etching of a
film).
o The surface is coated with a thin layer of photoresist, a chemical whose resistance
to chemical reaction is changed by exposure to light.
o The surface is then exposed to light through a mask that has opaque and
transparent areas in the pattern of features to be drawn.
o The resist is then developed, dissolving either the exposed areas or the unexposed
areas, depending on the kind of resist.
o The areas that are now uncoated can be processed, and then the remaining resist is
stripped off.
 Manufacturing circuits requires several different masks to form the circuit layers, as
illustrated in Figure 3.
o MOS transistors are formed in the bottom layers with channel areas containing
diffused impurity ions and gates formed from polysilicon lines.
o Wiring is formed in higher layers using etched metal conductors.

Figure 3 Graphical representation of the layers of an IC.

 A complete wafer contains between a few hundred to a few thousand circuits, depending
on the individual circuit size, as shown in Figure 4.

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Figure 4 A complete wafer containing multiple ICs.

(iii) IC manufacture – Test & packaging:
 ICs formed on wafer (as shown in Figure 4) must be tested for defects.
o Small defects can be introduced into an individual IC by stray particles obscuring
light during photolithography, by impurities occurring in chemical process steps,
or by particles impinging on wafers during handling in the manufacturing process
 Since a whole wafer-lot of ICs is manufactured together, the cost of the discarded
defective ICs must be amortized over those that work.
 Larger ICs have an increased chance of being defective, so it is important for designers to
constrain IC area to reduce cost.
 After testing the ICs on a wafer, the wafer is broken into individual chips, which are then
packaged.
 Working chips are packaged and tested further

Exponential Trends in IC Manufacture

 Circuit size and complexity of IC depends on minimum feature size
o Minimum feature size depends on manufacturing process - Mask resolution,
wavelength of light
 Process nodes (ITRS Roadmap)
o 350nm (1995), 250nm (1998), 180nm (2000), 130nm (2002), 90nm (2004),
65nm (2007), 45nm (2010), 32nm (2013), 22nm (2016), 16nm (2019)
o Smaller feature size  denser, faster IC

ITRS = International Technology Roadmap for Semiconductors

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SSI and MSI Logic Families

 In 1964, TI (Texas Instruments) introduced 5400 & 7400 family of TTL (transistor-
transistor logic) ICs.
 The 5400 family components were manufactured for high-reliability military applications,
whereas the 7400 family components were for commercial and industrial applications.
 Other IC manufacturers also provided compatible components, thus making the 7400
family a de facto standard.
 Small-scale integrated (SSI) components - small number of circuit elements
Eg: 7400: 4 × NAND gate, 7427: 4 × NOR gate, 7474: 2 × D flip-flop etc.
 Medium-scale integrated (MSI) components - large number of circuit elements
Eg: 7490: 4-bit counter, 7494: 4-bit shift register etc.
 The boundary between SSI and MSI is somewhat arbitrary. For example, it’s not clear
whether a 7442 BCD decoder is SSI or MSI.
 Manufacturers developed alternative versions of the components with different internal
circuitry and correspondingly different electrical characteristics.
 Variations on electrical characteristics:
o 74L… : low power
o 74S… : Schottky diodes  fast switching
o 74LS… : compromise between speed and power
o 74ALS… : advances low-power Schottky
o 74F… : fast
 One of the problems with TTL circuits is that they use bipolar transistors, which have
relatively high power consumption, even when not switching.
 One of the earliest CMOS logic families was the 4000 family –
o Provided SSI and MSI functions
o Very lower power consumption
o Power supply range 3V – 15V
o Slower
o Logic levels incompatible with TTL components
 In the 1980s, manufacturers introduced a new family of CMOS logic components, the
74HC00 & 74AHC00 family that were compatible with TTL components.
o 74AHC00 family - Improved speed and electrical characteristics

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Large Scale Integration (LSI):

 During the 1970s, IC technology developed to the level of large-scale integration (LSI),
at which it became feasible to provide a small computer, a microprocessor, on a single IC.
 Embedded systems using microprocessors became more cost-effective in many
applications than systems constructed from SSI and MSI components.
 The 7400 family components (SSI/MSI) were then commonly used as glue logic, that is,
simple logic circuits for interconnecting LSI components.
 Later additions to 74xx… families oriented toward glue-logic and interfacing
E.g., multibit tristate drivers, registers
o Other families replaced by PLDs and ASICs

Example 1: Use the following components to design a 4-digit decimal counter with a 7-
segment LED display: two 74LS390 dual decade counters, four 74LS47 BCD to 7-segment
decoders, four 7-segment displays, plus any additional gates required.
Solution:

CP0 Q0
CP1 Q1
Q2
MR Q3

Figure 5 A symbol for each of the decade counters in a 74LS390 component.

 The 74LS390 component contains two counters, each as shown in Figure 5.
 Internally, the counter consists of a single-bit counter clocked on the falling edge of CP0,
and a 3-bit divide-by-five counter clocked on the falling edge of CP1.
 A decade (divide-by-ten) counter can be formed by using the single bit counter for the
least significant bit and connecting the Q0 output externally to the CP1 input.
 When Q0 changes from 1 to 0, it causes the more significant bits to count up.
 The MR input to the counter is a master reset input. When 1, it forces the counter outputs
to 0000.
We can cascade the 74LS390 decade counters together, using the outputs of each
decade to generate a clock for the next decade. The outputs of a given decade changing from
1001 (the binary code for 9) to 0000 should cause the next decade to count up. The only time
this occurs is when Q3 and Q0 of the given decade both change to 0, so we can use an AND
gate to generate the clock for the next decade, as shown in Figure 6.

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Figure 6 Four 74LS390 decade counters cascaded to make a 4-digit counter.

 The 74LS47 component is shown in Figure 7

 The inputs A through D are the BCD value, with A being the least significant bit and D
the most significant bit.
 The segment outputs a through g are active-low, allowing them to drive the cathodes of a
7-segment display.
 When the lamp test input, LT, is low, it turns all segments on
 The ripple-blank input (RBI) and ripple-blank output (RBO) are used to turn off
any leading zero digits in the displayed value.
 When the RBI input to a decoder is low and the BCD value is 0000, all of the segments
are turned off and RBO is driven low.
 We tie the RBI input of the most significant digit low, and chain the RBO of all digits to
the RBI of the next digit (except the least significant digit, which we always want to
display something).

A a
B b
C c
D d
e
f
LT g
RBI RBO

Figure 7 A symbol for the 74LS47 BCD to 7-segment decoder.

 The complete circuit for the counter with display is shown in Figure 8.
 The two 74LS390 components are connected as shown in Figure 6 using three AND gates.
o These gates can be implemented using three of the four AND gates in a 74LS08
component.

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 Each counter output drives a 74LS47 decoder, which in turn drives a 7-segment LED
display.
 The resistors are required to limit the current flowing in each segment LED.
 The value of the resistor depends on the required display brightness.
 If we assume 2mA is sufficient, that the decoder output has a low-level voltage of 0.4V at
2mA, and that the voltage drop across the segment LED is 1.6V, we need the resistor to
drop 5.0 - 1.6 - 0.4 = 3.0V at 2mA.
 Thus, a 3.0V / 2mA = 1.5kΩ resistor will suffice.
+V

CP CP0 Q0 A a
CP1 Q1 B b
Q2 C c
MR Q3 D d
e
+V f
LT g
RBI RBO

+V

CP0 Q0 A a
CP1 Q1 B b
Q2 C c
MR Q3 D d
e
+V f
LT g
RBI RBO

+V

CP0 Q0 A a
CP1 Q1 B b
Q2 C c
MR Q3 D d
e
+V f
LT g
RBI RBO

+V

CP0 Q0 A a
CP1 Q1 B b
Q2 C c
MR MR Q3 D d
e
+V f
LT g
RBI RBO

FIGURE 8 Complete circuit for the 4-digit counter with display.

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Application – Specific Integrated Circuits (ASICs)

 In 1980s, Very Large Scale Integration (VLSI) came to existence
o At that stage, it became clear that the industry would soon run out of superlatives
to prefix to ―LSI‖.
 VLSI now just means detailed IC design
 Application-specific integrated circuit, or ASIC, to refers to an IC manufactured for a
particular application.
o Enabled by CAD tools, foundry services
 ASICs may be designed for,
o A particular end product provided by one manufacturer
 Eg: A portable music player, a toy, an automobile, a piece of military
equipment, or an industrial machine.
o A range of related products in a market segment
 These kinds of ASIC are sometimes called application-specific standard
products, or ASSPs, since they are treated as a standard part within the
market segment, but are not of use outside that segment.
Eg: ICs for cell phones

ASIC Economics
 ASIC has lower unit cost than an FPGA
o But more design/verification effort
o Higher non-recurring engineering (NRE) cost
 Amortized over production run
o ASICs make sense only for high volumes
 There are two main design and manufacturing techniques for ASICs:
o Full custom
 Design each transistor and wire (detailed design)
 High NRE cost, but best performance & least area
 Suitable for high-volume products, such as CPUs and ICs for consumer
appliances.
o Standard cell
 Use basic components from a foundry’s library
 NRE cost is significantly reduced

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2. Programmable Logic Devices

 Programmable logic devices (PLDs) can be programmed after manufacture to have
different functions.
o Higher unit cost than ASIC
o But lower NRE Cost
o Ideal for low to medium product volumes
 SSI & MSI families and ASICs all have fixed functions.

Programmable Array Logic (PALs)

 One of the first successful families of PLDs was introduced in the late 1970s by
Monolithic Memories, Inc., and called programmable array logic (PAL) components.
 A simple representative component in the family is the PAL16L8, whose circuit is shown
in Figure 9.
 The component has 10 pins that are inputs, 2 pins that are outputs, and 6 pins that are both
inputs and outputs. This gives a total of 16 inputs and 8 outputs (hence the name ―16L8‖).
 The symbol at each input in Figure 9 represents a gate that is a combination of a buffer
and an inverter. Thus, the vertical signals carry all of the input signals and their negations.
 The area in the dashed box is the programmable AND array of the PAL.
 Each horizontal signal in the array represents a p-term of the inputs, suggested by the
AND-gate symbol at the end of the line.
 In the unprogrammed state, there is a wire called a fusible link, or fuse, at each
intersection of a vertical and horizontal signal wire, connecting those signal wires.
 The PAL component can be programmed by blowing some of the fuses to break their
connections, and leaving other fuses intact.
 Programming is done by a special programming instrument before the component is
inserted into the final system.

On the diagram of Figure 9, X at the intersection of a vertical and a horizontal signal to

represents an intact fuse. An intersection without an X means that the intersecting signals are
not connected. So, for example, the horizontal signal numbered 0 has connections to the
vertical signals numbered 24 and 31, which are the signals I8 and 10. Some of the p-terms
are connected to the enable control signals for the inverting tristate output drivers. Others
are connected to the 7-input OR gates. So, for each output, we can form the AND-OR-

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INVERT function of inputs, with up to 7 p-terms involved. In the circuit shown in Figure 9,
output O1 implements the function 1. 2+ 3. 10, with the output enabled by the condition
I8. 10.

Figure 9 The internal circuit of a PAL16L8 component.

 Other PAL components also include registers, allow implementing simple sequential
circuits.
 As an example, the output circuit of a PAL16R8 component is shown in Figure 10.
 The feedback from the register output to the programmable AND array is useful for
implementation of FSMs.
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Figure 10 Registered output circuit of a PAL16R8.

Designing with PALs:
 Useful even for simple circuits
o Single package solution lowers cost
 Describe function using Boolean equations
o In HDL, or simple language such as ABEL
o Synthesize to fuse map file used by programming instrument
o If design doesn’t fit
 Partition into multiple PALs or use a more complex PLD

Generic Array Logic (GALs):

 Generic array logic (GAL) components provide output logic macrocells (OLMCs) that
replace the combinations of OR gates, registers and tristate drivers in PAL output circuits.

Figure 11 Internal circuit organization of a GAL220V10 component.

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 Each OLMC includes circuit elements together with programmable multiplexers,

allowing the output functionality to be determined as part of programming the component.
 As an example, Figure 11 shows the internal circuit organization of the GAL22V10
component, now manufactured by Lattice Semiconductor Corporation, and Figure 12
shows the OLMC circuit for each section.

Figure 12 Output logic macrocell of a GAL22V10 component.

 The OLMC has p-term inputs from an AND array with the same organization as that of a
PAL component.
 The number of p-terms ranges from 8 for some sections to 16 for others.
 The output of the OR gate connects to a D flip-flop that has clock, asynchronous reset and
synchronous preset signals in common with other OLMCs in the component.
 The select inputs of the multiplexers are set by programming the component.
 The four-input multiplexer allows selection of registered or combinational output, either
inverting or noninverting.
 The two-input multiplexer allows either registered or combinational feedback, or, if the
output driver is in the high-impedance state, direct input from the component pin.
 By appropriate programming, a GAL component can emulate any of the PAL
components, including the PAL16L8 and PAL16R8 components.

Example 2: Design a priority encoder that has 16 inputs, I[0:15]; a four-bit encoded output,
Z[3:0]; and a valid output that is 1 when any input is 1. Input I[0] has the highest priority, and
I[15] the lowest priority. The design is to be implemented in a GAL22V10 component.
Solution: The Boolean equations for the encoder, expressed in Verilog, are

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assign win[0] = I[0];

assign win[1] = I[1] & ~I[0];
assign win[2] = I[2] & ~I[1] & ~I[0];
...
assign win[15] = I[15] & ~I[14] & ~I[13] & ... & ~I[0];

assign Z[3] = win[15] | win[14] | win[13] | win[12] | win[11] | win[10] | win[9] |

win[8];
assign Z[2] = win[15] | win[14] | win[13] | win[12] | win[7] | win[6] | win[5] | win[4];
assign Z[1] = win[15] | win[14] | win[11] | win[10] | win[7] | win[6] | win[3] | win[2];
assign Z[0] = win[15] | win[13] | win[11] | win[9] | win[7] | win[5] | win[3] | win[1];

assign valid = I[15] | I[14] | I[13] | ... | I[0];

 Each of the win elements can be implemented as a p-term in a row of the GAL AND
array.
 Each Z output is thus the OR of 8 p-terms.
 Since each OLMC in a GAL22V10 component has at least 8 p-term inputs, these
equations will fit in any of the sections.
 The valid output is the OR of 16 inputs, so it could fit in either of the two sections that
have 16 p-term inputs to the OLMC.
o Alternatively, rewrite the equation for valid using the DeMorgan law,
assign valid = ~(~I[15] & ~I[14] & ~I[13] & ... & ~I[0]);
o Now, use just one p-term.
o This allows the valid output to be placed in any section of the GAL component
rather than only in those sections that have 16 OR-gate inputs.

Complex PLDs (CPLDs)

 A CPLD incorporates multiple PAL structures, all interconnected by a programmable
network of wires, as shown in Figure 13.
 Each of the PAL structures consists of an AND array and a number of embedded
macrocells (M/Cs in the figure).
o The macrocells contain OR gates, mutiplexers and flip-flops, allowing choice
among combinational or registered connections to other elements within the

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component, with or without logical negation, choice of initialization for flip-flops,

and so on.
o They are essentially expanded forms of the simple macrocell shown in Figure 12,
but without the direct connections to external pins.
o Instead, the external pins are connected to an I/O block, which allows selection
among macrocell outputs to drive each pin.
 The network interconnecting the PAL structures allows each PAL to use feedback
connections from other PALs as well as inputs from external pins.

Figure 13 The internal organization of a CPLD.

 Modern CPLDs use SRAM cells to store configuration bits that control connections in
the AND-OR arrays and the select inputs of multiplexers.
 Configuration data is stored in nonvolatile flash RAM within the CPLD chip, and is
transferred into the SRAM when power is applied.
 CAD tools are used to synthesize a design from an HDL model and to map the design
to the resources provided by a CPLD.

Field-Programmable Gate Arrays (FPGAs)

 For large designs, mapping the circuit onto CPLD resources becomes very difficult and
results in inefficient use of the resources provided by the chip.
 Field-programmable gate arrays (FPGAs) consist of an array of logic blocks, memory
blocks and I/O blocks, and a programmable interconnection network.

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 FPGAs could be thought of as arrays of gates whose interconnection could be

programmed ―in the field‖, away from the factory where the chips were made, hence the
name.
 FPGAs include an array of logic blocks that can be programmed to implement simple
combinational or sequential logic functions; input/output (I/O) blocks that can be
programmed to be registered or nonregistered, as well as implementing various
specifications for voltage levels, loading and timing; embedded RAM blocks; and a
programmable interconnection network. (See Figure 14)
… …

IO IO IO IO … … IO IO

IO LB LB LB LB … … LB LB IO
RAM
IO LB LB LB LB … … LB LB IO

IO LB LB LB LB … … LB LB IO
RAM
IO LB LB LB LB … … LB LB IO
…

…
IO LB LB LB LB … … LB LB IO
RAM
IO LB LB LB LB … … LB LB IO

IO IO IO IO … … IO IO
… …

Figure 14 The internal organization of an FPGA consisting of logic blocks (LB),

input/output blocks (IO), embedded RAM blocks (RAM) and programmable
interconnections (shown in gray).
 In many FPGA components, the basic elements within logic blocks are small 1-bit-wide
asynchronous RAMs called lookup tables (LUTs).
o The LUT address inputs are connected to the inputs of the logic block.
o The content of an LUT determines the values of a Boolean function of the inputs.
o The logic blocks also contain one or more flipflops and various multiplexers and
other logic for selecting data sources and for connecting data to adjacent logic
blocks.
Figure 15 shows the circuit for a slice within a logic block of a Xilinx Spartan-II FPGA.
The logic block contains two such slices, together with a small amount of additional logic.
Each slice consists of two 4-input LUTs, each of which can be programmed to implement any

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function of the four inputs. The carry and control logic consists of circuitry to combine the
LUT outputs, an XOR gate and an AND gate for implementing adders and multipliers, as
well as multiplexers that can be used to implement a fast carry chain.
COUT
YB
Y
LUT Carry
and S
G4 I4 O
Control D Q YQ
G3 I3
Logic CE
G2 I2
G1 I1 clk
R

F5IN
BY
SR
XB
X
LUT Carry
and S
F4 I4 O
Control D Q XQ
F3 I3
Logic CE
F2 I2
F1 I1 clk
R

BX
CIN
CE
CLK

Figure 15 The circuit of a slice of a Xilinx Spartan-II FPGA logic block.

0
D Q 1

CE
+V
clk

0
D Q 1

CE
clk

D Q
CE
clk

Figure 16 Typical organization of an FPGA I/O block.

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 The I/O block of an FPGA is typically organized as shown in Figure 16.

o The select inputs of the multiplexers are programmed to control whether the output is
registered or combinational.
o The top flip-flop and multiplexer control the high-impedance state of the tristate
driver that drives the pin as an output, and the middle flip-flop and multiplexer drive
the output value.
 The output driver is programmable, allowing selection of logic levels and control of the
slew rate.
 The RAM blocks in an FPGA provide for storage of information to be processed by the
FPGA circuitry.
 Each of the various logic, I/O and RAM blocks on an FPGA connect to interconnection
wires through programmable switches.
 There are two forms of FPGA that differ in the way they are configured.
o The first form uses RAM cells to store the configuration information.
 In-system pragrammable
o The second main form of FPGA uses antifuses to configure the device.
 An antifuse is a conductive connection that is formed during programming
 Device must be programmed separately before being installed into a system

Platform FPGAs:
 FPGAs including processor cores, computer network transmitter/receivers and
arithmetic circuits are called platform FGPAs.
 A platform FPGA is a single-chip solution upon which a complex application can be
implemented.
 Embedded software can run on the processor cores with instructions and data stored
in block RAMs.
 The network connections can be used to communicate with other computers and devices,
and the programmable logic and specialized arithmetic circuits can be used for high-
performance data transformations required by the application.
 A minimal amount of circuitry is required externally to the FPGA, thus reducing the
overall cost of the system.

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Structured ASICs:
 Structured ASIC is midway between PLDs and standard-cell ASICs.
 A structured ASIC is an array of basic logic elements, like an FPGA. It is not
programmable and no programmable interconnect.
 The logic elements are generally very simple, comprising a collection of transistors that
can be formed into logic gates and flip-flops.
 A structured ASIC is customized by designing the top one or more layers of metal
interconnection for the chip.
 Design effort and NRE cost for customization are much lower than those for a standard-
cell ASIC.
 Performance is potentially very close to that of a standard cell ASIC.

3. Packaging and Circuit boards

IC Packages
 ICs are encapsulated in protective packages.
 An IC is bonded into a package that serves several purposes:
o Protects the IC from moisture and airborne contaminants
o Provides electrical connections
o Removes heat
 There are numerous different kinds of IC package, each with different physical, electrical
and thermal properties.
 The choice of package depends on –
o the number of connections required
o the environment in which the product is to operate
 Within a package, the IC is affixed to the bottom of a cavity.
 Fine gold wires are connected from pads on the edge of the IC to points on the package’s
lead frame (see Figure 17), which is the metal framework leading to the external package
pins.
 The cavity is then sealed to protect the IC and the wires.
 For a high pin-count, high performance IC, using bond wires introduces mechanical
problems and delays and degrades signals.
 Recent packages for these ICs have adopted flip-chip technology. The connection pads on
the IC are covered in conductive material forming bumps (Figure 18).

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 The IC is then flipped over and affixed to the substrate of the package, with the bumps in
direct contact with substrate connection points.
 The connection points lead to the external pins of the package.

Figure 17 An IC in a package with bond-wires connecting to the lead frame.

Figure 18 Connection bumps on a flip-chip IC.

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Printed Circuit Boards (PCBs)

 The packaged ICs and other components in a system are assembled together on a printed
circuit board (PCB).
 PCB consists of layers of fiberglass or other insulating material separating layers of
metal wiring.
 The metal is deposited in a layer on a fiberglass sheet, and then etched using a
photolithographic process.
 Several layers are sandwiched together.
 Small holes are drilled through the layers and coated with metal to form connections,
called vias, between the layers.
 The completed PCB contains all the circuit wiring needed for the product.

Through-Hole PCBs (Suitable IC Packages – DIPs, PGAs)

 A through-hole PCB (Figure 19), includes additional metal-coated holes into which IC
package pins are inserted.
 Solder, a metal alloy with a low melting point, is melted into the holes to form electrical
connections between the pins and the PCB wiring.
 Products using this form of manufacture need ICs in insertion-type packages, such as
those shown in Figure 20.

Figure 19 A through-hole PCB.

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Figure 20 Insertion-type IC packages: DIPs (left) and PGAs (right).

 Dual in-line packages (DIPs) have two rows of pins with 0.1-inch spacing.
o SSI and MSI components
o Relatively large and limited number of pins
o largest practical size -> 48-pin DIP
 ICs requiring more pins can be packaged in a pin-grid array (PGA) package.
o Up to 400 or more pins
o Used for ICs such as computer CPUs
 Advantage of through-hole PCBs:
o can be manually assembled, since the component sizes are manageable.
o good for low-volume products

Surface-Mount PCBs (Suitable IC Packages – QFPs, BGAs)

 Is a surface-mount PCB (Figure 21), components are mounted on the surface rather than
being inserted in holes.
 Advantage –
o reduced manufacturing cost (for higher-volume products)
o finer feature sizes
o increased circuit density
 Surface mounting IC packages have pins or connection points that come into contact with
a metal pad on the PCB.
 Solder paste is applied between each pin and pad and subsequently melted, forming the
connection.

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Figure 21 A surface-mount PCB.

 There are numerous different surface mounting packages, some of which are shown in
Figure 22.

Figure 22 Surface mounting IC packages: QFPs (left) and BGA (right).

 Quad flat-pack (QFP) packages have pins along all four sides, and are suitable for ICs
with up to 200 or so pins.
 The spacing between pins varies from 1 mm for the packages with fewer pins, down to
0.65mm for the higher pin-count packages.

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 Fine-pitch QFP packages allow increased pin count, up to nearly 400 pins, by reducing
the pin spacing to 0.4mm.
 QFP packages are not suitable for manual handling and assembly.

 The most common package in use now for high pin-count ICs is the ball-grid array
(BGA) package.
 BGA packages can accommodate ICs with up to 1800 pins.

Multichip Modules (MCMs)

 Multichip modules (MCMs) attach the bare chips to a ceramic substrate (see Figure 23),
rather than placing each IC in a separate package and assembling several packages onto a
PCB.

Figure 23 A multichip module.

 Interconnection wires and passive components (resistors and capacitors) are also printed
or soldered onto the substrate.
 The complete module is then encapsulated with external connections made through
package pins to a PCB.
 Even denser packaging can be achieved by chip stacking
 Ideal for high-density applications. E.g., cell phones

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4. Interconnection and Signal Integrity

 A signal change must propagate from the source driver, through the bond wire, package
lead frame and pin of the source IC, along the PCB trace, through the pin, lead frame and
bond wire of the destination IC, and into the receiver.
 Along this path, there are several influences that can cause distortion of the signal and
introduce noise.
 The term signal integrity refers to the degree to which these effects are minimized.
 Effects include –
o signal skew
o ground bounce
o transmission line effects (overshoot, undershoot and ringing)
o electromagnetic interference (EMI) and crosstalk

Signal skew:
 In common PCB materials, the maximum propagation speed is approximately half the
speed of light in a vacuum, i.e (3 x 108ms—1) / 2 ≈150 mm/ns
 If two traces differ in length
o Skew at arrival point can be significant
o Careful PCB design needed – Use CAD tools to tune the PCB traces

Ground Bounce:

Figure 24 Inductance in the bond-wires, package leads and PCB connections for power
and ground.

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 Ground bounce arises when one or more output drivers switch logic levels.
 During switching, both of the transistors in the driver’s output stage are momentarily on,
and transient current flows from the power supply to ground.
 There is inductance in both the power and the ground connections, as shown in Figure
24.
 The inductance causes voltage spikes in the power supply and ground on the IC.
o This can cause voltage spikes on other output drivers and shifting of the
threshold voltage of receivers on the IC.
 To reduce the effects of ground bounce:
1. Place bypass capacitors between ground and +V
o Place a capacitor of value 0.01µF – 0.1µF, close to package pins
2. Separate PCB planes for ground and +V (Figure 25)
3. Limit output slew rate
o Trade off against propagation delay (Figure 26)

signal layer
power plane
signal layers
ground plane
signal layer
Figure 25 Cross section of a multilayer PCB with ground and power planes.

Figure 26 The effect of slew-rate limiting a signal. The signal takes longer to reach the
threshold voltage Vth.
 Differential signaling can be used to make the system more immune to noise induced by
ground bounce.

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Transmission-Line Effects:

Figure 27 Overshoot, undershoot and ringing transmission-line effects.

 When the transition time between logic levels is similar to or shorter than the
propagation delay along a signal path, the transition is affected by reflections at the
driving and receiving ends of the path.
 Reflections interfere with transitions, resulting in under/overshoot and ringing (Figure 27)
o Can cause false/multiple switching
 Use PCB layout techniques to minimize effects

Electromagnetic Interference (EMI) and Crosstalk:

 Transitions between logic levels on a signal cause electromagnetic fields to propagate
around the PCB trace. Some of the field energy is radiated out from the system, and may
impinge on other electronic systems, where it induces noise. This form of unwanted
coupling is called electromagnetic interference (EMI).
 There are government and other regulations that limit the amount of EMI that a system
may emit in various environments, since excessive EMI can be annoying (for example, if
it interferes with your TV reception) or a safety hazard (for example, if it interferes with
your aircraft navigation).
 Electromagnetic fields from an ―aggressor‖ PCB trace can also impinge on adjacent
traces, inducing crosstalk on the ―victim‖ traces.
 The closer the traces and the longer their parallel paths, the more pronounced the
crosstalk effect.
 EMI and Cross talk can be reduced by –
1. Appropriate PCB design techniques 2. Limiting slew rates of transitions

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Differential Signaling
 Differential signalling reduces a system’s susceptibility to noise
 Differential signaling involves transmitting both a positive signal S_P and its negation
S_N, and sensing the voltage difference between the two at a receiver.
 If S_P - S_N is a positive voltage, then S is received as the value 1; if S_P - S_N is a
negative voltage, then S is received as 0. This arrangement is illustrated in Figure 28.
 The noise is induced equally on the wires for both S_P and S_N. Such common-mode
noise is cancelled out when the voltage difference is sensed.

SP
S
SN
Figure 28 A differential driver and receiver.
 Suppose a noise voltage VN is induced equally on the two wires. At the receiver, the
voltage sensed is,
(S_P + VN) - (S_N + VN) = S_P + VN - S_N - VN = S_P - S_N
 For the assumption of common-mode noise induction to hold, differential signals must
be routed along parallel paths on a PCB.
 The signals are inverses of each other, means that they both change at the same time. So,
crosstalk effects cancel out.
 Differential signaling allows common-mode noise rejection and improved signal
integrity.
 Improved signal integrity means – reduced switching current, reduced ground bounce,
reduced EMI, and reduced crosstalk with other signals.

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