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 Introduction to COA
❖Target Audience of this course
❑ CSE/ IT/ EC/ BSC/ MSC – Computer/ IT/ Electronics
d a
❑ All the competitive examinations covered:
u n
F
▪ GATE/ BARC/ ISRO/ UGC-NET {8 to 10%}
❖Books used to prepare this course
i n g
❑ Morris Mano
e r
❑ Pal Choudhary

i ne
g
❑ William Stallings
❑ John Hayes

E n
❑ Andrew Tanenbaum
Computer Organization & Architecture
✓ Syllabus

a
Control Unit System Primary Memory ❖ Basics of Computer Architectures

d
{ROM/RAM} ❑ Von Neumann & Harvard Architecture
Bus

n
Execution Unit ❑ Flynn’s Classifications, RISC & CISC Architecture
Secondary Memory

u
❑ Memory calculation

F
Registers ❑ Registers organization in computer
Cache / TCM
❖ Machine Instructions

g
CPU Memory ❑ Instructions Formats

i n
❑ Instruction cycle, Instructions execution

r
Input Devices ❑ Addressing Modes of Instructions

e
{Keyboard / Mouse etc.} ❑ Instruction State transition Diagram

e
Output Devices ❖ Control Units

i n
{Monitor / Printer etc.} ❑ Hardwire Control Units

g
Input / Output ❑ Microprogrammed Controlled
❖ Memory

n
❖ Execution Unit
❑ Memory Hierarchy, Cache Memory & It’s Mapping ❑ ALU, Number Representation {2’s Complement, IEEE 754}

E
❑ Primary Memory, Secondary Memory ❑ Half & Full Adder, CLA
❑ TCM, Buffer ❑ Multiplier {Booth’s Algo.}, Division Algorithm {Restoring
❖ Input Output & Non Restoring methods}
❑ Memory Mapped IO & IO Mapped IO
❖ Pipelining
❑ Data Transfer Modes
❑ Pipelining Process & Pipelining Hazards
❑ Programmed IO, Interrupt, DMA
❖ System Bus
❑ Serial & Parallel IO
❑ System Bus, Bus Contention and Bus Arbitration Schemes
❑ Synchronous & Asynchronous IO.
 Computer Architecture
❖ CPU – Central Processing Unit
❑ It is Heart of computer system.

a
Control Unit Primary Memory
System {ROM/RAM} ❑ It consists Control Unit, Execution Unit & Registers.

d
Bus ❑ It executes all the programs of computer.

n
Execution Unit
Secondary Memory ❑ Program execution is execution of instructions in sequence.

u
Registers ❑ Instruction execution happens in three stages:

F
Cache / TCM ▪ Fetch

g
CPU Memory ▪ Decode
▪ Execute

i n
❑ Fetch and Decode is performed by control unit & execute is

r
Input Devices
performed by ALU.

e
{Keyboard / Mouse etc.}
❖ Memory Unit

e
Output Devices ❑ Memory stores programs and data.

i n
{Monitor / Printer etc.} ❑ Each instruction and data is stored at unique location into

g
Input / Output memory.

n
❖ System Bus ❑ Primary Memories are ROM and RAM.

E
❑ System bus lines carries information. ❑ Secondary Memories are like Floppy Disk, Hard disk etc.
❑ System includes Address bus, Data bus and control bus. ❑ Cache Memory is high speed memory built using SRAM.
❑ Address bus: it carries address information. It explains how ❖ IO devices
much physical memory can be interfaced on lines. ❑ It is used to perform Input and Output operations.
❑ Data bus: it carries data information. It explains how much ❑ Input device can be keyboard, Mouse etc.
data can be exchanged in single machine cycle. ❑ Output device can be Monitor, printer etc.
❑ Control bus; it carries control information. It explains which ❑ Touch Screen can be used as Input and Output.
operation should be performed. {Read/ Write} ❑ IO devices are used to access computer system.
 Von Neumann Architecture Void main () 0001001001000101
Main Memory

a
{ 0000100110101001

d
{Program & Data} Int A = 8, B = 5, C; 0101010010010100
Compiler

n
C = B + A; 1000100100110010

u
} 1010101110110110

F
Higher Level language Machine language {Program & data}

g
Control ❖ Main Memory of Von Neumann Architecture

n
Registers ❑ It consists program & data in same memory. So common system bus is

i
Unit

r
there for program & data access.

e
❖ Control Unit

e
❑ It provides timing control, instruction fetch, instruction decode,

i n
pipelining, Memory Access etc.

g
𝐀𝐋𝐔 ❖ Registers

n
❑ It holds data and it can be operand of ALU.

E
CPU – Central Processing Unit ❑ It is vary fast in accessing data with memory.
❑ Example: General Purpose registers, Flag Register, Stack Register,
Program Counter etc.
❖ ALU
Input Output ❑ It performs all the arithmetic and logical tasks. {+, -, *, /, ^, |}
Devices ❖ IO devices
❑ It used for user interface with computer system for input & Output.
 Harvard Architecture
Void main () 000100100 001100100
RAM Memory ROM Memory

a
{ 100010100 101010100
{Data} {Program}

d
Int A = 8, B = 5, C; Compiler 001001101 101001101

n
C = B + A; 010010101 110011101

u
} 010010010 011110010

F
Higher Level language Machine language {Program & data in

g
separate memory}
Control

n
Registers ❖ Main Memory of Harvard Architecture

i
Unit

r
❑ It consists program & data in separate memory. So program {Instructions}

e
is stored in ROM and Data is stored in RAM memory.

e
❖ Control Unit

n
❑ It provides timing control, instruction fetch, instruction decode,

g i
pipelining, Memory Access etc.
𝐀𝐋𝐔 ❖ Registers

n
❑ It holds data and it can be operand of ALU.

E
CPU – Central Processing Unit ❑ It is vary fast in accessing data with memory.
❑ Example: General Purpose registers, Flag Register, Stack Register, Program
Counter etc.
❖ ALU
Input Output ❑ It performs all the arithmetic and logical tasks. {+, -, *, /, ^, |}
Devices ❖ IO devices
❑ It used for user interface with computer system for input & Output.
 Von Neumann Vs Harvard
Address

a
Address Data
Data & Data

d
Von Neumann Memory

n
Code Harvard CPU Address
CPU Code

u
Data/Code Memory Code
Memory

g F
n
Parameters Von Neumann Harvard

r i
Memory ❖ Data and Program {Code} are stored in ❖ Data and Program {Code} are stored in

e
same memory different memory

e
Memory Type ❖ It has only RAM for Data & Code ❖ It has RAM for Data and ROM for Code
Buses

g i n
❖ Common bus for Address & Data/Code ❖ Separate Bus Address & Data/Code

n
Program Execution ❖ Code is executed serially and takes more ❖ Code is executed in parallel with data so it

E
cycles takes less cycles.
Data/Code Transfer ❖ Data or Code in one cycle ❖ Data and Code in One cycle
Control Signals ❖ Less ❖ More
Space ❖ It needs less Space ❖ It needs more space
Cost ❖ Less ❖ Costly
 Flynn’s Classifications
❖ Flynn’s Classifications ❖ SIMD – Single Instruction Multiple Data stream

a
❑ It is a way of organizing multiple processor system. ❑ In SIMD, one instruction controls multiple simultaneous

d
❑ Flynn has explained the most common approach for execution of number of processing elements on lock step

n
categorizing the systems with parallel processing basis.

u
capabilities. ❑ Each Processing unit has associate data memory for

F
❖ Categories of Computer systems execution of instruction.
❑ SISD – Single Instruction Single Data stream Processing Memory

g
❑ SIMD – Single Instruction Multiple Data stream Instruction
Unit 1 Unit 1

ir n
Data
❑ MISD – Multiple Instruction Single Data stream Stream
Stream
❑ MIMD – Multiple Instruction Multiple Data stream Control Processing Memory

e
❖ SISD – Single Instruction Single Data stream Unit Unit 2 Data Unit 2

e
❑ In SISD, one instruction runs on one processor on the data Stream

i n
stored on single memory. Processing Memory

g
❑ Uniprocessor comes in this category. Unit N Data Unit N

n
Stream
Control Processing Memory

E
❑ Scientific computing based on SIMD Architecture.
Unit Unit Unit ❑ Example of this model are vectors and arrays.
Instruction Data
Stream Stream Array A A0 A1 A2 A3 ……… An
❑ Machine Instructions are executed in sequential order.
❑ This architecture is also known sequential computers. ❑ If we want to perform arithmetic operation with all the
❑ Many of conventional computer follows this architecture. element of Array A then it can be done by this architecture.
❑ Instructions and data must be stored in primary memory. ❑ Example: Add 10 with all elements, Multiply 5 with all
❑ Clock defines the speed of processing in SISD. element, rotate 3 bits right of all the elements.
 Flynn’s Classifications
❖ MISD – Multiple Instruction Single Data stream ❖ MIMD – Multiple Instruction Multiple Data stream

a
❑ In MISD, Here multiple processor executes different ❑ In MIMD, Here multiple processor executes different

d
instructions with single data stream. instructions with multiple data stream.

n
Data Control Processing

u
Control Processing Stream Unit 1 Instruction Unit 1 Data

F
Unit 1 Instruction Unit 1 Stream 1 Stream 1
Stream 1 Control Processing

g
Control Processing Shared
Main Unit 2 Instruction Unit 2 Data

ir n
Unit 2 Unit 2 Memory
Instruction Memory Stream 2 Stream 2
Stream 2

e
Control Processing

e
Control Processing Unit N Instruction Unit N Data

i n
Unit N Instruction Unit N Stream N Stream N

g
Stream N ❑ Shared Memory in MIMD system is Symmetric

n
multiprocessor system (SMP).
❑ Different processor takes instructions and data from

E
common shared memory.
❑ This architecture is not implemented commercially. ❑ With the use of buses, multiple processor executes
❑ Example : Lets have same data ∆ to be used in multiple program along with shared memory.
instructions.
▪ A = Sin ∆
▪ B = Cos ∆
▪ C = Tan ∆
 Flynn’s Classifications
Control Processing Local Processors Organization

a
Unit 1 Instruction Unit 1 Data Memory 1

d
Stream 1 Stream 1

u n
Control Processing Local SISD SIMD MISD MIMD

F
Unit 2 Instruction Unit 2 Data Memory 2
Stream 2 Stream 2

ir n g
Uniprocessor
Control Processing Local
Unit N Instruction Unit N Memory N

e
Data Vector Array
Stream N Stream N

e
Processor Processor

n
❑ Local Memory with MIMD is Non Uniform Memory Access

i
NUMA organization.

g
❑ NUMA is costlier compared to SMP. Shared Memory Distributed Memory

n
❑ Collection of Uniprocessor or SMP can be used to form {Tightly Coupled} {Loosely Coupled}

E
cluster.
❖ Symmetric Multiprocessor SMP characteristics
❑ There are two or more similar or comparable processor.
❑ Memory Access time for all the processor will be same. Clusters
❑ All the processors shares IO devices through same channel.
❑ All the processors can perform same function. {That’s why SMP NUMA
it is called symmetric multiprocessor system}
 RISC Vs CISC
Parameters RISC CISC
Full Form ❖ Reduced Instruction Set Computer

d a
❖ Complex Instruction Set Computer

n
Instruction Size ❖ Fixed Size ❖ Variable Size

u
Instruction Fetch Time ❖ Same for all instruction ❖ Vary with respect to instructions
Instruction Set ❖ Small & Simple

g F
❖ Large and Complex

n
❖ Less Modes as most instructions are based ❖ More Modes as Complex instructions are

i
Addressing Modes

r
on registers available with different verities.

e
Numbers of Registers ❖ Many ❖ Few
Complier Design ❖ Simple

i ne ❖ Complex

g
Program Size ❖ Long {Weak code density} ❖ Small {Better Code density}

n
Numbers of Operand ❖ Fixed {Mainly in Registers} ❖ Variable {Can be in Registers & Memory}

E
Control Unit ❖ Hardwire controlled ❖ Micro Program Controlled
Execution Speed ❖ Faster ❖ Slower
Pipelining ❖ More Effective ❖ Less Effective {It has more bubbles due more
memory based instructions}
Processor ❖ More Suitable for dedicated operations. ❖ More suitable for verities of operations.
 Little Endian & Big Endian
❑ There are two ways of ordering the data while ❑ As we also operate with stack memory in CPU, we

a
storing it into the Memory. can remember this as per:

d
▪ Big Endian ❑ In Big Endian, Lower Address holds higher Byte of

n
▪ Little Endian

u
data and Higher Address holds lower Byte of data.
❑ Big Endian : Most Significant Byte stored 1st in the ❑ In Little Endian, Lower Address holds Lower Byte
memory and Last significant Byte stored at last in
the memory.

g F
of data and Higher Address holds Higher Byte of
data.

r i n
❑ Little Endian : Last Significant Byte stored 1st in the ❑ Big Endian examples: Motorola 68xx, IBM

e
memory and Most significant Byte stored at last in Mainframe, TCP/IP etc.

e
the memory. ❑ Little Endian examples: Intel x86, AMD, PIC etc.

i n
❑ Suppose we want to store 12345678H data starting ❑ Advantages of Big Endian:

g
at address 1000H. 1. Easier to determine sign

n
Add Data Add Data 2. Easier to compare two number

E
1000H 12H 1000H 78H 3. Easier to divide two number
1001H 34H 1001H 56H
1002H 56H 1002H 34H 4. Easier to Print
1003H 78H 1003H 12H ❑ Advantages of Little Endian:
1004H 1004H 1. Easier for Multiplication & Addition of
Big Endian Little Endian multi-precision numbers.
Examples on Little Endian & Big Endian
❑ GATE CS – We are given two bytes data as 10101100 00110011. How it will be stored in Little Endian

a
format?

d
A. 0x0000 = 10101100, 0x0001 = 00110011

n
B. 0x0000 = 00110011, 0x0001 = 00110011

u
C. 0x0000 = 10101100, 0x0001 = 10101100

F
D. 0x0000 = 00110011, 0x0001 = 10101100

n g
❑ GATE CS – A Hexadecimal number C34BE877H is stored from memory

i
r
location 1000H in little Endian Format, What will be the value occupied by

e
memory locations 1000H, 1001H, 1002H & 1003H?

e
A. C3H, 4BH, E8H & 77H

i n
B. C3H, E8H, 4BH & 77H

g
C. 77H, E8H, 4BH & C3H

n
D. 77H, 4BH, E8H & C3H

E
❑ ISRO 2007 CS – In the Big Endian system, the computer stores
A. MSB of Data in the lowest memory address of data unit
B. LSB of Data in the lowest memory address of data unit
C. MSB of Data in the Highest memory address of data unit
D. LSB of Data in the Highest memory address of data unit
GATE Questions of Computer Organization
❑ GATE CS – Among the given options choose correct one:

a
I. Von Neumann Architecture shares common memory for instructions and data.

d
II. Harvard Architecture has separate memory for instructions and data.

n
A. Only I is true

u
B. I and II are true

F
C. Only II is true

g
D. I and II are false

r i n
❑ GATE CS – Suppose we want to compute the value of 𝒚𝟔 , 𝒚, 𝒚𝟏/𝟑 using the

e
value of y. which of the following among Flynn’s CPU classification will be best

e
suited for above calculation?

i n
A. SISD Stream

g
B. SIMD Stream

n
C. MISD Stream

E
D. MIMD Stream
❑ GATE CS – Vector and Arrays belongs to which class of Flynn’s Classification.
A. SISD Stream
B. SIMD Stream
C. MISD Stream
D. MIMD Stream
 Memory Interfacing Questions of COA
❑ GATE CS – If there are 512G locations in the memory, then find the number of bits to represent each

a
location.

n d
Fu
i n g
e r
❑ GATE CS – If there are 26 bits available to represent each word of

ne
memory, then how many locations can be addressed uniquely?

i
n g
E
❑ GATE CS – If memory is byte addressable and size of memory is 512KB. Calculate the number of bits
required to represent each word.

d a
u n
g F
r i n
e e
g i n
E n
❑ GATE CS – If the size of memory is 521GB. Size of word is 16bits. Find the numbers of bits required to
represent each word uniquely. Also Find the number of locations required to represent each bit
uniquely.

d a
u n
g F
r i n
e e
g i n
E n
❑ GATE CS – If memory size is 64GB. If word size is 32bits. Then find the memory capacity in Words, Bytes
and bits. Also find the numbers of bits required to represent words, bytes and bits.

d a
u n
g F
r i n
e e
g i n
E n
 Memory Interfacing Questions of COA
❑ GATE CS – How many 256MB RAM chips required to build 4GB RAM?

d a
u n
g F
r i n
e
❑ GATE CS – How many 128KB RAM chips required to build 1MB RAM?

i ne
n g
E
❑ GATE CS – How many 64K X 8 RAM chips are required to build 1MB of RAM. Also Calculate the size of
decoder.

d a
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g F
r i n
e e
g i n
E n
❑ GATE CS – How many 256M X 8 RAM chips are required to build 32GB of RAM. Also Calculate the size
of decoder.

d a
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g F
r i n
e e
g i n
E n
 Memory Interfacing Questions of COA
❑ GATE CS – We are given with 64K X 2 RAM chips. How many chips required to build 128KB RAM. Also

a
calculate the size of Decoder.

n d
Fu
i n g
e r
i ne
n g
E
❑ GATE CS – We are given with 16K X 4 RAM chips. How many chips required to build 64KB RAM. Also
calculate the size of Decoder.

d a
u n
g F
r i n
e e
g i n
E n
 Memory Interfacing Questions of COA
❑ GATE 2009 CS / ISRO 2015 CS – How many 32K X 1 RAM chips are needed to provide memory capacity

a
of 256K bytes?

d
A. 8

n
B. 32

u
C. 64

F
D. 128

i n g
e r
i ne
n g
E
❑ GATE 2013 CS – A RAM chip has capacity of 1024 words of eight bits each (1K X 8). The Number of 2 X 4
decoders with enable input line needed to construct a 16K X 16 from 1K X 8 RAM is ………..
A. 4

a
B. 5

d
C. 6

n
D. 7

Fu
i n g
e r
i ne
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E
 Registers of Basic Computer in COA
Memory I Opcode Operand ❖ Memory

a
4K X 16 ❑ Here, memory is given by 4K X 16.

d
Basic Instruction Format ❑ Total Address of memory = 4 K = 𝟐𝟐 × 𝟐𝟏𝟎 = 𝟐𝟏𝟐
Address Data

n
❑ So, Numbers of Bits required to Access Memory is 12.
AR – Address Register ❑ Each Address has 16 bits of data, means word size is

u
[12 bits] 16bits.

F
PC – Program Counter ❑ Memory is used to store Instructions and data.

g
❖ Basic Instruction Format
[12 bits]

n
❑ Here, basic instruction format is given with 16 bits.

i
IR – Instruction Reg. DR – Data Register

r
❑ I bit = If it is 0 then direct addressing is used and If it is

e
[16 bits] [16 bits] 1 then indirect addressing is used.
❑ Opcode = It explains that what operation should be

e
AC – Accumulator Reg. TR – Temporary Reg. performed by given instruction. {3 bits for this case}

i n
[16 bits] [16 bits] ❑ Operand = 12 bits of operand is used to take data from

g
OUTR [8 bits] memory for given operation.
INPR [8 bits]

n
❖ AR/MAR – Address Register {12 bits for this case}

E
❖ AC – Accumulator {16 bits for this case} ❑ It holds address of memory.
❑ It is process register for ALU. ALU use it for all arithmetic and ❖ PC – Program Counter {12 bits for this case}
logical operations. ❑ It holds address of next instruction in memory.
❖ TR – Temporary Register {16 bits for this case} ❖ IR – Instruction Register {16 bits for this case}
❑ It holds data temporarily during instruction execution. ❑ After Fetching Instruction from memory, it is stored in
❖ OUTR & INPR – Input Output Registers {8 bits for this case} Instruction Register IR.
❑ OUTR holds data to be given to output devices. ❖ DR/MDR – Data Register {16 bits for this case}
❑ INPR holds data given by input devices. ❑ It has data operand read from the memory.
 Registers Organization in COA ❖ Memory and IO Devices
Memory IO Devices ❑ Memory is used to store Instructions and data of

a
4K X 16 Programs.

d
Address Data Address Data ❑ IO Devices are used to perform Input and Output

n
operations.

u
❖ System Bus

F
❑ System Bus includes Address, Data and Control signals.

g
❑ Using system bus computer executes instructions,

n
Takes data from input and gives data on to output.

r i
❖ MAR – Memory Address Register & MDR – Memory Data

e
System Bus Register

e
❑ MAR holds address of memory and MDR exchanges

n
the data with respect to memory.

g i
MAR MDR INPR OUTR ❖ INPR & OUTR

n
❑ It holds the data for Input & Output operations.

E
❖ Local Bus
Local Bus ❑ It provides internal communication with computer.
❖ Registers of Computer
PC IR AC TR ❑ It is connected with local {Internal} bus of computer.
❖ ALU and Accumulator
ALU ❑ Most of Arithmetic and Logical task of ALU is
Computer performed with respect to Accumulator register only.
 Common Bus Access using MUX in COA
Common Bus

d a
u n
S1

F
S0

i n g
r
4X1 4X1 4X1 4X1

e
MUX MUX MUX MUX

3 2 1 0 3 2 1 0

i ne3 2 1 0 3 2 1 0

g
D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0

E n
D3 D2 D1 D0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0
Register D Register C Register B Register A
Working of Computer using Common Bus in COA
S0
Common

a
S1
BUS

d
S2

n
Memory

u
7
[4096 X 16] R & W

AR [12] LD, CLR & INR 1

g F
i n
PC [12] 2
DR [16] LD, CLR & INR

e r 3

i ne
g
ALU AC [16] LD, CLR & INR 4

n
INPR [8]

E
IR [16] LD
TR [16] LD, CLR & INR
OUTR [8] LD
5
6

CLOCK
 d a
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g F
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ee
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 Questions on Registers of Computer
❑ GATE 2020 CS – Consider the following data path diagram

a
❑ Execute : 𝑹𝟎 ← 𝑹𝟏 + 𝑹𝟐

d
❑ The following steps are used to execute it over the given data path. Assume that PC is incremented

u n
appropriately. The subscripts r and w indicate read and write operations, respectively

F
1. 𝐑𝟐𝐫 , 𝐓𝐄𝐌𝐏𝟏𝐫 , 𝐀𝐋𝐔𝐀𝐃𝐃 , 𝐓𝐈𝐌𝐏𝟐𝐰
2. 𝐑𝟏𝐫 , 𝐓𝐄𝐌𝐏𝟏𝐰

g
3. 𝐏𝐂𝐫 , 𝐌𝐀𝐑 𝐖 , 𝐌𝐄𝐌𝐫
4. 𝐓𝐄𝐌𝐏𝟐𝐫 , 𝐑𝟎𝐰

r i n
e
5. 𝐌𝐃𝐑 𝐫 , 𝐈𝐑 𝐖

e
❑ Find the correct order:

i n
A. 2 1 4 5 3

g
B. 1 2 4 3 5

n
C. 3 5 2 1 4

E
D. 3 5 1 2 4
❑ GATE CS – Which of the following register is connected to system bus?
A. PC
B. MAR

a
C. IR

d
D. MDR

u n
F
❑ GATE CS – Which of following register always points to the

g
next instruction to be executed?

r i n
A. PC

e
B. MAR

e
C. IR

i n
D. MDR

n g
❑ GATE CS – Which of following register contains the most recently

E
fetched instruction?
A. PC
B. MAR
C. IR
D. MDR
❑ GATE CS – Which of the following register contains the address of a main memory location from where
instruction has to be fetched?
A. PC

a
B. MAR

d
C. IR

n
D. MDR

Fu
❑ GATE CS – Which of the following register contains the contents found at the

g
address held by MAR

n
A. PC

r i
B. AC

e
C. IR

e
D. MDR

i n
❑ ISRO 2008 CS – The Memory Address Register

g
A. Is a hardware memory device which denotes the location of the current instruction being executed

n
B. Is a group of electrical circuit, that performs the intent of instructions fetched from memory

E
C. Contains the address of memory location that is to be read from or store into
D. Contains a copy of the designated memory location specified by the MAR after “READ” or the new
contents of the memory prior to a “Write”