Chapter 1

Computer Abstractions and

Technology
 §1.1 Introduction
The Computer Revolution
› Progress in computer technology
– Underpinned by Moore’s Law
› Makes novel applications feasible
– Computers in automobiles
– Cell phones
– Human genome project
– World Wide Web
– Search Engines
› Computers are pervasive
Classes of Computers
› Personal computers
– General purpose, variety of software
– Subject to cost/performance tradeoff

› Server computers
– Network based
– High capacity, performance, reliability, dependability
– Range from small servers to building sized
Classes of Computers
› Supercomputers
– High-end scientific and engineering calculations
– Highest capability
› represented a small fraction of the overall computer
market, but share is increasing…

› Embedded computers
– Hidden as components of systems
– Stringent power/performance/cost constraints
– Real-time and dependability requirements
The PostPC Era
› Personal Mobile Device (PMD)
– Battery operated
– Connects to the Internet
– Hundreds of dollars
– Smart phones, tablets, electronic glasses
› Cloud computing
– Warehouse Scale Computers (WSC)
– Software as a Service (SaaS)
– Portion of software run on a PMD and a portion run
in the Cloud
– Amazon, Microsoft, Google
The PostPC Era
Data Center

Microsoft Data Center eastern US

Getting bigger

Planned expansion: 2km long…

What You Will Learn
› How programs are translated into the machine
language
– And how the hardware executes them
› The hardware/software interface
› What determines program performance
– And how it can be improved
› How hardware designers improve performance
› What is parallel processing
Understanding Performance
› Algorithm
– Determines number of operations executed
› Programming language, compiler, architecture
– Determine number of machine instructions executed
per operation
› Processor and memory system
– Determine how fast instructions are executed
› I/O system (including OS)
– Determines how fast I/O operations are executed
 §1.2 Eight Great Ideas in Computer Architecture
Eight Great Ideas

› Design for Moore’s Law

› Use abstraction to simplify design

› Make the common case fast

› Performance via parallelism

› Performance via pipelining

› Performance via prediction

› Hierarchy of memories

› Dependability via redundancy

 §1.3 Below Your Program
Below Your Program
› Application software
– Written in high-level language
› System software
– Compiler: translates HLL code to
machine code
– Operating System: service code
› Handling input/output
› Managing memory and storage
› Scheduling tasks & sharing resources

› Hardware
– Processor, memory, I/O controllers
 Levels of Program Code
› High-level language
– Level of abstraction closer
to problem domain
– Provides for productivity
and portability
› Assembly language
– Textual representation of
instructions
› Hardware representation
– Binary digits (bits)
– Encoded instructions and
data
 §1.4 Under the Covers
Components of a Computer
› Same components for
all kinds of computer
– Desktop, server,
embedded
› Input/output includes
– User-interface devices
› Display, keyboard, mouse
– Storage devices
› Hard disk, CD/DVD, flash
– Network adapters
› For communicating with
other computers
Touchscreen

› PostPC device
› Supersedes keyboard
and mouse
› Resistive and Capacitive
types
– Most tablets, smart
phones use capacitive
– Capacitive allows multiple
touches simultaneously
Through the Looking Glass

› LCD screen: picture elements (pixels)

– Mirrors content of frame buffer memory
Opening the Box
I/O: capacitive multitouch LCD
screen, front/rear camera,
microphone, headphone jack,
speakers, accelerometer, gyroscope,
Wi-Fi, Bluetooth

Battery

Computer board

Power, I/O
32 GB flash Apple A5
controllers
Inside the Processor (CPU)
› Datapath: performs operations on data
› Control: sequences datapath, memory, ...
› Cache memory
– Small fast SRAM memory for immediate access to
data
– SRAM is faster but less dense, and hence more
expensive, than DRAM
 Inside the Processor
› Apple A5

• 12.1 by 10.1 mm
• 45nm technology
• 2xARM @ 1GHz
• PowerVR GPU
• 512 MiB DRAM
Abstractions

› Abstraction helps us deal with complexity

– Hide lower-level detail
› Instruction set architecture (ISA)
– The hardware/software interface
› Application binary interface
– The ISA plus system software interface
› Implementation
– The details underlying and interface
A Safe Place for Data
› Volatile main memory
– Loses instructions and data when power off
› Non-volatile secondary memory
– Magnetic disk
– Flash memory
– Optical disk (CDROM, DVD)
Networks
› Communication, resource sharing, nonlocal access
› Local area network (LAN)
› Ethernet (10/100 Gbit/s)
› Wide area network (WAN): the Internet
› Wireless network (IEEE 802.11)
› WiFi, Bluetooth → 1-100 Mbit/s
 §1.5 Technologies for Building Processors and Memory
Technology Trends
› Electronics technology
4x every 3y
continues to evolve
– Increased capacity and
performance
– Reduced cost

DRAM capacity

Year Technology Relative performance/cost

1951 Vacuum tube 1
1965 Transistor 35
1975 Integrated circuit (IC) 900
1995 Very large scale IC (VLSI) 2,400,000
2013 Ultra large scale IC 250,000,000,000
Semiconductor Technology
Semiconductor
Manufacturing
› Silicon: semiconductor Process
10 µm – 1971
› Add materials to transform 6 µm – 1974
3 µm – 1977
properties: 1.5 µm – 1982
– Conductors 1 µm – 1985
800 nm – 1989
› microscopic copper or aluminum wire 600 nm – 1994
– Insulators 350 nm – 1995
250 nm – 1997
› plastic sheathing or glass 180 nm – 1999
– Switch 130 nm – 2001
90 nm – 2004
› Transistor 65 nm – 2006
45 nm – 2008
32 nm – 2010
22 nm – 2012
14 nm – 2014
10 nm – 2017
Atom size is 20-200 pm 7 nm – ~2019
5 nm – ~2021
 Manufacturing ICs
2mm
thick
~25cm

› One layer of transistors and 2-8 levels of metal

conductor, separated by layers of insulators
› Yield: proportion of working dies per wafer
Intel Core i7 Wafer

› 300mm wafer, 280 chips, 32nm technology

› Each chip is 20.7 x 10.5 mm
 Integrated Circuit Cost
Cost per wafer
Cost per die =
Dies per wafer  Yield
Dies per wafer  Wafer area Die area
1
Yield =
(1 + (Defects per area  Die area/2))2

› The cost of an integrated circuit rises quickly as the

die size increases, due both to the lower yield and to
the fewer dies that fit on a wafer.
› Nonlinear relation to area and defect rate
– Wafer cost and area are fixed
– Defect rate determined by manufacturing process
– Die area determined by architecture and circuit design
 §1.6 Performance
Defining Performance
› Which airplane has the best performance?

Boeing 777 Boeing 777

Boeing 747 Boeing 747

BAC/Sud BAC/Sud
Concorde Concorde
Douglas Douglas DC-
DC-8-50 8-50

0 100 200 300 400 500 0 2000 4000 6000 8000 10000

Passenger Capacity Cruising Range (miles)

Boeing 777 Boeing 777

Boeing 747 Boeing 747

BAC/Sud BAC/Sud
Concorde Concorde
Douglas Douglas DC-
DC-8-50 8-50

0 500 1000 1500 0 100000 200000 300000 400000

Cruising Speed (mph) Passengers x mph

Response Time and Throughput
› Response time
– How long it takes to do a task
› Throughput
– Total work done per unit time
› e.g., tasks/transactions/… per hour

› How are response time and throughput

affected by
– Replacing the processor with a faster version?
– Adding more processors?
› We’ll focus on response time for now…
Relative Performance
› Define Performance = 1/Execution Time
› “X is n time faster than Y”
Performanc e X Performanc e Y
= Execution time Y Execution time X = n
› Example: time taken to run a program
– 10s on A, 15s on B
– Execution TimeB / Execution TimeA
= 15s / 10s = 1.5
– So A is 1.5 times faster than B
Measuring Execution Time
› Elapsed time
– Total response time, including all aspects
› Processing, I/O, OS overhead, idle time
– Determines system performance
› CPU time
– Time spent processing a given job
› Discounts I/O time, other jobs’ shares
– Comprises user CPU time and system CPU time
– Different programs are affected differently by CPU
and system performance
 CPU Clocking
› Operation of digital hardware governed by a
constant-rate clock
Clock period

Clock (cycles)

Data transfer
and computation

Update state

› Clock period: duration of a clock cycle

– e.g., 250ps = 0.25ns = 250×10–12s
› Clock frequency (rate): cycles per second
– e.g., 4.0GHz = 4000MHz = 4.0×109Hz
 CPU Time

CPU Time = CPU Clock Cycles  Clock Cycle Time

CPU Clock Cycles
=
Clock Rate
› Performance improved by
– Reducing number of clock cycles
– Increasing clock rate
– Hardware designer must often trade off clock rate against
cycle count
CPU Time Example
› Computer A: 2GHz clock, 10s CPU time
› Designing Computer B
– Aim for 6s CPU time
– Can do faster clock, but causes 1.2 × clock cycles
› How fast must Computer B clock be?
Clock CyclesB 1.2  Clock Cycles A
Clock Rate B = =
CPU Time B 6s
Clock Cycles A = CPU Time A  Clock Rate A
= 10s  2GHz = 20  109
1.2  20  109 24  109
Clock Rate B = = = 4GHz
6s 6s
 Instruction Count and CPI

Clock Cycles = Instructio n Count  Cycles per Instructio n

CPU Time = Instructio n Count  CPI  Clock Cycle Time
Instructio n Count  CPI
=
Clock Rate
› Instruction Count for a program
– Determined by program, ISA and compiler
› Average cycles per instruction
– Determined by CPU hardware
– If different instructions have different CPI
› Average CPI affected by instruction mix
 CPI Example
› Computer A: Cycle Time = 250ps, CPI = 2.0
› Computer B: Cycle Time = 500ps, CPI = 1.2
› Same ISA
› Which is faster, and by how much?

CPU Time = Instructio n Count  CPI  Cycle Time

A A A
= I  2.0  250ps = I  500ps A is faster…
CPU Time = Instructio n Count  CPI  Cycle Time
B B B
= I  1.2  500ps = I  600ps

B = I  600ps = 1.2
CPU Time
…by this much
CPU Time I  500ps
A
 CPI in More Detail
› If different instruction classes take different
numbers of cycles

n
Clock Cycles =  (CPIi  Instructio n Count i )
i =1

› Weighted average CPI

Clock Cycles n
 Instructio n Count i 
CPI = =   CPIi  
Instructio n Count i=1  Instructio n Count 

Relative frequency
CPI Example
› Alternative compiled code sequences using
instructions in classes A, B, C
Class A B C
CPI for class 1 2 3
IC in sequence 1 2 1 2
IC in sequence 2 4 1 1

◼ Sequence 1: IC = 5 ◼ Sequence 2: IC = 6
◼ Clock Cycles ◼ Clock Cycles
= 2×1 + 1×2 + 2×3 = 4×1 + 1×2 + 1×3
= 10 =9
◼ Avg. CPI = 10/5 = 2.0 ◼ Avg. CPI = 9/6 = 1.5
 Performance Summary

Instructio ns Clock cycles Seconds

CPU Time =  
Program Instructio n Clock cycle

› Performance depends on
– Algorithm: affects IC, possibly CPI
– Programming language: affects IC, CPI
– Compiler: affects IC, CPI
– Instruction set architecture: affects IC, CPI, Tc
 §1.7 The Power Wall
Power Trends

› In CMOS IC technology

Power = Capacitive load Voltage2  Frequency

×30 5V → 1V ×1000
Reducing Power
› Suppose a new CPU has
– 85% of capacitive load of old CPU
– 15% voltage and 15% frequency reduction

Pnew Cold  0.85  (Vold  0.85)2  Fold  0.85

= = 0.85 4
= 0.52
Cold  Vold  Fold
2
Pold

› The power wall

– We can’t reduce voltage further
– We can’t remove more heat
› How else can we improve performance?
 §1.8 The Sea Change: The Switch to Multiprocessors
Uniprocessor Performance

Constrained by power, instruction-level parallelism,

memory latency
Multiprocessors
› Multicore microprocessors
– More than one processor per chip
› Requires explicitly parallel programming
– Compare with instruction level parallelism
› Hardware executes multiple instructions at once
› Hidden from the programmer
– Hard to do
› Programming for performance
› Load balancing
› Optimizing communication and synchronization
The multicore revolution
SPEC CPU Benchmark
› Programs used to measure performance
– Supposedly typical of actual workload
› Standard Performance Evaluation Corp (SPEC)
– Develops benchmarks for CPU, I/O, Web, …
› SPEC CPU2006
– Elapsed time to execute a selection of programs
› Negligible I/O, so focuses on CPU performance
– Normalize relative to reference machine
– Summarize as geometric mean of performance ratios
› CINT2006 (integer) and CFP2006 (floating-point)

n
n
Execution time ratio
i=1
i
CINT2006 for Intel Core i7 920
 SPEC Power Benchmark
› Power consumption of server at different
workload levels
– Performance: ssj_ops/sec
– Power: Watts (Joules/sec)

 10   10 
Overall ssj_ops per Watt =   ssj_opsi    poweri 
 i=0   i=0 
SPECpower_ssj2008 for Xeon X5650
 §1.10 Fallacies and Pitfalls
Pitfall: Amdahl’s Law
› Improving an aspect of a computer and
expecting a proportional improvement in
overall performance
Taf f ected
Timprov ed = + Tunaf f ected
improvemen t factor

› Example: multiply accounts for 80s/100s

– How much improvement in multiply performance to
get 5× overall?
80
20 = + 20 ◼ Can’t be done!
n
› Corollary: make the common case fast
Fallacy: Low Power at Idle
› Look back at i7 power benchmark
– At 100% load: 258W
– At 50% load: 170W (66%)
– At 10% load: 121W (47%)
› Google data center
– Mostly operates at 10% – 50% load
– At 100% load less than 1% of the time
› Consider designing processors to make power
proportional to load
Pitfall: MIPS as a Performance Metric

› MIPS: Millions of Instructions Per Second

– Doesn’t account for
› Differences in ISAs between computers
› Differences in complexity between instructions

Instructio n count
MIPS =
Execution time  106
Instructio n count Clock rate
= =
Instructio n count  CPI CPI  10 6
 10 6

Clock rate

› CPI varies between programs on a given CPU

 §1.11 Concluding Remarks
Concluding Remarks
› Cost/performance is improving
– Due to underlying technology development
› Hierarchical layers of abstraction
– In both hardware and software
› Instruction set architecture
– The hardware/software interface
› Execution time: the best performance measure
› Power is a limiting factor
– Use parallelism to improve performance