CS 61C Reference Card Version 5.0.

Instruction Name Description Type Opcode Funct3 Funct7

add rd rs1 rs2 ADD R[rd] = R[rs1] + R[rs2] R 011 0011 000 000 0000
sub rd rs1 rs2 SUBtract R[rd] = R[rs1] - R[rs2] R 011 0011 000 010 0000
and rd rs1 rs2 bitwise AND R[rd] = R[rs1] & R[rs2] R 011 0011 111 000 0000
or rd rs1 rs2 bitwise OR R[rd] = R[rs1] | R[rs2] R 011 0011 110 000 0000
xor rd rs1 rs2 bitwise XOR R[rd] = R[rs1] ^ R[rs2] R 011 0011 100 000 0000
sll rd rs1 rs2 Shift Left Logical R[rd] = R[rs1] << R[rs2] R 011 0011 001 000 0000
srl rd rs1 rs2 Shift Right Logical R[rd] = R[rs1] >> R[rs2] R 011 0011 101 000 0000
(Zero-extend)
sra rd rs1 rs2 Shift Right Arithmetic R[rd] = R[rs1] >> R[rs2] R 011 0011 101 010 0000
(Sign-extend)
slt rd rs1 rs2 Set Less Than if (R[rs1] < R[rs2]) { R 011 0011 010 000 0000
(signed) R[rd] = 1;
} else {
sltu rd rs1 rs2 Set Less Than R[rd] = 0;
R 011 0011 011 000 0000
(Unsigned) }
Arithmetic

addi rd rs1 imm ADD Immediate R[rd] = R[rs1] + imm I 001 0011 000
andi rd rs1 imm bitwise AND R[rd] = R[rs1] & imm I 001 0011 111
Immediate
ori rd rs1 imm bitwise OR Immediate R[rd] = R[rs1] | imm I 001 0011 110
xori rd rs1 imm bitwise XOR R[rd] = R[rs1] ^ imm I 001 0011 100
Immediate
slli rd rs1 imm Shift Left Logical R[rd] = R[rs1] << imm I* 001 0011 001 000 0000
Immediate
srli rd rs1 imm Shift Right Logical R[rd] = R[rs1] >> imm I* 001 0011 101 000 0000
Immediate (Zero-extend)
srai rd rs1 imm Shift Right Arithmetic R[rd] = R[rs1] >> imm I* 001 0011 101 010 0000
Immediate (Sign-extend)
slti rd rs1 imm Set Less Than if (R[rs1] < imm) { I 001 0011 010
Immediate (signed) R[rd] = 1;
} else {
sltiu rd rs1 imm Set Less Than R[rd] = 0;
I 001 0011 011
Immediate (Unsigned) }

lb rd imm(rs1) Load Byte R[rd] = M[R[rs1] + imm][7:0] I 000 0011 000

(Sign-extend)
lbu rd imm(rs1) Load Byte (Unsigned) R[rd] = M[R[rs1] + imm][7:0] I 000 0011 100
(Zero-extend)
lh rd imm(rs1) Load Half-word R[rd] = M[R[rs1] + imm][15:0] I 000 0011 001
(Sign-extend)
lhu rd imm(rs1) Load Half-word R[rd] = M[R[rs1] + imm][15:0] I 000 0011 101
(Unsigned) (Zero-extend)
Memory

lw rd imm(rs1) Load Word R[rd] = M[R[rs1] + imm][31:0] I 000 0011 010

sb rs2 imm(rs1) Store Byte M[R[rs1] + imm][7:0] = S 010 0011 000

R[rs2][7:0]
sh rs2 imm(rs1) Store Half-word M[R[rs1] + imm][15:0] = S 010 0011 001
R[rs2][15:0]
sw rs2 imm(rs1) Store Word M[R[rs1] + imm][31:0] = S 010 0011 010
R[rs2][31:0]
 Instruction Name Description Type Opcode Funct3

beq rs1 rs2 label Branch if EQual if (R[rs1] == R[rs2]) B 110 0011 000
PC = PC + offset
bne rs1 rs2 label Branch if Not Equal if (R[rs1] != R[rs2]) B 110 0011 001
PC = PC + offset
blt rs1 rs2 label Branch if Less Than (signed) if (R[rs1] < R[rs2]) B 110 0011 100
PC = PC + offset
Control

bltu rs1 rs2 label Branch if Less Than (Unsigned) B 110 0011 110
bge rs1 rs2 label Branch if Greater or Equal (signed) if (R[rs1] >= R[rs2]) B 110 0011 101
PC = PC + offset
bgeu rs1 rs2 label Branch if Greater or Equal (Unsigned) B 110 0011 111
jal rd label Jump And Link R[rd] = PC + 4 J 110 1111
PC = PC + offset
jalr rd rs1 imm Jump And Link Register R[rd] = PC + 4 I 110 0111 000
PC = R[rs1] + imm
auipc rd immu Add Upper Immediate to PC imm = immu << 12 U 001 0111
R[rd] = PC + imm
lui rd immu Load Upper Immediate imm = immu << 12 U 011 0111
R[rd] = imm
Other

ebreak Environment BREAK Asks the debugger to do I 111 0011 000

something (imm = 0)
ecall Environment CALL Asks the OS to do I 111 0011 000
something (imm = 1)
mul rd rs1 rs2 Multiply (part of mul ISA extension) R[rd] = (R[rs1]) * (omitted)
Ext

(R[rs2])

# Name Description # Name Desc Pseudoinstruction Name Description Translation

x0 zero Constant 0 x16 a6 Args beqz rs1 label Branch if EQuals if (R[rs1] == 0) beq rs1 x0 label
x1 ra Return x17 a7 Zero PC = PC + offset
Address bnez rs1 label Branch if Not if (R[rs1] != 0) bne rs1 x0 label
PC = PC + offset
x2 sp Stack x18 s2 Equals Zero
Pointer j label Jump PC = PC + offset jal x0 label
x3 gp Global x19 s3 jal label Jump and Link PC = PC + offset jal ra label
Pointer R[ra] = PC + 4

x4 tp Thread x20 s4 jr rs1 Jump Register PC = R[rs1] jalr x0 rs1 0

Saved Registers

Pointer la rd label Load absolute R[rd] = &label auipc, addi

x5 t0 x21 s5 Address

x6 t1
Temporary
x22 s6 li rd imm Load Immediate R[rd] = imm lui (if needed), addi
Registers
x7 t2 x23 s7 mv rd rs1 MoVe R[rd] = R[rs1] addi rd rs1 0

x8 s0 x24 s8 neg rd rs1 NEGate R[rd] = -(R[rs1]) sub rd x0 rs1

Saved
x9 s1 Registers x25 s9 nop No OPeration do nothing addi x0 x0 0

x10 a0 Function x26 s10 not rd rs1 bitwise NOT R[rd] = ~(R[rs1]) xori rd rs1 -1

x11 a1 Arguments x27 s11 ret RETurn PC = R[ra] jalr x0 ra 0

or Return
Values 31 25 24 20 19 15 14 12 11 7 6 0
x12 a2 x28 t3 R funct7 rs2 rs1 funct3 rd opcode
Temporaries

x13 a3 Function x29 t4 I imm[11:0] rs1 funct3 rd opcode

x14 a4 Arguments x30 t5 I* funct7 imm[4:0] rs1 funct3 rd opcode
x15 a5 x31 t6 S imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
Caller saved registers
B imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode
Callee saved registers (except x0, gp, tp)
U imm[31:12] rd opcode
Immediates are sign-extended to 32 bits, J imm[20|10:1|11|19:12] rd opcode
except in I* type instructions
 Selected ASCII values
HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR HEX DEC CHAR
0x20 32 {SPACE} 0x30 48 0 0x40 64 @ 0x50 80 P 0x60 96 ` 0x70 112 p
0x21 33 ! 0x31 49 1 0x41 65 A 0x51 81 Q 0x61 97 a 0x71 113 q
0x22 34 " 0x32 50 2 0x42 66 B 0x52 82 R 0x62 98 b 0x72 114 r
0x23 35 # 0x33 51 3 0x43 67 C 0x53 83 S 0x63 99 c 0x73 115 s
0x24 36 $ 0x34 52 4 0x44 68 D 0x54 84 T 0x64 100 d 0x74 116 t
0x25 37 % 0x35 53 5 0x45 69 E 0x55 85 U 0x65 101 e 0x75 117 u
0x26 38 & 0x36 54 6 0x46 70 F 0x56 86 V 0x66 102 f 0x76 118 v
0x27 39 ' 0x37 55 7 0x47 71 G 0x57 87 W 0x67 103 g 0x77 119 w
0x28 40 ( 0x38 56 8 0x48 72 H 0x58 88 X 0x68 104 h 0x78 120 x
0x29 41 ) 0x39 57 9 0x49 73 I 0x59 89 Y 0x69 105 i 0x79 121 y
0x2A 42 * 0x3A 58 : 0x4A 74 J 0x5A 90 Z 0x6A 106 j 0x7A 122 z
0x2B 43 + 0x3B 59 ; 0x4B 75 K 0x5B 91 [ 0x6B 107 k 0x7B 123 {
0x2C 44 , 0x3C 60 < 0x4C 76 L 0x5C 92 \ 0x6C 108 l 0x7C 124 |
0x2D 45 - 0x3D 61 = 0x4D 77 M 0x5D 93 ] 0x6D 109 m 0x7D 125 }
0x2E 46 . 0x3E 62 > 0x4E 78 N 0x5E 94 ^ 0x6E 110 n 0x7E 126 ~
0x2F 47 / 0x3F 63 ? 0x4F 79 O 0x5F 95 _ 0x6F 111 o 0x00 0 NULL

IEEE 754 Floating Point Standard

Sign Exponent Significand
Exponent
Significand Meaning Single Precision 1 bit 8 bits (bias = -127) 23 bits
(pre-bias; binary)
00…00 Any Value Denormalized Double Precision 1 bit 11 bits (bias = -1023) 52 bits
00…01 → 11…10 Any Value Normal
Standard exponent bias: - (2E-1-1) where E is the number of exponent bits
11…11 0 ±∞
Normalized floats: Value = (-1)Sign ⨉ 2Exp + Bias ⨉ [Link]ficand2
11…11 Non-zero NaN
Denormalized floats: Value = (-1)Sign ⨉ 2Bias + 1 ⨉ [Link]ficand2
C Format String Specifiers SI Prefixes
Specifier Output Size Prefix Symbol Size Prefix Symbol Size Prefix Symbol
d or i Signed decimal integer 10 -3 milli- m 10 3 kilo- k 2 10 kibi- Ki
u Unsigned decimal integer 10-6 micro- μ 106 mega- M 220 mebi- Mi
o Unsigned octal 10-9 nano- n 109 giga- G 230 gibi- Gi
x Unsigned hexadecimal integer, 10-12 pico- p 1012 tera- T 240 tebi- Ti
lowercase
10-15 femto- f 1015 peta- P 250 pebi- Pi
X Unsigned hexadecimal integer,
uppercase 10-18 atto- a 1018 exa- E 260 exbi- Ei
f Decimal floating point, 10-21 zepto- z 1021 zetta- Z 270 zebi- Zi
lowercase
10-24 yocto- y 1024 yotta- Y 280 yobi- Yi
F Decimal floating point,
uppercase Laws of Boolean Algebra
e Scientific notation
(significand/exponent), lowercase
E Scientific notation
(significand/exponent), uppercase
c Character
s String of characters
p Pointer address
 Single-Cycle Datapath Diagram

wdata
ALU
PC+4

+4
PC+4
0 PC
PC
ALU
1 RegFile
IMEM wdata 1 DMEM
A
rdata1 0
inst[11:7] ALU
inst rd Branch addr 1
addr Comp ALU PC+4
inst[19:15] 2
rs1
Mem
rdata2 0 rdata 0
inst[24:20]
rs2 B
1
RegWEn
wdata
inst[31:7] Imm
Gen MemRW

PCSel inst[31:0] RegWEn ImmSel BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel

5-Stage Datapath Diagram

inst
wdata
ALU

+4
PC+4
0
PC +4
ALU
1 PC RegFile PC PC

IMEM wdata 1 DMEM

A
rdata1 0
ALU
inst[11:7]
rd RegRead Branch addr 1
Data1 ALU
addr Comp ALU PC+4
inst[19:15]
rs1
Out 2
inst
inst rdata2 0 rdata Mem
inst[24:20]
0
rs2 RegRead B
Data2 1
RegWEn
wdata
Imm RegRead
inst[31:7] Gen imm Data2 MemRW

inst inst inst

inst (WB) RegWEn inst (ID) ImmSel inst (EX) BrUn BrEq BrLT BSel ASel ALUSel MemRW inst (M) PCSel WBSel