1.

Assume that for traffic light signal one hot coded signal is used to activate the red,
yellow and green lights, respectively. However, an error in the three-bit signal could
cause multiple lights to activate, or no light to activate. Design a circuit that causes
the three lights to activate normally for valid one-hot code words, and for the red light
to be
activated alone for invalid code words.

Module 2

1. Apply the correct resizing technique to interface the 7-bit unsigned output with the
11-bit unit. Write the resized binary representation and explain the logic behind the
operation.. ….5m
2. Design a 4-bit ripple carry adder using 1-bit full adders. Draw the block diagram and
discuss how the carry propagates from the least significant bit to the most significant
bit during addition….10 mrks
3. Design a full adder using multiplexer and XOR gate only to achieve fast carry
operation ( include truth table, all required expression).----10mrks
4. A 4-bit binary adder is implemented using the carry-lookahead technique. Each bit
generates a generate signal 𝑔𝑖 and a propagate signal 𝑝𝑖 . The adder uses these
signals to calculate the carry bits 𝑐1 , 𝑐2 , 𝑐3 , 𝑐4 from an initial carry-in 𝑐0 . Derive the
Boolean expressions for all carry bits 𝑐1 , 𝑐2 , 𝑐3 , 𝑐4 in terms of 𝑔𝑖 , 𝑝𝑖 , and 𝑐0 . Analyse ,
how the carry-lookahead adder improves speed compared to a ripple-carry adder.
5. Design a 4-bit circuit that can perform both addition and subtraction of two unsigned
binary numbers 𝐴 = 𝐴3 𝐴2 𝐴1 𝐴0 and 𝐵 = 𝐵3 𝐵2 𝐵1 𝐵0using a single 4-bit adder and a
control signal M. The circuit should work as follows: When M = 0, the circuit outputs
𝑆 = 𝐴 + 𝐵, M = 1, the circuit outputs 𝑆 = 𝐴 − 𝐵.
6. Design a 4-bit arithmetic circuit using a single 4-bit adder that can perform both
addition and subtraction of two 4-bit unsigned numbers, and discuss each operation
in details. Write the Verilog code for this circuit using + and – operator.
7. Design a 4-bit comparator for X and Y and generate outputs gt = 1 when X > Y.
Describe how each bit contributes to the final output.

8. Consider two unsigned 4-bit numbers 𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0and 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0 . Describe the

method for formation of partial products using AND gates and left shifts.
b) Draw a diagram showing all partial products for multiplying 𝐴and 𝐵.
c) If 𝐴 = 10112and 𝐵 = 11012, calculate all the partial products and the final
product step by step.
 9. Design with neat logical diagram unsigned 4-bit multiplier which forms partial
products and adds them. If 𝐴 = 10112and 𝐵 = 11012, find all partial products and
the final product.
10. You are given a 4-bit signed number 10112. Draw a simple circuit to resize it to a 7-
bit signed number using sign extension. Show the 7-bit output for this example.---5m
11. Add the two signed 8-bit numbers −63and −96. Write the binary result and give a
brief analysis of the result----5 marks
12. Design a 4-bit circuit that can perform both addition and subtraction of two signed
binary numbers, include unsigned and signed overflow bit.
13. Show how to use an adder for two signed fixed-point signals: a, with 4 pre-binary-
point and 7 post-binary-point bits, and b, with 6 pre-binary-point and 4 post-binary-
point bits. The result c should have 6 pre-binary-point and 4 post-binary-point
bits….5 marks
14. Express the number (4.5)10 in floating-point format with 5 bits of exponent and 12
bits of mantissa magnitude. …5 m

Module 3

1. A digital system consists of three cascaded combinational blocks with total

propagation delay exceeding one clock period. Apply the concept of pipelining by
inserting registers at appropriate locations and determine how this modification
affects the maximum clock frequency and data throughput….5m
2. Consider a combinational circuit divided into multiple stages. Demonstrate how
inserting pipeline registers between stages improves system performance, and
analyze the impact of pipelining on latency and throughput of the circuit…5m
3. Develop a Verilog model for a pipelined circuit that computes the average of
corresponding values in three streams of input values, a, b and c. The pipeline
consists of three stages: the first stage sums values of a and b and saves the value of
c; the second stage adds on the saved value of c; and the third stage divides by three.
The inputs and output are all signed fixed-point numbers indexed from 5 down to -
8…10m
4. A flip flop consists of negative-edge-triggered clock enable, negative-logic
asynchronous preset and clear, and both active-high and active-low outputs. It is
illegal for both preset and clear to be active together. Develop a Verilog model for
this flip-flop.
5. Design a 4-bit shift register capable of performing both parallel data storage and
serial data shifting operations. Use 2:1 multiplexers and edge-triggered D flip-flops
as the basic building blocks.
6. Design a multiplier for two 16-bit operands containing just one adder that adds
successive partial products over successive clock cycles. The final product is 32 bits.
7. Design a circuit that counts 16 clock cycles and produces a control signal, ctrl, that is
1 during every eighth and twelfth cycle.
8. Design a circuit that counts 16 clock cycles and produces a control signal, ctrl, that is
1 during every seven and eleven cycle.
9. Design a circuit that counts 16 clock cycles and produces a control signal, ctrl, that is
1 during every six and fourteen cycle.
10. Design a circuit that counts 16 clock cycles and produces a control signal, ctrl, that is
1 during every nine and twelfth cycle.
11. A digital alarm clock needs to generate a periodic signal at a frequency of
approximately 500Hz to drive the speaker for the alarm tone. Use a counter to divide
the system’s master clock signal, with a frequency of 1 MHz, to derive the alarm
tone.
12. Design a circuit for a modulo 10 counters, otherwise known as a decade counter.
Write the Verilog code for this.
13. Develop a Verilog model for an interval timer that has clock, load and data input
ports and a terminal-count output port. The timer must be able to count intervals of
up to 1000 clock cycles.
14. Develop a Verilog model for an interval timer that has clock, load and data input
ports and a terminal-count output port. The timer must be able to count intervals of
up to 1000 clock cycles. when it reaches zero, it reloads the previously loaded value
rather than wrapping around to the largest count value
15. Discuss the ripple counter with the timing diagram.
16. Develop a data path to perform a complex multiplication of two complex numbers.
The operands and product are all in Cartesian form. The real and imaginary parts of
the operands are represented as signed fixed point numbers with 4 pre-binary-point
and 12 post-binary-point bits. The real and imaginary parts of the product are
similarly represented, but with 8 pre-binary- point and 24 post-binary-point bits. The
complex multiplier is subject to constraints that strongly limit the circuit area.
17. Develop a Verilog model of the complex multiplier data path. The operands and
product are all in Cartesian form. The real and imaginary parts of the operands are
represented as signed fixed point numbers with 4 pre-binary-point and 12 post-
binary-point bits. The real and imaginary parts of the product are similarly
represented, but with 8 pre-binary- point and 24 post-binary-point bits. The complex
multiplier is subject to constraints that strongly limit the circuit area.
18. Design a finite state machine to implement the control sequence for the complex
multiplier. The control sequence is initiated by input_rdy being 1 during the clock
cycle in which new data arrives at the data path inputs. The operands and product
are all in Cartesian form. The real and imaginary parts of the operands are
represented as signed fixed point numbers with 4 pre-binary-point and 12 post-
binary-point bits. The real and imaginary parts of the product are similarly
represented, but with 8 pre-binary- point and 24 post-binary-point bits. The complex
multiplier is subject to constraints that strongly limit the circuit area.
19. Develop a Verilog model of the finite-state machine for complex multiplier. The
operands and product are all in Cartesian form. The real and imaginary parts of the
operands are represented as signed fixed point numbers with 4 pre-binary-point and
12 post-binary-point bits. The real and imaginary parts of the product are similarly
represented, but with 8 pre-binary- point and 24 post-binary-point bits. The complex
multiplier is subject to constraints that strongly limit the circuit area
20. Discuss the clocked synchronous timing methodology for a register-to-register
path.
With the help of a neat timing diagram, define and explain the following timing
parameters: Clock-to-output delay (𝑡𝑐𝑜 ), Propagation delay of combinational logic
(𝑡𝑝𝑑 ), Setup time (𝑡𝑠𝑢 ), Slack time (𝑡𝑠𝑙𝑎𝑐𝑘 ). Also derive the condition required to
satisfy correct timing operation.
21. Consider a register-to-register path in a synchronous digital system with the following
parameters: 𝑡𝑐𝑜 = 0.8 ns, 𝑡𝑝𝑑 = 3.5 ns, 𝑡𝑠𝑢 = 0.7 ns. Write the timing inequality that
must be satisfied for correct operation. Calculate the minimum clock period (𝑡𝑐 ). The
maximum clock frequency at which the system can operate.

Module 4
1. Design an audio echo effects unit that operates by delaying samples of an audio
signal represented as a stream of 16-bit 2s-complement binary-coded values. The
sample rate is 50kHz. Arrival of a new input sample is indicated by a control
input, audio_in_en, being 1 for the clock cycle in which the sample arrives. The
unit should indicate availability of an output sample using an output control
signal, audio_out_en, in the same way. The delay time is determined by an 8-bit
unsigned input representing the number of milliseconds of delay. The system
clock frequency is 1MHz.
2. Design a 64K × 8-bit composite memory using four 16K × 8-bit components.
3. Discuss the internal operation of an asynchronous static RAM during a write cycle
using control signals CE, WE, and OE. Include the role of address decoding, latch-
based storage cells, and timing constraints on address and data signals.
4. Describe the architecture and timing behavior of a flow-through synchronous
SRAM (SSRAM).
5. Develop a Verilog model of a dual-port, 4K ×16-bit flowthrough SSRAM. One port
allows data to be written and read, while the other port only allows data to be
read.
6. Compute the 12-bit ECC word corresponding to the 8-bit data word 01100001.
7. Determine whether there is an error in the ECC word 110111000110, and if so,
correct it.
8. Determine whether there is an error in the ECC word 000111000100, and if so,
correct it.
9. Design a FIFO to store up to 256 data items of 16 bits each, using a 256 16-bit
dual-port SSRAM for the data storage. The FIFO should provide status outputs, to
indicate when the FIFO is empty and full. Assume that the FIFO will not be read
when it is empty, nor be written to when it is full, and that the write and read
ports share a common clock