EX NO: 3 VERIFICATION OF THE TRUTH TABLE OF THE 4 TO 2 LINE PRIORITY

ENCODER AND 3 TO 8 LINE DECODER

AIM:
To verify the truth table of the 4 to 2 line priority encoder and 3 to 8 line decoder using logic
gates
APPARATUS REQUIRED:

SL NO NAME OF THE APPARATUS RANGE QUANTITY

1 Digital IC trainer 1

2 NOT Gate IC 7404 1

3 OR Gate IC 7432 1

4 AND Gate IC7408 1

5 Bread Board 1

6 NOT Gate IC7404 1

7 Connecting wires and probes As required

THEORY:
4 TO 2 LINE PRIORITY ENCODER:
The priority encoders output corresponds to the currently active input which has the
highest priority So when an input with a higher priority is present, all other inputs with a
lower priority will be ignored This is also referred to as 4- bit priority, which consists of 4
inputs and 2 output lines Since an encoder contains 2^n input lines and n output lines The
third output is ‘V’, which is considered as a valid but indicator and it is set to 1 when more
than one input line is high or active (1)If the valid bit is equal to ‘0’, then all the inputs are ‘0’
In this case, the other 2 output lines are considered as don’t care conditions denoted by ‘X
BLOCK SCHEMATIC DIAGRAM:

TRUTH TABLE FOR 4:2 PRIORITY ENCODER:

D3 D2 D1 D0 A B V

0 0 0 0 X X 0

1 0 0 0 0 0 1

X 1 0 0 0 1 1
1
X X 1 0 1 0
1
X X X 1 1 1

From the above truth table, we can observe that D3, D2, D1, D0 are the inputs; A and B are the
outputs and V is the valid bit indicator Here D3 input is the highest priority input and D0 is the
lowest priority input

When the input D3 is active high (1), which has the highest priority irrespective of all other input
lines, then the output of the 4-bit priority encoder is 11

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When the D3 input is active low and the D2 is active high that has the next highest priority
irrespective of all other input lines, then the output is BA=10

When D3, D2 inputs are active low, and the D1 is active high and has the next highest priority
regardless of the remaining input line, then the output will be BA = 01

The output expression can be determined for a 4-bit encoder with the help of a karnaugh map (K-
map) as shown below

LOGIC EXPRESSION:

A = D3 + D1D2′
B= D2 + D3
V = D 0 + D1 + D2 + D3

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LOGIC DIAGRAM:

3 TO 8 LINE DECODER:
In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic
circuit that converts coded inputs into coded outputs, where the input and output codes are different
eg n-to-2n , binary-coded decimal decoders Decoding is necessary in applications such as data
multiplexing, 7 segment display and memory address decoding
The example decoder circuit would be an AND gate because the output of an AND gate is
"High" (1) only when all its inputs are "High" Such output is called as "active High output" If instead
of AND gate, the NAND gate is connected the output will be "Low" (0) only when all its inputs are
"High" Such output is called as "active low output"

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BLOCK SCHEMATIC:

TRUTH TABLE FOR 3 TO 8 LINE:

Inputs Outputs

E A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 X X X 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 1

1 0 0 1 0 0 0 0 0 0 1 0

1 0 1 0 0 0 0 0 0 1 0 0

1 0 1 1 0 0 0 0 1 0 0 0

1 1 0 0 0 0 0 1 0 0 0 0

1 1 0 1 0 0 1 0 0 0 0 0

1 1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0

LOGIC EXPRESSION:
Y0=A'B'C'

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Y1=AB'C'
Y2=A'BC'
Y3=ABC'
Y4=A'B'C
Y5=AB'C
Y6=A'BC
Y7=ABC
LOGIC DIAGRAM :

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PROCEDURE:

1. The connections are made as per the circuit diagram.

RESULT:
The design of the 4 to 2 line Encoder and 3 to 8 Decoder circuit was implemented and the
truth table is verified successfully.

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