Department of Electronics and Communication Engineering

24EC411 Analog Circuits II

( Common to ECE and VLSI )

II Year — IV Semester
 1.1. CURRENT MIRROR (CONSTANT CURRENT SOURCE)
Q1. Draw and explain the circuit diagram of a basic current mirror. [Nov 003]
Q2. Explain the working of constant current source with a circuit diagram. [May 2005, Nov 006]
Q3. Draw the circuit of simple bipolar transistor current source and show that its output current is
dependent on the § of the transistor. [May 2007, Nov 2009]
Definition:
A circuit in which the output current is equal to input current is called current mirror.
In current mirror circuit, the output current is the mirror image of the input
current. Circuit Diagram:

Fig. Current mirror circuit

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Esplanation:
A constant current source uses the transistor in the active mode of operation.
The c o ll e c t o r c ur re nt is independent of the c olle ct o r voltage.
Transistors Q &Q2 tire matched.
The circuit is fabricated using IC technology.
I Base and emitter of Q & Q2 £fre tied together and have the same VBE
Since Q is identical to Q the emitter current of Q will be equal to emitter current of Q which
is approximately equal tO Iref.
As 1ong as Q2 is maintained in the active regio, Its collector current Ic2 will be approximately equal to Iref.
Since the output current Io is a reflection or mirror of the reference current Iref. the circuit is often
referred to as a current mirror.
Analysis:
If the effect of finite § is considered, this may lead to an output current not equal to the input reference
current, since

where the expression for ICFis found by using KCL at the collector of Q1.

The current gain of the current mirror is

which approaches unity for § very large.

Current source output current characteristics

Disadvantage:
The output resistance of the current mirror is limited by the ro of Q2,

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 1.2 CURRENT SOURCES
Current Source:
Definition:
A circuit which generates current is known as current source.
Types of current sources:
1. Widlar current source
2. Wilson current source
1. Widlar Current Source

Q. Draw the circuit of widlar current source and derive an expression for its output current. [May 2006,
Nov 2007, May 2008, Nov 2008]

Circuit Diagram:

Explanation:
In the Widlar current source, resistor (R2) is added to the emitter circuit of transistor Q2.
Since multistage amplifier systems have high gain, bias currents must be small.
The Widlar current source generates small constant currents using relatively small resistors.
Analysis:

S Where, Io is the reverse saturation current,

S VT is the thermal voltage (kT/q=26mV at room
temperature) Solving Equation for VBE, we get
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 We can express VBE1 and VBE2 in the circuit as,

Assuming we have matched devices, VT and Io are the same for Qi and Q2.
Subtracting VBE2 from VBE1, and using the appropriate property of logarithms (i.e., lnA-lnB=ln(A/B)),

Writing a KVL around the base loop of the two transistors,

Assuming that IC2=IE2=lout, and using our expression for VBEI-VBE2,

Since ICF (=ICi) is usually defined in design can be solved for the required value of R2.
2. Wilson Current Source
Q. With neat diagram explain Wilson current source. [Nov 2009]
Circuit Diagram

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Explanation:
Another current source configuration that possesses increased output resistance is the Wilson current
source.
The increased ro of the Wilson current source is due to the negative feedback provided by Q3.
It provides an output current Io which is very nearly equal tO Vref and also exhibits a very high
output resistance.
Analysis:
Writing a KCL equation at the emitter of Q2

If all three transistors are matched VBE1=VBE2'VBE3, 1' 2' 3, IB1=IB3, and Ici'k3.

Tthe relationship between base and collector currents (IB=Ic/§).

We can rewrite the expression for IE28S

Using Icz'OIE2'§IE2/(b+1) and simplifying,

Now, if we sum the currents at the base of Q2,

Solving for Ic2, we get an expression for the output current (IC2)in terms of the transistor parameter
§ and the input current, ICF

For reasonable values of §, the second term will be negligible and IC2' uNIgEF•

Therefore, in addition to the increased output resistance, the Wilson configuration provides an output
that is almost independent of the internal transistor characteristics.

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 1.3. CURRENT SOURCES AS ACTIVE LOADS

The current source can be used as an active load in both analog and digital IC‘s.

The active load realized using current source in place of the passive load (i.e. a resistor) in the collector
arm of differential amplifier.
The active load used to achieve high voltage gain without requiring large power supply voltage.

1.4. VOLTAGE SOURCES

Q. Explain the voltage sources with neat circuit diagram.
Definition:

A voltage source is a circuit that produces an output voltage Vo, which is independent of the load.
Methods:
There are four methods used to produce a voltage source, namely,
1. Voltage source circuit using Impedance transformation:
2. Emitter— follower or Common Collector Type Voltage source:
3. Voltage source using breakdown voltage of the base- emitter junction
4. Voltage Source using VBE as a reference:
1. Voltage source circuit using Impedance
transformation: Circuit Diagram:

Esplanation:
The voltage source circuit using the impedance transforming property of the transistor is shown in figure.
The source voltage Vs drives the base of the transistor through a series resistance Rs.
The output is taken across the emitter.
From the circuit, the output ac resistance looking into emitter is given by
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 Equation is applicable only for small changes in the output current.

The load regulation parameter indicates the changes in Vo resulting from large changes in output
current h.
Reduction in Vo occurs as Io goes from no-load current to full-load current and this factor determines the
output impedance of the voltage sources.
2. Emitter— follower or Common Collector Type Voltage source:
Circuit Diagram:

Esplanation:
The figure shows an emitter follower or common collector type voltage
source. Thisvoltage source is suitable for the differential gain stage used in
op-amps.
The low output impedance of the common-collector stage simulates a low impedance voltage source
with an output voltage level of Vo represented by

The diode Dr is used for offsetting the effect of dc value VBE , across the E-B junction of the
transistor.

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For compensating the temperature dependence of VBE drOp of Q1.
The load ZL shown in dotted line represents the circuit biased by the current through Qi.

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 The impedance Ro looking into the emitter of Qi derived from the hybrid z model is given by

The voltage source using common collector stage has the limitations of its weakness for changes in bias
voltage VN.
The output voltage Vo with respect to changes in supply voltage Vcc.
This is overcome in the voltage source circuit using the breakdown voltage of the base- emitter
junction. The emitter — follower stage of common — collector is eliminated in this circuit, since the
impedance seen looking into the bias terminal N is very low.
The current source Ii is normally simulated by a resistor connected between Vcc and node n.
Then, the output voltage level Vo at node N is given by V0 = VB +VBE Where VB is the breakdown
voltage of diode DB and VBE is the diode drop across Dr.
The breakdown diode DB is normally realized using the base-emitter junction of the transistor.
The diode Dr provides partial compensation for the positive temperature coefficient effect of VB.
In a monolithic IC structure, DB and Dr can be conveniently realized as a single transistor with two
individual emitters as shown in figure.
Advantages:
1. Producing low ac impedance and

2. Resulting in effective decoupling of adjacent gain stages.

[Link] source using breakdown voltage of the base- emitter junction
The structure consists of composite connection of two transistors which are diode connected back-to
back. Since the transistors have their base to collector terminals common, they can be designed as a
single transistor with two emitters.

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 The output resistance Ro looking into the output terminal in figure is given by

Ro=RB+VT/ Ii

where RB and VT / Ii are the ac resistances of the base—emitter resistance of diode DB and Dr
respectively.
Typically, RB is in the range of 40 1 to 100a, and V0 in the range of 6.5V to 9V.

4. Voltage Source using VBE as a reference:

The output stage of op-amp requires stabilized bias voltage source, which can be obtained using a
forward-biased diode connected transistor.
The forward voltage drop for such a connection is approximately 0.7V, and it changes slightly with
current.
When a voltage level greater than 0.7V, is needed, several diodes can be connected in series, which can
offer integral multiples of 0.7V.
Alternatively, the figure shows a multiplier circuit, which can offer voltage levels that need not be
integral multiplied of 0.7V.
The drop across R2 equals VBE drop of Q1. Considering negligible base current for Q1, current
through R2 is the same as that flowing through RI.
Therefore, the output voltage V0 can be expressed as

Hence, the voltage Vo can be any multiple of VBE by properly selecting the resistors Ri and R2.
Due to the shunt feedback provided by RI, the transistor current It automatically adjusts itself, towards
maintaining 12 and Vo relatively independent of the changes in supply voltage.
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 The ac output resistance of the circuit Ro is given by,

1.5. Voltage References

Q. Explain the voltage references with neat circuit diagram.

Definition:

I The circuit that is designed for providing a constant voltage independent of changes in
temperature is called a voltage reference.
Concepts:
The most important characteristic of a voltage reference is the temperature coefficient reference
voltage TCR, and it is expressed as

Reference voltage must be independent of any temperature change.

Reference voltage must have good power supply rejection which is as independent of the supply
voltage.
Output voltage must be as independent of the loading of output current.
The circuit should have low output impedance.
The voltage reference circuit is used to bias the voltage source circuit, and the combination can be
called as the voltage regulator.
The basic design strategy is producing a zero TCR at a given temperature, and thereby achieving good
thermal ability.
Temperature stability of the order of 100ppm/0C is typically expected.
Methods:

There are two methods.

1. Voltage Reference circuit using Avalanche Diode Reference:
2. Voltage Reference circuit using temperature compensation scheme

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 1. Voltage Reference circuit using temperature compensation scheme:

Circuit Diagram:

Esplanation:
This design utilizes the close thermal coupling achievable among the monolithic components.
This technique compensates the known thermal drifts by introducing an opposing and compensating
drift source of equal magnitude.
A constant current I is supplied to the avalanche diode DBand it provides a bias voltage of VB‹ the
base of Q .
The temperature dependence of the VBE drop across Qt and those across Dt ..d D2 results in
respective temperature coefficients.
Hence, with the use of resistors R1 tlnd R2 With tapping across them at point N compensates for the
temperature drifts in the base- emitter loop of Q .
This results in generating a voltage reference VR with normally zero temperature coefficient.
2. Voltage Reference circuit using Avalanche Diode Reference:

Circuit Diagram

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Explanation:
A voltage reference can be implemented using the breakdown phenomenon condition of a heavily doped
PN junction.
The Zener breakdown is the main mechanism for junctions, which breakdown at a voltage of 5V or less.

For integrated transistors, the base-emitter breakdown voltage falls in the range of 6 to 8V.
Therefore, the breakdown in the junctions of the integrated transistor is primarily due to avalanche
multiplication.
The avalanche breakdown voltage VB of a transistor incurs a positive temperature coefficient,
typically in the range of 2mV/0 C to 5mV/0C.
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The base bias for transistor Q1 is provided through register R1 and it also provides the dc current
needed to bias DB, DI and D2.
The voltage at the base of Q1 is equal to the Zener voltage VB added with two diode drops due to

D} and D2

The voltage across R2 is equal to the voltage at the base of Q1 less the sum of the base —
emitter voltages of Q1 and Q2

Hence, the voltage across R2 is approximately equal to that across DB = VB. Since Q2 and Q3 act as a
current mirror circuit, current h equals the current through R2.

It shows that, the output current Io has low temperature coefficient, if the temperature coefficient of R2 is
low, such as that produced by a diffused resistor in IC fabrication.
The zero temperature coefficients for output current can be achieved, if diodes are added in series with
R2, so that they can compensate for the temperature variation ofR2 and VB.
The temperature compensated avalanche diode reference source circuit is shown in figure.
The transistor Q4 and Q5 form an active load current mirror circuit. The base voltage of Q1 is the
voltage VB across Zener DB.
Then, VB = (VBE * n) +VBE across Q1 + VBE across Q2 + drop across R2. Here, n is the number of
diodes.
It can be expressed as

Differentiating for VB, to, R2 and VBE partially, with respect to temperature T, we get

Dividing throughout by I0 R2, we get

Therefore, zero temperature coefficient of 10 can be obtained, if the above condition is satisfied.
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 1.6. DIFFERENTIAL AMPLIFIER
[Link] the operation of basic differential amplifier. [May 2005]

Definition:

An amplifier that is used to amplify the difference between two signals is known as
differential amplifier.

This forms the basic input stage of an integrated amplifier.

The basic differential amplifier has the following important properties.

1. Excellent stability

2. High versatility and

3. High immunity to interference signals

Advantages

1. Lower cost
2. Easier fabrication as IC component and closely matched components.
Block Diagram:

The above figure shows the basic block diagram of a differential amplifier, with two input terminals and
one output terminal.
The output signal of the differential amplifier is proportional to the difference between the two input
signals. V0 = Adm (VI — V2 )
If V1 = V2, then the output voltage is zero.
A non-zero output voltage V0 is obtained when VI and V2 are not equal.
The difference mode input voltage is defined as Vm = VI — V2
The common mode input voltage is defined as

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If Vl = V2, then the differential mode input signal is zero and common mode input signal is Vcm = V1 =V2.

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 1.6.1. DIFFERENTIAL AMPLIFIER WITH ACTIVE LOAD:
[Link] the circuit of a differential amplifier with current mirror load. Drive an expression for its
gain. (May 2007, Dec 2018, May 2018) [Nov/Dec 2022]

Differential amplifier is designed with active loads to increase the differential mode voltage gain.

The open circuit voltage gain of an op-amp is needed to be as large as possible.

This is got by cascading the gain stages which increase the phase shift.

The gain can be increased by using large values of collector

resistance. For such a circuit, the voltage gain is given by Adm =
gm Rc
To increase the gain the Ic Rc product must be made very large.

Limitations in IC fabrication

1. A large value of resistance needs a large chip area.

2. For large RC, the quiescent drop across the resistor increased.
3. A large power supply will be required to maintain a given operating current.
4. Large monolithic resistor introduces large parasitic capacitances which limits the frequency response
of the amplifier.
5. For linear operation of the differential pair, the devices should not be allowed to enter into saturation.

This limits the max input voltage that can be applied to the bases of transistors Ql and Q2 the base-
collector junction must be allowed to become forward-biased by more than 0.5V.
The large value of load resistance produces a large dc voltage drop (IEE / 2) Rc, so that the collector
voltage will be VC=Vcc - (IEE/2) RC and it will be substantially less than the supply voltage Vcc.
This will reduce the input voltage range of the differential amplifier.

Due to the reasons cited above, an active load is preferred in the differential amplifier configurations.

BJT Differential Amplifier using active loads:

A simple active load circuit for a differential amplifier is the current mirror active load as shown in
figure.

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 The active load comprises of transistors Q3 and Q4 with the transistor Q3 connected as a Diode with
its base and collector shorted. The circuit is shown to drive a load RL.
When an ac input voltage is applied to the differential amplifier, the various currents of the circuit
are given by IC4 = IC3 = ICI = gmVid/2, where IC4 = IC3 due to current mirror action. IC2 = -
gmVid/2 . We know that the load current IL entering the next stage is
IL= IC2-IC4 = - gmVid/2 - gmVid/2 = - gmVid
Then, the output voltage from the differential amplifier is given by V0= - ILRL = gon

RLVid. The ac voltage gain of the circuit is given by

I The amplifier can amplify the differential input signals

It provides single-ended output with a ground reference since the load RL is connected to only one
output terminal.
This is made possible by the use of the current mirror active load.

The output resistance Ro of the circuit is that offered by the parallel combination of transistors Q2
(NPN) and Q4 (PNP). It is given by Rr = ro2 || ro4
Analysis of BJT differential amplifier with active load:

The collector currents of all the transistors are equal. IC1 = IC2 = IC3 =IC4 = IEE/2 .

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 The Collector -emitter voltages of Q1 and Q2 are given
by VCEI-VCE2 =VC-VE=V CC - VEB-(-VEB)=
VCC
Equation shows that, the offset is higher than that of a resistive loaded differential amplifier A.
This can be reduced by the use of emitter resistors for Q 3 and Q 4 , and a transistor Q5 in the
current mirror load.
Common Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of differential mode gain to the common mode gain.
The common mode rejection ratio is a measure of the differential amplifier's ability to reject the
common mode signal and amplify the differential mode signal.

Thus, the larger the input trans conductance or REE, the larger the common mode rejection ratio.
Input common-mode range (ICMR)
The input common-mode range is the range of common-mode voltages over which the differential
amplifier continues to sense and amplify the difference signal with the same gain.
Typically, the ICMR is defined by the common-mode voltage range over which all MOSFETs remain in
the saturation region and all BJTs remain in the active region.
Output offset voltage ( VOS(out))
The output offset voltage is the voltage which appears at the output of the differential amplifier when the
input terminals are connected together.
Input offset voltage ( VOS(in) = VOS)
The input offset voltage is equal to the output offset voltage divided by the differential voltage gain.

1.7. BASIC INFORMATION ABOUT OPERATIONAL AMPLIFIERS

Q. Explain about Ideal Op-amp in detail. [May 2018)
An operational amplifier is a direct coupled high gain amplifier.
It consists of one or more dfferential amplifiers, followed by a level translator and an output
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stage. It is a versatile device.

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 It is used to amplify ac as well as dc input signals & designed for computing mathematical functions
such as addition, subtraction, multiplication, integration & differentiation.

Symbol:

Pin Configuration:

Ideal characteristics of O P A M P

1. Open loop gain infinite

2. Input impedance infinite

3. Output impedance zero

4. Bandwidth infinite

5. Zero offset, ie, Vo=0 when V1=V2=0

Ideal Vs Practical Op-Amp

Parameter Ideal Practical

Open Loop gain A 105
Bandwidth BW 10-100Hz
Input Impedance Z >lMf2

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 Output Impedance Z t 0 f2 10-100 f2
Output Voltage out Depends only on Depends slightly on
Rd = (V+—V-) Differential mode average input - (V++V-)/2
signal Common- Mode signal

CMRR 10-100dB

1.8. GENERAL OPERATIONAL AMPLIFIER STAGES

Q1. Explain the general stages of op-amp with block diagram.
Q2. Draw and explain the block diagram of an op amp. Discuss the functions of each stage
in detail.[Nov/Dec 2021] [Nov/Dec 2022]

1. Input stage:
The input stage, or differential amplifier, provides the common-mode rejection to op-amp operation.

It also supplies the large input impedance.

It allows coupling to a high impedance source without loss of signal level.
The differential amplifier may also provide voltage gain if the output of the differential amplifier is
connected to an emitter follower with a large emitter resistor.
The Emitter Follower amplifier will provide a high impedance load to the differential amplifier to
obtain a high voltage gain.
2. Intermediate stage:

The intermediate stages are shown as the voltage gain stage and the level shifter in the figure above.

The voltage gain stage usually consists of one or more CE amplifiers to provide the bulk of the overall
voltage gain.
Linear operational amplifiers are direct coupled to eliminate the need for coupling capacitors that are too
large to be placed on an IC chip.
The level shifter stage may be one or more level shifters that are included to ensure that there is no dc
offset in the output signal.
In addition, these intermediate stages may be used to convert the signal from differential (double-
ended) mode to single-ended mode.

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3. Output stage:

The output stage, or power output stage, also serves a dual purpose.

It must supply the current required by the load without dissipating too much power in the output
transistors.
The output stage should provide a low output impedance to allow coupling to a low impedance load
without loss of gain.

1.9. INTERNAL CIRCUIT DIAGRAMS OF IC 741

[Link] CHARACTERISTICS OF AN OP-AMP

Q. Explain the AC characteristics of op-amp.[Nov/Dec 2021] [Nov/Dec 2022]

1. Frequency Response
2. Circuit Stability
3. Slew Rate
4. Frequency Compensation
1. Frequency Response:

The variation in operating frequency will cause variations in gain magnitude and its phase angle.

The gain of the op-amp responds to different frequencies is called the frequency response.

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Op-amp should have an infinite bandwidth BW

8
II
If its open loop gain in 90dB with dc signal, its gain should remain the same 90 dB through audio and
onto high radio frequency.
The op-amp gain decreases (roll-off) at higher frequency.

There is a capacitive component in the equivalent circuit of the op-amp, decrease gain after a certain
frequency reached.
For an op-amp with only one break (corner) frequency, all the capacitors effects can be represented by a
single capacitor C.
Variation of the low frequency model with capacitor C at the output is shown in fig.

Equivalent circuit of practical circuit

There is one pole due to RoC and one -20dB/decade.

The open loop voltage gain of an op-amp with only one corner frequency is obtained from above
fig. fi is the corner frequency or the upper 3 dB frequency of the op-amp.

The magnitude and phase angle characteristics:

1. For frequency f<< fl, the magnitude of the gain is 20 log AOL in db.

2. At frequency f= f1, the gain in 3 dB down from the dc value of AOL in db.
This frequency fl is called comer frequency.
3. For t>> fl, the fain roll-off at the rate off -20dB/decade or -6dB/decade.

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 Frequency response of op amp

2. Circuit Stability:
Q. Explain various stability criteria of op-amp. [Nov 2006]
A circuit or a group of circuit connected together as a system is said to be stable, if its output
reaches a fixed value in a finite time.
A system is said to be unstable, if its output increases with time instead of achieving a fixed
value. Bode plots are compared of magnitude Vs Frequency and phase angle Vs frequency.
Any system whose stability is to be determined can represented by the block diagram.

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 Feedback loop system
The block between the output and input is referred to as forward block.
The block between the output signal and feedback signal is referred to as feedback block.
The content of each block is referred as transfer frequency.
AOL (f) = V0 /Vin if Vf= 0------(1)

where AOL (f) = open loop volt gain.

The closed loop gain Af is given by AF = V0 /Vin = AOL / (1+(AOL ) (B)-- -(2)

B = gain of feedback circuit.

B is a constant if the feedback circuit uses only resistive components.

Once the magnitude Vs frequency and phase angle Vs frequency plots are drawn, system stability may
be determined as follows
Method 1:

Determine the phase angle when the magnitude of(AOL) (B) is 0dB (or)
1. If phase angle is >-180, the system is stable.
However, some systems the magnitude may never be 0, in that cases method 2, must be used.

Method 2:

Determine the phase angle when the magnitude of(AOL) (B) is 0dB (or) 1.
If phase angle is > - 180, the magnitude is —ve decibels then the system is stable.
However, some systems the phase angle of a system may reach -1800, under such conditions method
1 must be used to determine the system stability.
[Link] Rate:
Q. Define slew rate and describe the methods to improve slew rate. [Nov 2005, 08, 2009, May 2009,

Dee 2018]

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 The slew rate is defined as the maximum rate of change of output voltage caused by a step input
voltage.
An ideal slew rate is infinite.
Slew rate is the maximum rate of change of output voltage with respect to
time. It is specified in V/ps.
Reason for Slew rate:

The rate at which the volt across the capacitor increases is given
by dVc/dt = FC----(1)

I -> Maximum amount furnished by the op-amp to capacitor C.

Op-amp should have the either a higher current or small compensating capacitors.
4. Frequency Compensation:
Frequency compensation is needed when large bandwidth and lower closed loop gain is desired.
Compensating networks are used to control the phase shift and hence to improve the stability.
Frequency compensation methods:

1. External compensation

a. Dominant- pole compensation

b. Pole- zero compensation

2. Internal compensation
1.11. DC CHARACTERISTICS OF AN OP-AMP
Q. Explain the DC characteristics of op-amp.

DC characteristics of op amp are,

1. Input bias current

2. Input offset current
3. Input offset voltage
4. Thermal drift
1. Input bias current:

Input bias current IBis defined as the average value of the base currents entering into terminal of an
op- amp.
IB' (IB“+ IB°) / 2

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2. Input offset current

The difference between the bias currents at the input terminals of the op- amp is called as input offset current.
Its= IB+ - IB*
The input terminals conduct a small value of dc current to bias the input transistors. Since the input
transistors cannot be made identical, there exists a difference in bias currents

3. Input offset voltage

A small voltage applied to the input terminals to make the output voltage as zero when the two input
terminals are grounded is called input offset voltage

4. Thermal drift

Bias current, offset current and offset voltage change with temperature.
A circuit carefully nulled at 25°c may not remain so when the temperature rises to 35°c. This
is called drift.
1.12. OPEN LOOP OP-AMP CONFIGURATION
Q. Explain the open loop configuration of op-amp with example circuits. (Nov 2016)
The term open-loop indicates that no feedback in any form is fed to the input from the output.
When connected in open — loop, the op-amp functions as a very high gain amplifier.
There are three open — loop configurations of op-amp namely,

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 1. Differential amplifier

2. Inverting amplifier

3. Non-inverting amplifier

The above classification is made based on the number of inputs used and the terminal to which the
input is applied.
The op-amp amplifies both ac and dc input signals.
Thus, the input signals can be either ac ordc voltage.
1. Differential Amplifier:

In t hi s c o n fi gur at i o n, the in p ut s are app li e d t o b o t h th e inv er ti n g and the

non- inverting input terminals of the op-amp.
It amplifies the difference between the two input voltages.

Figure shows the open-loop differential amplifier

configuration. The input voltages are represented by Vi1 and

Vi2.

The source resistance Rii and Ri2 are negligibly small in comparison with the very high input resistance
offered by the op-amp.
Thus the voltage drop across these source resistances is assumed to be zero.

The output voltage Vo is given by

V0 A (Vil — Vi2)
where A is the large signal voltage gain.
Thus the output voltage is equal to the voltage gain A times the difference between the two input
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voltages. This is the reason why this configuration is called a differential amplifier.
In open — loop configurations, the large signal voltage gain A is also called open-loop gain A.

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2. Inverting amplifier:

In this configuration, the input signal is applied to the inverting input terminal of the op - amp and the
non-inverting input terminal is connected to the ground.
Figure shows the circuit of an open loop inverting amplifier.

The output voltage is 180 out of phase with respect to the input.
Hence, the output voltage V0 is given by,
V0 = -AVi.

Thus, in an inverting amplifier, the input signal is amplified by the open-loop gain A and in phase
shifted by 1800.
[Link]-inverting Amplifier:

Figure shows the open — loop non- inverting amplifier.

The i np ut s i gn a1 i s ap p1 i e d t o t h e n o n - inverting input terminal of the op-amp
and the inverting input terminal is connected to the ground.

The input signal is amplified by the open — loop gain A and the output is in-phase with input signal.

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Vo AVi

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Limitations of Open — loop Op — amp configuration:

In the open — loop configurations, clipping of the output waveform can occur when the output
voltage exceeds the saturation level of op-amp.
This is due to the very high open — loop gain of the op-amp.

The open — loop gain of the op — amp is not a constant.

It varies with changing temperature and variations in power supply.
Also, the bandwidth of most of the open- loop op amps is negligibly small.
This makes the open — loop configuration of op-amp unsuitable for ac applications.
1.13. CLOSED LOOP OP-AMP CONFIGURATION
Q. Explain the inverting and Non-inverting amplifier of closed loop configurations. [Dec 2018]
The op-amp can be effectively utilized in linear applications by providing a feedback from the
output to the input, either directly or through another network.
If the feedback signal is out - of- phase by 1800 with respect to the input, then the feedback is
referred to as negative feedback or degenerative feedback.
If the feedback signal is in phase with re sp ect to the input, then the feedback is referred to as
positive feedback or regenerative feedback.
An op amp that uses feedback is c al l ed a clo se d — loop ampli fi
er. The most commonly used closed loop amplifier configurations are
1. Inverting amplifier (Voltage shunt amplifier)
2. Non- Inverting amplifier (Voltage — series Amplifier)
The inverting close-loop configuration
External components R1 and R2 form a close
loop Output is fed back to the inverting input
terminal

Input signal is applied from the inverting terminal

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34
 The required conditions to apply virtual short for op-amp circuit:

S Negative feedback configuration

S Infinite open- loop gain
Closed loop gain: G - VO II = -R2 /R1
Infinite differential gain: V2 - V1 = Vo /A =
0

Infinite input impedance: i2 = i1 = 0

Zero output impedance: Vo = Vl - i1R2 = - vI R2 /R1

Voltage gain is negative: Input and output signals are out of phase

Closed loop gain depends entirely on external passive components (independent of op-amp gain)

Close loop amplifier trades gain (high open loop gain) for accuracy (finite but accurate closed loop
gain)
Equivalent circuit model for the inverting configuration

Input impedance: Ri -vI /iI = vI / (vI /R1) = R1

For high input closed loop impedance, RI should be large, but is limited to provide sufficient
G In general, the inverting configuration suffers from a low input impedance
Output impedance: Ro = 0

Voltage gain: Avo = -

R2/R1

[Link] inverting closed loop Configuration:

External components RI and R2 form a close loop

35
Output is fed back to the inverting input terminal Input signal is applied from the noninverting terminal.

36
 The required conditions to apply virtual short for op- amp
circuit: S Negative feedback configuration
S Infinite open loop gain

Closed loop gain: G - VO /VI = 1 + R2 /R1

Infinite differential gain: V+ - V- - Vo /A =

0 Infinite input impedance: i2 = i1 = V-

/R1

Zero output impedance: Vo = V- + iiR2 = VI (1 + R2 /R1)

Closed loop gain depends entirely on external passive components (independent of op amp gain)

Close loop amplifier trades gain (high open loop gain) for accuracy (finite but accurate closed loop gain)
Equivalent circuit model for the noninverting configuration

Input impedance: Ri = Infinite

Output impedance: Ro = 0

37
 UNIT II
APPLICATIONS OF OPERATIONAL AMPLIFIERS
Sign Changer (Phase Inverter)
Explain sign changer and scale changer using op-amp.

The basic inverting amplifier configuration using an op-

amp with input impedance Z1 and feedback impedance
Zf .
If the impedance Z1 and Z f are equal in magnitude and
phase, then the closed loop voltage gain is -1, and the input
signal will undergo a 180° phase shift at the output.
Hence, such circuit is also called phase inverter.
If two such amplifiers are connected in cascade, then the output from the second stage is the same
as the input signal without any change of sign.
Hence, the outputs from the two stages are equal in magnitude but opposite in phase and such a
system is an excellent paraphase amplifier.
Scale Changer:
Referring the above diagram, if the ratio Zf Zt = k, a real constant, then the closed loop gain is —
k, and the input voltage is multiplied by a factor —k and the scaled output is available at the
output.
Usually, in such applications, Zf and Z1 are selected as precision resistors for obtaining precise
and scaled value of input voltage.
Phase Shift Circuits
Explain the phase shift circuits using op-amp.
The phase shift circuits produce phase shifts that depend on the frequency and maintain a constant

These circuits are also called constant-delay filters or all-pass filters.

That constant delay refers to time difference between input and output remains constant when
frequency is changed over a range of operating frequencies.
This is called all-pass because normally a constant gain is maintained for all the frequencies
within the operating range.
1
 The two types of circuits, for lagging phase angles and leading phase angles.
Phase-lag circuit:
Phase lag circuit is constructed using an op-amp, connected in both inverting and non-inverting
modes.
To analyze the circuit operation, it is assumed that the input voltage v1 drives a simple inverting
amplifier with inverting input applied at(-)termina1 of op-amp and a non-inverting amplifier with
a low-pass filter.
It is also assumed that inverting gain is -1 and non-inverting gain after the low-pass circuit is

and the relationship between output and input can be expressed by

The relationship is complex as defined above equation and it shows that it has both magnitude and
phase. Since the numerator and denominator are complex conjugates, their magnitudes are identical and
the overall phase angle equals the angle of numerator less the angle of the denominator.

Phases-lead circuit

2
 Phase lead circuit is constructed using an op-amp, connected in both inverting and non-inverting
modes.
To analyze the circuit operation, it is assumed that the input voltage v1 drives a simple inverting
amplifier with inverting input applied at(-)terminal of op-amp and a non-inverting amplifier with
a High-pass filter.
Voltage follower:
Draw the voltage follower circuit and explain. (May 2018)

If R1=m and Rf =0 in the non-inverting amplifier

configuration. The amplifier act as a unity-gain
amplifier or voltage follower.
The circuit consists of an op-amp and the output
voltage is equal to the input voltage, both in
magnitude and phase. V0=Vi.

Since the output voltage of the circuit follows the input voltage, the circuit is called voltage
follower. It offers very high input impedance of the order of Mfg and very low output impedance.
Therefore, this circuit draws negligible current from the source.
Thus, the voltage follower can be used as a buffer between a high impedance source and a low
impedance load for impedance matching applications.

3
 Voltage to Current Converter with floating loads (V/I) [Nov/Dec 2022]
Explain voltage to current converter using op-amp. (Nov 2006, 2016, May 2018) [Nov/Dec 2021]

Voltage to current converter in which

load resistor RL is floating (not
connected to ground).
Vin is applied to the non- inverting input
terminal, and the feedback voltage across
R1 devices the inverting input terminal.
This circuit is also called as a current —
series negative feedback amplifier.

Because the feedback voltage across RI (applied Non-inverting terminal) depends on the output
current i0 and is in series with the input difference voltage Vid.
Writing KVL for the input loop,

From the fig input voltage Vin is converted into output current of Vin/RL [Vin -> i0].
In other words, input volt appears across R1. If RL is a precision resistor, the output
current (i0 = Vin/R1) will be precisely fixed.
Applications:
1. Low voltage ac and dc voltmeters
2. Diode match finders
3. LED and Zener diode testers.
Voltage — to current converter with Grounded load

4
EC8453 / Linear Integrated Circuits UNIT-2

This is the other type V — I converter, in which one terminal of the load is connected to ground.
Analysis of the circuit:
The analysis of the circuit can be done by following 2 steps.
1. To determine the voltage V1 at the non-inverting (+) terminals and
2. To establish relationship between V1 and the load current IL. Applying KCL at node
a, R= Rf
Il +I2=IL
(Vi+Va)/R + (Vo —Va )/R= IL
Vo = (Vi +Vo - IL R)/2 and gain =1+ R/R= 2.

Current to Voltage Converter (I —V):

Explain current to voltage converter using op-amp. (Nov 2016)[Nov/Dec2021]

Open — loop gain A of the op-amp is very large. Input impedance of the op amp is very high.
Sensitivity of the I — V converter:
1. The output voltage V0 = -RF lin.
2. Hence the gain of this converter is equal to -RF. The magnitude of the gain (i.e.) is called as sensitivity
of I to V converter.
3. The amount of change in output volt AV0 for a given change in the input current AIin is decide by
the sensitivity of I-V converter.
4. By keeping RF variable, it is possible to vary the sensitivity as per the requirements.
Applications of I — V Converter:
One of the most common uses of the current to voltage converter is
1. Digital to analog Converter (DAC)
2. Sensing current through Photo detector. Such as photo cell, photo diodes and photovoltaic cells.
Photoconductive devices produce a current that is proportional to an incident energy or light (i.e). It
can be used to detect the light.

5
 Adder:
Op-amp may be used to design a circuit whose output is the sum of several input signals. Such a
circuit is called a summing amplifier or a summer or adder.
Inverting Summing Amplifier:

A typical summing amplifier with three input

voltages V1, V2 and V3 three input resistors
R1, R2, R3 and a feedback resistor Rf is
shown in figure.
The op-amp is an ideal one, AOL= m.
Since the input bias current is assumed to be
zero, there is no voltage drop across the resistor Rcomp and hence the non-inverting input terminal is
at ground potential.
I= V1/RI+V2/R2. +Vn/Rn;
Vo= - Rf I=Rf/R(V1+V2+. Vn).
To find Rcomp, make all inputs VI = V2 = V3 =
0. So the effective input resistance Ri = R1 || R2 ||
R3. Therefore, Rcomp = Ri || Rf= RI || R2 || R3 ||
R,f.
Non-Inverting Summing Amplifier:

A summer that gives a non-inverted sum is the non-

inverting summing amplifier of figure
Let the voltage at the (-) input terminal be Va. which is
a non-inverting weighted sum of inputs.
Let RI = R2 = R3 = R = Rf/2, then Vo = VI+V2+V3
Subtractor:
(Write short notes on subtractor.) (May
2018)
A basic differential amplifier can be used as a
subtractor as shown in the above figure.
If all resistors are equal in value, then the output voltage
can be derived by using superposition principle.
 To find the output V01 due to V1 alone, make V2 = 0.
Then the circuit of figure as shown in the above becomes a non-inverting amplifier having input
voltage V1/2 at the non-inverting input terminal and the output becomes
V01 = V1/2(1+R/R) = V1 when all resistances are R in the circuit.
Similarly the output V02 due to V2 alone (with V1 grounded) can be written simply for an inverting
amplifier as V02 = -V2
Thus the output voltage Vo due to both the inputs can be written as V0 =V01 - V02 =V1 - V2
Adder/Subtractor:

It is possible to perform addition and subtraction

simultaneously with a single op-amp using the
circuit shown in figure
The output voltage Vo can be obtained by using
superposition theorem.
To find output voltage V01 due to V1 alone, make
all other input voltages V2, V3 and V4 equal to
Instrumentation Amplifier: zero.

Explain operation of instrumentation amplifier. Name two applications of the same. (Nov 2003,
May 2005, 2008, Dec 2018)

Current flowing in resistor R is I= (VI-V2)/R and it flow through R’ in the direction shown, Voltage
at non-inverting terminal op-amp A3 is R2V1’/(R1+R2).
By superposition theorem,
Vo= (R2/R1)V1+(1+R2/R1)(R2V2/(R1+R2)=R2/RI(VI’-V2’);
V1’= R’I+V1=R’/R(V1-V2)+V1
V2’= R’I+V1=R’/R(V1-V2)+V2;
V0= (R2/R1)[(2R’/R(V2-V1)+ (V2-V1)]= (R2/R1)[(1+2R’/R)(V2-V1)
In a number of industrial and consumer applications, one is required to measure and control physical
quantities.
Some typical examples are measurement and control of temperature, humidity, light intensity, water
flow etc. these physical quantities are usually measured with help of transducers.
The output of transducer has to be amplified so that it can drive the indicator or display system.
This fiinction is performed by an instrumentation amplifier.
The important features of an instrumentation amplifier are
1. High gain accuracy
2. High CMRR
3. High gain stability with low temperature coefficient
4. Low output impedance
There are specially designed op-amps such as pA725 to meet the above stated requirements of a
good instrumentation amplifier.
The op-amp A1 and A2 have differential input voltage as zero. For V1=V2, that is, under common
mode condition, the voltage across R will be zero. As no current flows through R and R‘ the non-
inverting amplifier.
A1 acts as voltage follower, so its output V2‘=V2. Similarly op-amp A2 acts as voltage follower
having output V1‘=V1. However, if V1JV2, current flows in R and R‘, and (V2‘-V1‘)> (V2- VI).
Therefore, this circuit has differential gain and CMRR more compared to the single opamp circuit.
The difference gain of this instrumentation amplifier R, however should never be made zero, as this
will make the gain infinity.
To avoid such a situation, in a practical circuit, a fixed resistance in series with a potentiometer is used
in place of R.

Figure shows a differential instrumentation amplifier using Transducer Bridge.

8
 The circuit uses a resistive transducer whose resistance changes as a function of the physical quantity to
be measured.
The bridge is initially balanced by a dc supply voltage Vdc so that V1=V2.
As the physical quantity changes, the resistance RT of the transducer also changes, causing an
unbalance in the bridge (VI JV2).
This differential voltage now gets amplified by the three opamp differential instrumentation amplifier.

Applications of instrumentation amplifier with the transducer bridge:

temperature indicator,
temperature controller and
light intensity meter
Integrator:
Q. Explain the circuit that provides an output voltage which is proportional to the time integral of
the input. [Nov/Dec 2021][Nov/Dec 2022]
Draw the circuit of integrator using opamp. Explain the working. ( Nov 2009)

A circuit in which the output voltage is the integral of the input voltage is the integrator or Integration
Amplifier.
The expression for the output voltage V0 can be obtained by KVL eqn. at node
V2. ii = IB + if

Since IB is negligiblesmall, iJ 'iF

Relation between current through and voltage across the capacitor is
() Cdvc(1)/d
 The output voltage can be obtained by integrating both sides with respect to time

Practical Integrator:
Practical Integrator reduce the error voltage at the output, a resistor RF is connected across the
feedback capacitor CF.
Thus RF limits the low frequency gain and hence minimizes the variations in the output voltages.
The frequency response of the basic integrator, shown from this fb is the frequency at which the
gain is dB and is given by

10
Both the stability and low frequency roll-off problems can be corrected by the addition of a resistor
RF in the practical integrator.
o Stability refers to a constant gain as frequency of an input signal is varied over a certain range.
o Low frequency -> refers to the rate of decrease in gain roll off at lower frequencies.
The gain limiting frequency fa is given by

The value of fa and R1 CF and RF CF values should be selected such that fa<fb.
The input signal will be integrated properly if the time period T of the signal is larger than or equal to RF
CF,

Uses:
Most commonly used in
• Analog computers
• ADC
• Signal wave shaping circuits.

11
Differentiator:
Draw the circuit of differentiator using op-amp. Explain the working. ( Nov 2009)
Explain the circuit that performs the mathematical operation of differentiation. Draw its output wave
form. [Nov/Dec 2021]

The circuit performs the mathematical operation of differentiation (i.e.) the output waveform is
the derivative of the input waveform.
Since the differentiator performs the reverse of the integrator function. Thus the output V0 is equal to
RF Cl times the negative rate of change of the input voltage Vin with time.
The negative sign indicates a 180 phase shift of the output waveform V0 with respect to the input
signal. The below circuit will not do this because it has some practical problems. The gain of the
circuit (RF
/XC1) R with R in frequency at a rate of 20dB/decade.
This makes the circuit unstable. Also input impedance XCls with R in frequency which makes
the circuit very susceptible to high frequency noise.

The output voltage can be obtained by differentiating input voltage with respect to time
Vo(t)- -RfC1dvin(t)/dt
Practical Differentiator:

A workable differentiator can be designed by

implementing the following steps.
1. Select fa equal to the highest frequency of the
input signal to be differentiated then assuming a
value of Ct < lpf. Calculate the value of RF.
2. Choose b = 20fa and calculate the values of Ri and CF SO that Ri Ci = Rr CF.
13
 Precision Rectifier:

The ordinary diodes cannot rectify voltages below the cut-in-voltage of the diode. A circuit which
can act as an ideal diode or precision signal — processing rectifier circuit for rectifying voltages which are
below the level of cut-in voltage of the diode can be designed by placing the diode in the feedback loop of
an op-amp. Precision diodes:

Figure shows the arrangement of a precision diode. It is a single diode arrangement and functions
as a non-inverting precision half— wave rectifier circuit.
If V1 in the circuit of figure is positive, the op-amp output VOA also becomes positive. Then the closed
loop condition is achieved for the op-amp and the output voltage V0 = Vi When Vi < 0, the
voltage VOA becomes negative and the diode is reverse biased. The loop is then broken and the
output V0 = 0.

19
 Consider the open loop gain AOL of the op-amp is approximately 104 and the cut-in voltage Vy for
silicon diode is 0.7V. When the input voltage Vi > Vy / AOL, the output of the op-amp VOA
exceeds Vy and the diode D conducts.

Applications: The precision diodes are used in

half wave rectifier,
Full-wave rectifier,
peak value
detector,
Clipper and clamper circuits.
Disadvantage:
It can be observed that the precision diode as shown in figure operated in the first quadrant with Vi >
0 and V0 > 0. The operation in third quadrant can be achieved by connecting the diode in reverse
direction.
Half— wave Rectifier:

What is precision rectifier? With circuit schematic explain the working principles of half wave
rectifier. ( Nov 2007)

A non-saturating half wave precision rectifier circuit is shown in figure.

When Vi > 0V, the voltage at the inverting input becomes positive, forcing the output VOA to go
negative.
This results in forward biasing the diode D1 and the op-amp output drops only by 0.7V below the
inverting input voltage. Diode D2 becomes reverse biased. The output voltage V0 is zero when the
input is positive.
20
 When Vi > 0, the op-amp output VOA becomes positive, forward biasing the diode D2 and reverse
biasing the diode DI. The circuit then acts like an inverting amplifier circuit with a nonlinear diode
in the forward path. The gain of the circuit is unity when Rf= Ri
The circuit operation can mathematically be expressed
as V 0 = 0 when V i > 0 and
V 0 = Ri/RiVi forV i <0
The voltage VoA at the op amp output is VoA= - 0.7V for V i>0
VOA' RiVl + 0.7V for V i<0
Advantages:
It is a precision half wave rectifier and
lit is a non-saturating one.
The inverting characteristics of the output V0 can be circumvented by the use of an additional inversion for
achieving a positive output.
Full wave Rectifier:

What is precision rectifier? With circuit schematic explain the working principles of Full wave rectifier.
( Nov 2008)
The first part of the Full wave circuit is a half wave rectifier circuit. The second part of the circuit is an
inverting amplifier.

For positive input voltage Vi > 0V and assuming that RF =Ri = R, the output voltage VOA = Vi.
The voltage V0 appears as (-) input to the summing op-amp circuit formed by A2, The gain for the
input V‘0 is R/(R/2), as shown in figure.
The input Vi also appears as an input to the summing amplifier.

21
 Then, the net output is V0 =-Vi -2V0= -Vi -2(-Vi) = Vi. Since Vi > 0V, V0 will be positive, with
its input output characteristics in first quadrant.
For negative input Vi < 0V, the output V‘0 of the first part of rectifier circuit is zero. Thus, one input
of the summing circuit has a value of zero.
However, Vi is also applied as an input to the summer circuit formed by the op-amp A2.
The gain for this input id (-R/R) = -1, and hence the output is V0 = -Vi. Since Vi is negative, V0 will
be inverted and will thus be positive. This corresponds to the second quadrant of the circuit.
To summarize the operation of the
circuit, V0 = Vi when Vi < 0V
and
V0 = Vi for Vi > 0V, and
hence V0 = |Vi
Peak Detector
What is peak detector? Draw the circuit using op-amp.
Peak detector measures the +ve peak value of the square wave input.
Square, Triangular, Saw tooth and pulse waves are typical examples of non-sinusoidal waveforms.
A conventional AC voltmeter cannot be used to measure these sinusoidal waveforms because it is
designed to measure the RMS value of the pure sine wave.

One possible solution to this problem is to measure the peak values of the non-sinusoidal waveforms.
i) During the positive half cycle of Vin: the o/p of the op-amp drives DI on. (Forward biased)
Charging capacitor C to the positive peak value Vp of the input volt Vin.
ii) During the negative half cycle of Vin: D1 is reverse biased and voltage across C is retained. The
22
only discharge path for C is through RL since the input bias IB is negligible.

23
 For proper operation of the circuit, the charging time constant (CRd ) and discharging time constant
(CA) must satisfy the following condition.
CRd <= T/10
Where Rd = Resistance of the forward-biased diode.
T = time period of the input waveform.
CRL >= IOT
Where RL= load resistor.
Note: Negative peak of the input signal can be detected simply by reversing diode D1 and D2.
Clipper:

What is clipper? With circuit schematic explain the working of positive and negative clipper.

A circuit that removes parts of the input signal is called clipper. It can be formed by using an
op- amp with a rectifier diode.
Positive Clipper:

A circuit that removes positive parts of the input signal

can be formed by using an op-amp with a rectifier diode.
The clipping level is determined by the reference voltage
Vref.
if Vref < Vin, The Output voltage has the portions of the
positive half cycles above Vref clipped off.
Operation:
During the positive half cycle of the input, the diode DI
conducts only until Vin = Vref.
Output V0 follows input until Vin = Vref.
When Vin > Vref => the V0 becomes +ve to derive D1 into
off. It opens the feedback loop and op-amp operates
open loop.
When Vin drops below Vref(Vin<Vref) the o/p of the op-amp V0 again becomes —ve to device D1 into
conduction. It closes the feedback path. (o/p follows the i/p).
Thus diode DI is on for vin<Vref(o/p follows the i/p) and D1 is off for Vin>Vref.

24
Negative Clipper

The positive clipper is converted into a —ve clipper by simply reversing diode D1 and changing the
polarity of Vref voltage.
The negative clipper clips off the —ve parts of the input signal below the reference voltage.
Diode DI conducts -> when Vin > -Vref and therefore during this period o/p volt V0 follows the
input volt Vin.
The negative portion of the output volt below —Vref is clipped off because (DI is off) Vin<-Vref.
Positive and Negative Clampers:
In clamper circuits a predetermined dc level is added to the output voltage. (or) The output is
clamped to a desired dc level.
1. If the clamped dc level is +ve, the clamper is positive clamper
2. If the clamped dc level is —ve, the clamped is negative clamper.

25
Peak clamper:
In this circuit, the input waveform peak is clamped at Vref. For this reason, the circuit is called the
peak clamper.

First consider the input voltage Vref at the (+) input: since this volt is +ve, V‘0 is also +ve which
forward biases DI. This closed the feedback loop.
Voltage Vin at the (-) input: During its —ve half cycle, diode D1 conducts, charging c; to the —ve
peak value of Vp.
During the +ve half cycle, diode DI in reverse biased. Since this voltage Vp is in series with the
+ve peak volt Vp the o/p volt V0 = 2 Vp. Thus the nett o/p is Vref plus 2 Vp. So the — ve peak of 2
Vp is at Vref. For precision clamping, CiRd << T/2.
26
 Where Rd = resistance of diode D1 when it is forward biased.
T = time period of the input waveform.
Resistor R is used to protect the op-amp against excessive discharge currents from capacitor Ci
especially when the dc supply voltages are switched off. A +ve peak clamping is accomplished by
reversing D1 and using —ve reference voltage (-Vref).
Note: Inv and Non-lnv clamper — Fixed dc level, Peak clamper — Variable dc level
 Unit — III

Comparator
Explain the working of inverting and non-inverting comparator using op-amp.[Nov/Dec 2021]

A comparator compares a signal voltage on one input of an op-amp with a known voltage called a
reference voltage on the other input. Comparators are used in circuits such as,
• Digital Interfacing
• Schmitt Trigger
• Discriminator
• Voltage level detector and oscillators

Non-inverting Comparator:

A fixed reference voltage Vref of 1 V

is applied to the negative terminal and
time varying signal voltage Vin is
applied to the positive terminal.
When Vin is less than Vref the output
becomes V0 at —Vsat [Vin < Vref
V0 (-Vsat)]. =>

When Vin is greater than Vref, the (+) input becomes positive, V0 = +Vsat.
[Vin > Vref=> V0 (+Vsat)]. Thus the V0 changes from one saturation level to another.

29
 The diodes DI and D2 protect the op-amp from damage due to the excessive input voltage Vin.
Because of these diodes, the difference input voltage Vid of the op-amp diodes are called clamp
diodes. The resistance R in series with Vin is used to limit the current through DI and D2. To
reduce offset problems, a resistance Rcomp = R is connected between the (-ve) input and Vref.
Inverting Comparator:
This fig shows an inverting comparator in which the reference voltage Vref is applied to the (+)
input terminal and Vin is applied to the (-) input terminal.

In this circuit Vref is obtained by using a 10K potentiometer that forms a voltage divider with DC
supply volt +Vcc and -1 and the wiper connected to the input.

30
Applications:
Zero Crossing Detector: [ Sine wave to Square wave converter]
Explain how comparator work as a zero crossing detector. ( May 2004)
The basic comparator can be used as a zero crossing detector by setting Vref is set to Zero.
This Fig shows when in what direction an input signal Vin crosses zero volts. (i.e.) the output V0 is
driven into negative saturation when the input the signal Vin passes through zero in positive
direction. Similarly, when Vin passes through Zero in negative direction the output V0 switches
and saturates positively.
Analog Multiplier:
1.1 Introduction
• A multiplier is a circuit which produces output that is the product of two inputs applied.
• A circuit which performs multiplication of two analog voltages is called as analog multiplier.
• IfV, and V2were the two input analog voltages applied, then the output voltage Ve is given as
V = k Vt V2
Where, k is the scaling factor.
1.2 Modes of operation of a multiplier
• The modes of operation of multiplier tell about the restriction on polarity of one or both input
voltages V1 and V2 applied to multiplier. There were three modes
s• One quadrant multiplication
•t• Two quadrant multiplication
•t• Four quadrant multiplication
1.3 One quadrant
• Both input voltages Veand V2are restricted to positive polarity.
• That is, Veand V2must be positive as shown here. It uses
first quadrant.
1.4 Two quadrant
• In this mode, any one input voltage Vi or V2 is held positive and the other is allowed to swing in
both positive and negative polarity.
• It uses any two or four quadrants (Quadrant I and II or I and IV) as shown here.
1.5 Four quadrant (Gilbert cell)
• In this mode, both the input voltages Veand V2 are allowed to swing in both positive and negative
polarity.

• It uses all four quadrants and hence the same.

• The figure here shows the four quadrant multiplication.
1.6 Characteristics or requirements of a multiplier

List and define various performance parameters of multiplier DC. May 2012J
The following characteristics or requirements are very important for a multiplier to achieve maximum
efficiency. They are:
•t• Accuracy
•t• Linearity
•t• Squaring mode accuracy
•t• Bandwidth
•t• Quadrant
1.6.1 Accuracy
• The deviation of practical output from the ideal output of multiplier for the given input voltages
within the operating range of multiplier.
• This characteristic tells how accurate the multiplier is and whether the expected output is obtained
or not.
1.6.2 Linearity
• It is the maximum percentage deviation that a practical output compared with a linear straight line
output.
1.6.3 Squaring mode accuracy
• The accuracy of multiplier when both inputs tied together gives square — law curve.
• The deviation of practical squared output versus ideal square-law curve is squaring mode accuracy.
1.6.4 Bandwidth
• The operating capability of a multiplier for high frequency analog inputs is indicated with bandwidth.
 • Capability with high frequency indicates the improvement in bandwidth.

1.6.5 Quadrant
• It defines the unipolar or bipolar capabilities of input voltages applied.

1.7 Types of analog multipliers

The basic techniques to achieve multiplication are:
â• Logarithmic type
â• Quarter square type
•t• Pulse width / height modulation type
•t• Current rating type
•t• Triangle averaging type
•t• Emitter coupled transistor pair type
•i• Variable transconductance type
•°• Four quadrant type based on variable transconductance (or) Gilbert cell
1.8 Analog Multiplier ICs (Discuss briefly about analog multiplier.) [May 2018]
• Analog multiplier is a circuit whose output voltage at any instant is proportional to the product
of instantaneous value of two individual input voltages.

• Important applications of these multipliers are multiplication, division, squaring and square —
rooting of signals, modulation and demodulation.
• These analog multipliers are available as integrated circuits consisting of op-amps and other circuit
elements.
• The Schematic of a typical analog multiplier, namely, AD633 is shown in figure.

• The AD633 multiplier is a four — quadrant analog multiplier.

• It possesses high input impedance; this characteristic makes the loading effect on the signal
source negligible.
• It can operate with supply voltages ranging from +18V.
• The IC does not require external components.
• The typical range of the two input signals is +10V.
1.8.1 Schematic representation of a multiplier:
• The schematic representation of an analog multiplier is shown in figure.
• The output Vo is the product of the two inputs Vxand Vy iS divided by a reference voltage Vref•
 • Normally, the reference voltage VrefiS internally set to 10V.
• Therefore, Vo 'VxVyJ10•
• In other words, the basic input — output relationship can be defined by KVx Vy When K = 1/10,
a constant.
• Thus for peak input voltages of 10V, the peak magnitude of output voltage is 1/10 *10 *10
=10V.
• Thus, it can be noted that, as long as Vx< 10V and Vy < 10V, the multiplier output will not saturate.
1.8.2 Multiplier quadrants:
The transfer characteristics of a typical four-quadrant multiplier are shown in figure.
Both the inputs can be positive or negative to obtain the corresponding output as shown in the transfer
characteristics.
1.8.3 Applications of Multiplier ICs:
Sketch and explain the applications of multiplier.
IMay 2011J
The multiplier ICs are used for the following
purposes:
1. Voltage Squarer
2. Frequency doublers
3. Voltage divider
4. Square rooter
5. Phase angle detector
6. Rectifier
[Link] Voltage Squarer:

• Figure shows the multiplier IC connected as a squaring circuit.

• The inputs can be positive or negative, represent ed by any corresponding voltage level between 0
and 10V.
• The input voltage Vi to be squared is simply connected to both the input terminals.
• Hence we have, Vx' Vy' Viand the output is Ve' KVi2•
• The circuit thus performs the squaring operation.
• This application can be extended for frequency doubling applications.
1.8.3.2Frequency doublers:
How the multiplier IC used as the frequency doubler? May 2012J
• The figure shows the squaring circuit connected for frequency doubling
operation.
• A sine-wave signal Vi has a peak amplitude of A, and frequency of fHz.
• Then, the output voltage of the doublers circuit is given by

• Assuming a peak amplitude Ag of 5V and frequency f of 10 KHz, Vo=1.25 — 1.25 cos2z (20000) t.
• The first term represents the dc term of 1.25V peak amplitude.
• The input and output waveforms are shown in figure.

• The output waveforms ripple with twice the input frequency in the rectified output of the input
signal.
• This forms the principle of application of analog multiplier as rectifier of ac signals.

• The dc component of output V can be removed by connecting a lpF coupling capacitor between
the output terminal and a load resistor, across which the output can be observed.
[Link] Voltage Divider:
Voltage divider can be implemented by connecting a multiplier in the feedback loop of an op-amp as
 shown in the figure.
• Vnum is the numerator voltage and Vden is the denominator voltage.
• Note that node ‘a’ is at virtual ground and other end ofRc is physically grounded.

• From the diagram,

1j + 12' 0

substituting in' VnumI R; i2' V q/R

Vnumt R + V jjy / R 0

V = k VOAVden' Vnum

Where, V is the output of multiplier with two inputs VoAand Vden

VOA' Vnum/ [Link]

K is the scale factor.

• Thus VoAfrom op-amp is the divided voltage.
• This feature is used in automatic gain control (AGC) circuits.
[Link] Square Rooter:
• The divider voltage can be used to find the square root of a signal by connecting both inputs of
the multiplier to the output of the op-amp.
• Substituting equal in magnitude but opposite in polarity (with respect to ground) to Vi•
• But we know that V is one - term (Scale factor) of V0* V or -Vi' V o m' V2/ 10.
• Solving for Veand eliminating 1-1 yields.
Vo' 10. |Vt
• The equation states that Ve equals the square root of 10 times the absolute magnitude of Vi•
• The input voltage Vi must be negative, or else, the op-amp saturates.
• The range of Vi is between -1 and -10V. Voltages less than -1V will cause inaccuracies in the result.
• The diode prevents negative saturation for positive polarity Vi signals.
• For positive values of Vi the diode connections are reversed.
1.8.3.5Phase Angle detector: Explain the operation of phase detector with relevant sketches.[Nov/Dec 2022]
• The multiplier configured for phase angle detection measurement is shown in figure.
• When two sine - waves of the same frequency are applied to the inputs of the multiplier, the
output Vo has a dc component and an AC component.
• The trigonometric identity shows that Sin A sin B =l/2 (cos (A-B) — cos (A+B)).
• When the two frequencies are equal, but with different phase angles,
E.g. A = 2nft + 8 for signal Vxand B = 2nft for signal Vy9
• Then using the identity
[Sin (2zfi + 8)][Sin2zfr)] =1/2 [cos 8 —cos (4 rift + 8 )]
= 'Z2 (dc- ac frequency term).
• Therefore, when the two input signals Vxand Vy die applied to the multiplier, Ve(dc) is given by

• Where App and Typ 8re the peak voltage amplitudes of the signals Vxfind Vy•
• Thus, the output V0(dc) depends on the factor cos 8.
• A dc voltmeter can be calibrated as a phase angle meter when the product of Vgp and Vp is made
equal to 20.
• Then, a (0-1) V range dc voltmeter can directly read cos 8, with the meter calibrated directly in
degrees from a cosine table.
• The input and output waveforms are shown in figure.
• Then the above eqn becomes Vo(dc) = cos 8, if we make the product VxpVyp' 20 or in other words,
Vgp Vyp' 4.47V.

Fig• Phase angle measurement circuit diagram

 Fig• input- output waveforms of phase angle detector

Schmitt Trigger: [Square Circuit]

Explain the operation of schmitt trigger. ( Nov 2008, Dec 2018)
Describe the circuit and working of a square-wave generator. [Nov/Dec 2021] [Nov/Dec 2022]

18
 This circuit converts an irregular shaped waveform to a square wave or pulse. The input voltage
Vin triggers (changes the state of) the output Vo every time it exceeds certain voltage levels called the
upper threshold Vut and lower threshold Vlt voltage.
These threshold voltages are obtained by using the voltage divider RI— R2, where the voltage across
Ri is feedback to the (+) input.
The voltage across Riis variable reference threshold voltage that depends on the value of the output
voltage. When V0 = +Vsat, the voltage across RI is called upper threshold voltage Vut.
z The input voltage Vin must be more positive than Vut in order to cause the output V0 to switch from
+Vsat to -Vsat using voltage divider rule, Voltage at (+) input terminal is
VU Vref+ (Vsat-Vref)/(R1+Rz) when Vo= +vsat.
When v0= -vsat. Hysteris width VH= VUT - VLT' 2 W (Vsat)/ (R1+ )
When V0 = -Vsat, the voltage across RI is called lower threshold voltage Vlt .the Vin must be
more negative than Vlt in order to cause V0 to switch from —Vsat to +Vsat. for Vin > Vlt , V0 is at
—Vsat.
Voltage at (+) terminal iS VLT Vref- (Vsat+Vref)/(R1+ ).

• If the threshold voltages Vut and Vlt are made larger than the input noise voltages, the positive
feedback will eliminate the false output transitions.
• Also the positive feedback, because of its regenerative action, will make V0 switch faster between
+Vsat and —Vsat.
• Resistance Rcomp=R1 || R2 is used to minimize the offset problems.

18
 Active filters:
An electric filter is circuit that passes a specified band of frequencies and blocks signal at
frequencies outside this band.
Depending on the type of elements used in their construction, filter may be classified as passive or
Active elements used in passive filters are Resistors, capacitors, inductors. Elements used in active filters
are transistor, or op-amp.
Active filters offer the following advantages over passive filters:
1. Gain and Frequency adjustment flexibility.
2. No loading problem:
3. Cost: Active filters are more economical than passive
filter. The most commonly used filters are these:
1. Low pass Filters
2. High pass Filters
3. Band pass filters
4. Band —reject filters
5. All pass filters.
Frequency response of the active filters:
Compare the frequency response of Active filters. ( Nov 2016)

18
Design First order Low Pass Butterworth filter: (Dec 2018)
First order LPF that uses an RC for filtering op-amp is used in the non-inverting configuration.
Resistor R1 & Rf determine the gain of the filter.

Gain A= (1+WRi)
Voltage across capacitor Vi= Vi / (1+j2nfRC)
Output voltage V0 for non inverting amplifier =AVi = (1+Rt/Ri) VG(1+j2nfRC)
Overall gain V0/Vi = (1+Rf/R1) Vi/(1+j2zfRC
Transfer function H(s) =A/(jf/R+1) if R -1/2nRC
H (jm) = A/(j RC+1) = A/(j RC+1).
Filter design:
A LPF can be designed by implementing the following steps.
1. Choose a value of high cut off frequency fH.
2. Select a value of C less than or equal to lpf.
3. Choose the value of R using fh=1/2nRC
4. Finally select values of R1 and RF dependent on the desired pass band gain AF Using A= (1+Rf/R1)

18
EC8453 / Linear Integrated Circuits UNIT-2
Second order Low Pass Butterworth filter:

Filter Design:
1. Choose a value for a high cut off freq. (fH ).
2. To simplify the design calculations, set R2 = R3 = R and C2 = C3 = C then choose a value of C<=1pf.
3. Calculate the value of R, fi =1/2nRC
4. Finally, because of the equal resistor (R2 = R3) and capacitor (C2 = C3 ) values, the pass band volt gain
AF = 1 + RF / RI of the second order had to be = to 1.586. RF = 0.586 RI. Hence choose a value of
R1<=100kf2.
5. Calculate the value of RF.
First order High Pass Butterworth filter:
High pass filters are formed by interchanging frequency-determining resistors and capacitors in
low- pass filters.

At high frequencies f>fL gain = A.

At f= fL gain = 0.707 A.
At f < fL the gain decreases at a rate of -20 db
/decade. The frequency below cutoff frequency is

18
stop band.

18
 Second — order High Pass Butterworth Filter:

Band pass filters

Filters that pass band of frequencies and attenuates others. Its high cutoff frequency and low
cutoff frequency are related as fH >fL and maximum gain at resonant frequency fa fH fL
Figure of merit Q= fr/ (fH- fL) = f/B where B= bandwidth.
Two types of filters are Narrow band pass and wide band pass filters
Wide band pass filter:
It is connection of a low pass filter and a high pass filter in cascade. The fH of low pass filter and fL Of
high pass filter are related as fH > fL.

1. Design an op amp differentiator that will differentiate an input signal with fmax= 100Hz.
[Nov/Dec 2021] [Nov/Dec 2022]

100 = 1/(
2*3.14*0.1*R) R =
1/(0.628*100)
R= 0.015Ohm.
 NIT-5
.
Sine Wave Generators (Oscillators)
Explain sine wave oscillators using op-amp.

Sine wave oscillator circuits use phase shifting techniques that usually
employ Two RC tuning networks, and
Complex amplitude limiting circuitry
RC Phase Shift Oscillator:
Q. Explain the circuit of a RC phase shift oscillator. [Nov/Dec 2021]

Fig.5.3 RC Phase shift oscillator

RC phase shift oscillator using op-amp in inverting amplifier introduces the phase shift of 1800
between input and output. The feedback network consists of 3 RC sections each producing 600 phase shift.
Such a RC phase shift oscillator using op-amp is shown in the figure.
The output of amplifier is given to feedback network. The output of feedback network drives the
amplifier. The total phase shift around a loop is 1800 of amplifier and 1800 due to 3 RC sections, thus 3600
. This satisfies the required condition for positive feedback and circuit works as an oscillator.
Frequency of oscillation f=1/2zRC
Wien Bridge Oscillator Q. Explain the operation of a Wein bridge oscillator with neat sketches.[Nov/Dec
2022] Figure give the Wien-bridge circuit configuration. The loop is broken at the positive input.

2
 UNIT-5

When m = 2zf = 1/RC, the feedback is in phase (this is positive feedback), and the gain is 1/3, so
oscillation requires an amplifier with a gain of 3. When RF = 2RG, the amplifier gain is 3 and oscillation
occurs at f= 1/2nRC. The circuit oscillated at 1.65 kHz rather than 1.59 kHz with the component values
shown in Figure , but the distortion is noticeable.
If a resistor is placed in parallel with the amplifier input, it will cancel some of the negative resistance.
If the net resistance is negative, amplitude will grow until clipping occurs.
Similarly, if the net resistance is positive, oscillation amplitude will decay. If a resistance is added
in parallel with exactly the value of fi, the net resistance will be infinite and the circuit can sustain stable
oscillation at any amplitude allowed by the amplifier.
Increasing the gain makes the net resistance more negative, which increases amplitude. If gain is
reduced to exactly 3 when suitable amplitude is reached, stable, low distortion oscillations will result.
Amplitude stabilization circuits typically increase gain until suitable output amplitude is reached.
As long as fi, C, and the amplifier are linear, distortion will be minimal.
Multivibrator
Astable Multivibrator
Explain astable multivibrator using op-amp. (May 2014)

The two states of circuit are only stable for a limited time and the circuit switches between them
with the output alternating between positive and negative saturation values.
 UNIT-5

Analysis of this circuit starts with the assumption that at time i=0 the output has just switched to
state 1, and the transition would have occurred.
An op-amp Astable multivibrator is also called as free running oscillator. The basic principle of
generation of square wave is to force an op-amp to operate in the saturation region (+Vsat).
A fraction § =R2/(R1+R2) of the output is feedback to the positive input terminal of op-amp. The
charge in the capacitor increases & decreases upto a threshold value called +§Vsat.
The charge in the capacitor triggers the op-amp to stay either at +Vsat or —Vsat.
Asymmetrical square wave can also be generated with the help of Zener diodes. Astable multi
vibrator do not require a external trigger pulse for its operation & output toggles from one state to another
and does not contain a stable state.
Astable multivibrator is mainly used in timing applications & waveforms generators.
Design
1. The expression of fo is obtained from the charging period t1 & t2 of capacitor
as T=2RC In (R1+2R2)/R1
2. To simplify the above expression, the value of R1 & R2 should be taken as R2 =
1.16R Such that fo simplifies to fo =1/2RC.
3. Assume the value of RI and find R2.
4. Assume the value of C & Determine R from fo =1/2fi C
5. Calculate the threshold point from §VSAT-

4
 UNIT-5

Monostable Multivibrator using Op-amp

Explain with neat diagram the monostable multivibrator using op-amp. (Dec 2015)

A multivibrator which has only one stable and the other is quasi stable state is called as Monostable
multivibrator or one-short multivibrator. This circuit is useful for generating signal output pulse of
adjustable time duration in response to a triggering signal.

5
 UNIT-5

The width of the output pulse depends only on the external components connected to the
opamp. Usually a negative trigger pulse is given to make the output switch to other state. But, it then return
to its stable state after a time interval determining by circuit components.
The pulse width T can be given as T = 0.69RC. For Monostable operation the triggering pulse width
Tp should be less then T, the pulse width of Monostable multivibrator. This circuit is also called as time
delay circuit or gating circuit.

Triangular Wave Generator Circuit

Explain triangular wave generator with neat diagram.

6
 UNIT-5

This signal generator gives two waveforms: a triangle-wave and a square- wave. The central
component of this circuit is the integrator capacitor CI. Basically we are interested in performing two
functions on CI: charge it, discharge it - repeat indefinitely. The output waveforms are shown here and it
is apparent that a square wave generator followed by an integrator acts as a triangular wave generator.

Saw-Tooth Wave Generator

Explain sawtooth wave generator with neat diagram.

The saw tooth wave oscillator which used the operational amplifier. The composition of this circuit is
the same as the triangular wave oscillator basically and is using two operational amplifiers.
 UNIT-5

At the circuit diagram above, IC(1/2) is the Schmitt circuit and IC(2/2) is the Integration circuit.
The difference with the triangular wave oscillator is to be changing the time of the charging and the
discharging of the capacitor. When the output of IC (1/2) is positive voltage, it charges rapidly by the
small resistance (RI) value. (When the integration output voltage falls) When the output of IC(1/2) is
negative voltage, it is made to charge gradually at the big resistance(R2) value.
The output waveform of the integration circuit becomes a form like the tooth of the saw. Such
voltage is used for the control of the electron beam (the scanning line) of the television, When picturing a
picture at the cathode-ray tube, an electron beam is moved comparative slow. (When the electron beam
moves from the left to the right on the screen). When turning back, it is rapidly moved.(When moving
from the right to the left).
Like the triangular wave oscillator, the line voltage needs both of the positive power supply and the
negative power supply. Also, to work in the oscillation, the condition of R3>R4 is necessary.
However, when making the value of R4 small compared with R3, the output voltage becomes
small. The near value is good for R3 and R4 The oscillation frequency can be calculated by the following
formula. With the circuit diagram,the oscillation frequency is as follows.
f= (1/2C (R1+R2))*(R3/R4)
= (1/(2x0.1x10-6x(5.6x103+100x103))x(120x103/100x103)
= (1/(21.12x10-3))x1.2
= 56.8 Hz
Function Generator IC 8038
Explain with block diagram the function generator IC 8038.

8
 UNIT-5

Triangular wave

line wave

Square wave

It consists of two current sources, two comparators, two buffers, one FF and a sine wave converter.
Pin description:
Pin 1 & Pin 12: Sine wave [Link]: The distortion in the sine wave output can be reduced by adjusting
the 100KD pots connected between pinl2 & pinl 1 and between pin 1 & 6.
Pin 2 Sine Wave Output: Sine wave output is available at this pin. The amplitude of this sine wave is
0.22 Vcc. Where 5V < Vcc < + 15 V.
Pin 3 Triangular Wave output: Triangular wave is available at this pin. The amplitude of the triangular
wave is 0.33Vcc. Where 5V Vcc 15 V.
Pin 4 & Pin S Duty cycle / Frequency adjust: The symmetry of all the output wave forms & 50% duty
cycle for the square wave output is adjusted by the external resistors connected from Vcc to pin 4. These
external resistors & capacitors at pin 10 will decide the frequency of the output wave forms.
Pin 6 + Vcc: Positive supply voltage the value of which is between 10 & 30V is applied to this
pin. Pin 7 : FM Bias: This pin along with pin no8 is used to TEST the IC 8038.
Pin9 : Square Wave Output: A square wave output is available at this pin. It is an open collector output
so that this pin can be connected through the load to different power supply voltages. This arrangement is
very useful in making the square wave output.
Pin 10 : Timing Capacitors: The external capacitor C connected to this pin will decide the output
frequency along with the resistors connected to pin 4 & 5.
Pin 11 : -VEE or Ground: If a single polarity supply is to be used then this pin is connected to supply
ground & if(+) supply voltages are to be used then (-) supply is connected to this pin.
Pin 13 & Pin 14: NC (No Connection)

9
 UNIT-5
Important features of IC 8038:
1. All the outputs are simultaneously available.
2. Frequency range : 0.001Hz to 500kHz
3. Low distortion in the output wave forms.
4. Low frequency drifts due to change in temperature.
5. Easy to
use.
Parameters:
(i) Frequency of the output wave form: The output frequency dependent on the values of resistors R1 &
R2 along with the external capacitor C connected at pin 10.
If RA= RB = R & if RC is adjusted for 50% duty cycle then f0= 0.3/RC; RA = Rl, RB = R3, RC= R2.
(ii) Duty cycle / Frequency Adjust : (Pin 4 & 5): Duty cycle as well as the frequency of the output wave
form can be adjusted by external resistors at pin 4 & 5.
The values of resistors RA & RB connected between Vcc pin 4 & 5 respectively along with the capacitor
connected at pin 10 decide the frequency of the wave form. The values of RA & RB should be in the range
of l kD to l MW.
(iii) FM Bias:
The FM Bias input (pin7) corresponds to the junction of resistors R1 & R2.
The voltage Vin is the voltage between Vcc & pin8 and it decides the output frequency.
The output frequency is proportional to Vin as given by the following expression.
For RA = RB (50% duty cycle).
f0= 5 Vin/CRAVcc ; where C is the timing capacitor.
With pin 7 & 8 connected to each other the output frequency is given by f0— 0.3/RC where R = RA = RB
for 50% duty cycle.
This is because M Sweep input (pin 8):
Vin=Rl Vcc/R1+R2
This inpui should be connected to pin 7, if we want a constant output frequency.
But if the output frequency is supposed to vary. then a variable dc voltage should be applied to this pin.
The voltage between Vcc & pin 8 is called Vin and it decides the output frequency as, D=1.5
Vin/CRAVCC A potentiometer can be connected to this pin to obtain the required variable voltage
required to change the output frequency.

10
 UNIT IV

1.9 Operation of Basic Phase Locked LoOp [April/May 2024] [Dec 2018]

What are the important building blocks of PLL? Explain its working. [May 2018]/3fo.y 2010 Nov 2010J
The basic PLL block diagram consists of three components connected in a feedback loop:
• A phase detector (PD) or phase frequency detector (PFD)
• A voltage-controlled oscillator (VCO)
• A loop filter (LF)

The phase detector produces a signal VQ proportional to the phase difference between the
incoming signal and the VCO output signal.
The output of the phase detector is filtered by a low-pass loop filter.
The filter output voltage V0 controls the frequency of the VCO.
 The voltage at the input of the VCO determines the frequency osc of the periodic signal Vosc
at the output of the VCO.
A basic property of the PLL is that it attempts to maintain the frequency lock fosc Hi between Vosc
and Vi even if the frequency fi of the incoming signal varies in time.
Suppose that the PLL is in the locked condition, and that the frequency Hi of the incoming
signal increases slightly.
The phase difference between the VCO signal and the incoming signal will begin to increase in
time.
As a result, the filter output voltage V increases.
The VCO output frequency fast increases until it matches f , thus keeping the PLL in the locked
condition.
1.9.1 Locked Range and Capture Range of the PLL:
• Locked condition: f s - f1
• Unlocked condition: f s = f = const

1.9.2 Lock Range of the PLL:

With Usual notations, show that the ’lock-in-range’ of PLL is b s — -£ [Link] <- f> Dec 2011J
• The range of frequencies from ft = fj2iin tO fj = fj2qax Where the locked PLL remains in the locked
condition.
• The lock range is wider than the capture range.
» If the PLL is initially locked, and if fi < fin, or ft > fmax.
• The PLL becomes unlocked at fi / fosc-
• When the PLL is unlocked, the VCO oscillates at the frequency fo called the center frequency, or
the free- running frequency of the VCO.
• If ‹p radians are the phase difference between the signal and the VCO voltage, then the output
voltage of the analog phase detector is given by,
be' (Q If/2)---------------------------------------------------------- (1)

Wliere,Kp is the phase angle-to-voltage transfer coefficient of the phase detector.

• The control voltage to VCO is,
v‹= (q — n/2)
---- (2)
Where, A is the voltage gain of the
amplifier.
• This r‹shifts VCO frequency from its free running frequency f to a frequency f given by,
f = f + Kev-----------------------------------------------(3)
 Where, K is the voltage to frequency transfer coefficient of the
VCO.
• When PLL is locked-in to signal frequency fo. then we have
(4)
• Since,
------------------(5)
• Thus,
------------------(6)

• The maximum output voltage magnitude available from the phase detector occurs for p = n and 0
radian and e(maX) = +Yp. rr/2The corresponding value of the maximum control voltage available to

drive the VCO will be,

(7)

• The maximum VCO frequency swing that can be obtained is given by,
(8)

• Therefore, the maximum range of signal frequencies over which the PLL can remain locked will be,

' to * KAKO A )' to ‹-------------------------------(9)

Where 2 fiJtwill be lock-in frequency range and is given by,

Lock-in range = 2 b fi — Kv KqAu----------------------------- (10)

• The lock in range is symmetrically located with respect to VCO free running frequencyl0. For IC
PLL 565,

.Kv

Where, ' + cc (‘dcc)

Again, 14
Kp — '

And A = 1.4
• Hence the lock-in range from eqn (11) becomes,
f +7 8 o -------------------(12)

1.9.3 Capture Range of the PLL:

Derive the expression for the capture range of PLL.

• When PLL is not initially locked to the signal, the frequency of the VCO will be free running
frequency f . The phase angle difference between the signal and the VCO output voltage will be,
 r = (=,t * ®,) — (=, + *o) = (•', — =o) + °®---------------------------------(i3)
• Thus the phase angle difference does not remain constant but will change with time at a rate given by
(14)

• The phase detector output voltage will therefore not have a dc component but will produce an ac
voltage with a triangular waveform of peak amplitude Kp ( ) and a fundamental

frequency(J I ) ' *f
• The low pass filter (LPF) is a simple RC network having transfer function

T(jf) -------- (15)

Where, fl = ’/› u RC is the 3 dB point of LPF. In the slope portion of LPF where (ffl)2 >> 1, then
----(16)

• The fundamental frequency term supplied to the LPF by the phase detector will be the difference
frequency ñJ = :t—.
/-o lfA > 3Jt, the LPF transfer function will be approximately,
T h f) ’ ft/b f — :$i/ I f°o) ‘-----------------(17)
• The voltage veto drive the VCO is,

(18)

[From eqn.7]-----------------(19)

• Then the corresponding value of the maximum VCO frequency shift is,
(20)

• For the acquisition of signal frequency, we should put f = ft so that the maximum signal frequency
range that can be acquired by PLL is,

if to)«' + Kv Jp ( ) fi(f1/°f*) - (21)

• Now,
• SO,

(fiJ,)' = UK Kp )—) A:I [from eqn.21]

We get, is,

• Therefore, the total capture range

-----------------(22)
 • Where the lock-in range =
• In case of IC PLL 565, R = 3.6 K , so the capture range is

(23)
Where, C is in farads.
• The capture range is symmetrically located with respect to VCO free running frequency fo as
shown in the figure below.

Figure: PLL lock in range and capture range

• The PLL cannot acquire a signal outside the capture range, but once captured, it will hold on till
the signal frequency goes beyond the lock-in range.
• In order to increase the ability of lock-in range large capture range is required.
• However, a large capture range will make the PLL more susceptible to noise and undesirable signal.
• Hence a suitable compromise is often reached between these two opposing requirements of the capture
range.
• Many a times the LPF bandwidth is first set for a large value for initial acquisition of signal.
• Once the signal is captured, the bandwidth of LPF is reduced substantially.
• This will minimize the interference of undesirable signals and noise.
1.9.4 Phase Detector
• Phase detector compares the input frequency and VCO frequency and generates DC voltage.
• That is proportional to the phase difference between the two frequencies.
• Depending on whether the analog/digital phase detector is used, the PLL is called either an
analog/digital type respectively.
 • Even though most monolithic PLL integrated circuits use analog phase detectors.
E.g for Analog: Double-balanced mixer
E.g for digital: Ex-OR, Edge trigger, monolithic Phase detector.
1.9.5 Ex-OR Phase Detector:
• This uses an exclusive OR gate.
• The output of the Ex-OR gate is high only when f or Q is high.
• The DC output voltage of the Ex-OR phase detector is a function of the phase difference between
its two outputs.
• The maximum dc output voltage occurs when the phase difference is n radians or 180 degrees.
• The slope of the curve between 0 or H radians is the conversion gaill kp of the phase detector.
• For eg; if the Ex-OR gate uses a supply voltage Vcc = 5V, the conversion gain Kp is

1.9.6 Advantages of Edge Triggered Phase Detector over Ex-OR:

• The dc output voltage is linear over 2H radians or 360 degrees, but in Ex-OR it is II radians or 180
degrees.
• Better Capture, tracking & locking characteristics.
• Edge triggered type of phase detector using RS Flip — Flop is formed from a pair of cross coupled
NOR gates.
• RS FF is triggered, i.e., the output of the detector changes its logic state on the positive edge of
the inputs f & Q .
1.9.7 Monolithic Phase detector:
• It consists of2 digital phase detector, a charge pump and an amplifier.
• Phase detector 1 is used in applications that require zero frequency and phase difference at lock.
• In Phase detector 2, quadrature lock is desired.
• When detector 1 is used in the main loop, detector can also be used to indicate whether the main
loop is in lock or out of lock.
1.9.8 Low — Pass filter
• The function of the LPF is to remove the high frequency components in the output of the phase
detector and to remove the high frequency noise.
• LPF controls the characteristics of the phase locked loop. i.e., capture range, lock ranges, bandwidth.
1.9.9 Lock range (Tracking range):
• The lock range is defined as the range of frequencies over which the PLL system follows the
changes in the input frequency f.
 1.9.10 Capture range:
• Capture range is the frequency range in which the PLL acquires phase lock. Capture range is
always smaller than the lock range.
1.9.11 Filter Bandwidth:
• If filter b andwidth is reduced, its response time increases.
• However reduced Bandwidth reduces the capture range of the PLL.
• Reduced Bandwidth helps to keep the loop in lock through momentary losses of signal and also
minimizes noise.
1.9.12 Voltage Controlled Oscillator (VCO):
• The third section of PLL is the VCO.
• It generates an output frequency that is directly proportional to its input voltage.
• The maximum output frequency of NE/SE 566 is 500 KHz.
S4444STTTSSSSSSSSSSSSSSSSSSSSSSS4444STTTSSSSSSSSSSSSSSSSSSSSSSS4444STTTSSSSSSSSSSSSSSSSS
1.10 Closed Loop Analysis of PLL
Explain the closed loop analysis of PLL.
• Phase locked loops can also be analyzed as control systems by applying the Laplace transform.
• The loop response can be written as:

Where
8o is the output phase in radians
8i is the input phase in radians
Kp is the phase detector gain in volts per radian
Kv is the VCO gain in radians per volt-second
F(s) is the loop filter transfer function (dimensionless)
• The loop characteristics can be controlled by inserting different types of loop filters.
• The simplest filter is a one-pole RC circuit.
• The loop transfer function in this case is:

• The loop response becomes:

• This is the form of a classic harmonic oscillator.

 • The denominator can be related to that of a second order system:

Where,
§ is the damping factor
n is the natural frequency of the loop.
• For the one-pole RC filter,

• The loop natural frequency is a measure of the response time of the loop.
• The damping factor is a measure of the overshoot and ringing.
• Ideally, the natural frequency should be high and the damping factor should be near 0.707
(critical damping).
• With a single pole filter, it is not possible to control the loop frequency and damping factor
independently.
• For the case of critical damping,

• A slightly more effective filter, the lag-lead filter includes one pole and one zero.
• This can be realized with two resistors and one capacitor.
• The transfer function for this filter is

• This filter has two time constants ‹ - C( 1 + 2) 2

=C 2
• Substituting above yields the following natural frequency and damping factor

• The loop filter components can be calculated independently for a given natural frequency and
damping factor
 • Real world loop filter design can be much more complex.
E.g: Using higher order filters to reduce various types or source of phase noise.
1.10.1 Applications of PLL:
The PLL principle has been used in applications such as
FM stereo decoders
Motor speed control
Tracking filters
FM modulation and demodulation
FSK modulation
Frequency multiplier
Frequency synthesis
etc.,
1.10.2 Example of PLL ICs: 560 series (560, 561, 562, 564, 565 & 567).

1.11 Voltage Controlled Oscillator:

Briefly explain the working of voltage controlled oscillatop• [May 2018] IMOf 2010, 2011, Nov 2010, 2011J
1.11.1 Introduction
• A VCO is inbuilt in a PLL.
• The IC VCO is 566 IC.
• The frequency of oscillation is determined by external resistor and capacitor.
• It contains a current source, buffer, Schmitt trigger and an inverter.

Fig• Pin diagram of VCO

 Fig• Block diagram of VCO
1.11.2 Operation of a VCO
• The modulating input Vc is applied to constant source which generates current.
• The capacitor Ci charges and discharges due to the reference set at the non-inverting terminal of
op- itmp A2fTOHl 0.5 Vcc to 0.25 Vcc by resistor potential divider Ra Rb•
• If the output of buffer tries to exceed 0.5 Vcc the Schmitt trigger goes low and the capacitor
discharges until 0.25 Vpp.
• Again Schmitt trigger goes high state and this process repeats.
• The output of buffer is a triangle voltage and the output of inverter is a square wave.
• The output of Schmitt trigger is fed to constant current source to get a controlled current output to
charge and discharge Can
1.11.3 Calculation of free — running frequency [Dec 2018]
• The voltage change across the capacitor Cois Av = 0.255 V Ci.
• The rate of change of voltage across the capacitor is given as
i 0

C A

0•25VccC}
t
1

• The time period ‘T’ of the triangular waveform is 2At.

• The frequency of oscillation ft is,

f
 2At

0.25VccCi
2

0.5VccCi
Wh q 2(VC vC)
—C
ere
R}C}Vcc
• The output frequency thus depends on Vp, Rs& Ct.
1.11.4 Voltage to Frequency conversion factor
Af0
• V to F conversion factor is given as k, =

Where, AVc GChange in control voltage

Aft GChange in frequency due to change in Vc(AVc)
• Assuming that the free-running frequency of VCO is ft and the new frequency is forWe get,
Af= ft —
• From the previous analysis,

2(Vpp — V + AVE ) 2(Vcc Vc )

Af =
R{C]Vcc C] R Vcc

2AVC
Af = R,C,V„
Af 2AVc 2
N€iw kg=
AVc R CiVcc Vc R C]V
• From previous analysis,

2(Vcc 7
fo Vc )
& if VC = Vcc
R}C}Vcc 8
1
fo
4R,C,
K, can be written in terms of D as

p 8fo
K Vcc
1.11.5 Low pass filter
• The function of LPF in PLL is to remove high frequency harmonics or components generated in the
output of phase detector.
 • The bandwidth of the filter determines the response time and the capture range.

1.12 Monolithic Phase Locked Loops (PLL IC 565):

Discuss the principles of operations ofNE565 PLL circuit. [May 2018] May 2016, Nov 2016]
1.12.1 Pin Configuration of PLL IC 565

1.12.2 Basic Block Diagram Representation of IC 565 The

important electrical characteristics of the 565 PLL are,
• Operating frequency range• 0.001Hz to 500 KHz.
• Operating voltage range• +6 to +12v
• input level required for tracking: 10mv rms min to 3 Vpp lllax
• input impedances 10 K ohms typically.
• Output sink current.• lmA
• Output source current: 10 mA
 • The center frequency of the PLL is determined by the free running frequency of the VCO, which
is given by f = 1.2 / 4R Ci,where R s & Ci are an external resistor & a capacitor connected to
pins 8 & 9.
• The VCO free-running frequency fog is adjusted externally with Rs & Coto be at the center of
the input frequency range.
• Ci can be any value; Rt must have a value between 2 k ohms and 20 K ohms.
• Capacitor C2connected between 7 & +V.
• The filter capacitor C2 should be large enough to eliminate variations in the demodulated output
voltage in order to stabilize the VCO frequency.
• The lock range fL& capture range fcof PLL is given by,

Where Q = free running frequency of VCO

(Hz) V = (+Vcc) - (-Vcc) volts

1.13 Monolithic PLL IC 565 applications:

1.13.1 AM Demodulation:
Draw the circuit of PLL as AM detection and Plain its working. [Nov/Dec 2022]f3foy 2011, May 2012J

A PLL used to demodulate AM signals as shown in the figure below.

The PLL is locked to the carrier frequency of the incoming AM signal.
The output of VCO which has the same frequency as the carrier, but unmodulated is fed to
the multiplier.
Since VCO output is always 90 it is being fed to the multiplier.
This makes both the signals applied to the multiplier and the difference signals.
The demodulated output is obtained afler filtering high frequency components by the LPF.
Since the PLL responds only to the carrier frequencies which are very close to the VCO output,
a PLL AM detector exhibits high degree of selectivity and noise immunity which is not possible
with conventional peak detector type AM modulators.
1.13.2FM Demodulation:
Explain with neat block diagram, how PLL is used for FM demodulation. May 2012J
• If PLL is locked to a FM signal, the VCO tracks the instantaneous frequency of the input signal.
• The filtered error voltage which controls the VCO and maintains lock with the input signal is the
demodulated FM output.
• The VCO transfer characteristics determine the linearity of the demodulated output.
• Since, VCO used in IC PLL is highly linear, it is possible to realize highly linear FM demodulators.

1.13.3Frequency multiplication/division:

How PLL can be modeled as a frequency multiplier. May

2016J Brief the application ofPLL IC for frequency multiplication- [Nov/Dec 2021] [Nov/Dec
2022)fNOK2016J
• The block diagram shown below shows a frequency multiplier/divider using PLL.
• A divide by N network is inserted between the VCO output and the phase comparator input.
• In the locked state, the VCO output frequency f is given by fo' Nfs•
• The multiplication factor can be obtained by selecting a proper scaling factor N of the counter.
• Frequency multiplication can also be obtained by using PLL in its harmonic locking mode.
• If the input signal is rich in harmonics e.g. square wave, pulse train etc., then the VCO can be
directly locked to the n-th harmonic of the input signal without connecting any frequency divider
in between. However, as the amplitude of the higher order harmonics becomes less, effective
locking may not take place for high values of n.
• Typically n is kept less than 10.
 FSK Generator:
1.13.4 Draw the FSK modulator and demodulator and explain its
operation.[ ApriI2021]
The FSK generator is formed by using a 555 as an astable multivibrator, whose frequency is
controlled by the state of transistor Q
In other words, the output frequency of the FSK generator depends on the logic state of the
digital data input.
150 Hz is one the standards frequencies at which the data are commonly transmitted.
When the input is logic 1, the transistor Q is off.
Under the condition, 555 timer works in its normal mode as an astable multivibrator.
i.e., capacitor C charges through RA& RBto 2/3 Vcc & discharges through RBto 1/3 View
Thus capacitor C charges & discharges between 2/3 Vol& 1/3 Vp as long as the input is logic
1. The frequency of the output waveform is given by,

When the input is logic 0, (Q is ON saturated) which in turn connects the resistance across
RA•

This action reduces the charging time of capacitor Cl increases the output frequency, which is
given by,

By proper selection of resistance , this frequency is adjusted to equal the space frequency of
1270 Hz.
The difference between the FSK signals of 1070 Hz & 1270 Hz is 200 Hz, this difference is called
“frequency shift”.
The output 150 Hz can be made by connecting a voltage comparator between the output of the
ladder filter and pin 6 of PLL.
The VCO frequency is adjusted with R, so that at f = 1070 Hz.
1.13.5FSK Demodulation:
Explain how IC 565 PLL can be used as FSK demodulator. fNov 2011J

The output of 555 FSK generators is applied to the 565 FSK demodulator.
Capacitive coupling is used at the input to remove dc line.
At the input of 565, the loop locks to the input frequency & tracks it between the 2
frequencies. R, & Ci determine the free running frequency of the VCO.
3 stages RC ladder filter is used to remove the carrier component from the output.
1.13.6 Frequency translation: Explain frequency translation using
PLL.[Nov/Dec2021]
The frequency translation means shifting the frequency of an oscillator by a small factor.
The figure below shows the block schematic for frequency translator using PLL.
It consists of mixer, low pass filter and the PLL.
The input frequency fs which have to be shifted are applied to the mixer.
Another input to the mixer is the output voltage of VCO, f0.
Therefore, the output of mixer contains the sum and difference signal (f0 + fS).
The low pass filter connected at the output of mixer rejects the (f0 + fS) signal and gives only (f0
— fs) signal at the output.
The (f0 — fS) signal is applied to the phase detector.
Another input for phase detector is the offset frequency f .
In the locked mode, the VCO output frequency is adjusted to make two input frequencies of
phase detector equal.
1.13.7Frequency Synthesizer:
Explain with neat block diagram, how PLL used for frequency synthesiser. [Dec 2018] May 2012J
A phase locked loop compares the frequencies of two signals.
I t produces an error signal which is proportional to the difference between the input
frequencies. The error signal is then low pass filtered and used to drive a voltage-controlled
oscillator (VCO) which creates an output frequency.
The output frequency is fed through a frequency divider back to the input of the system,
producing a negative feedback loop.
If the output frequency drifts, the error signal will increase, driving the frequency in the
opposite direction so as to reduce the error.
Thus the output is locked to the frequency at the other input.
This input is called the reference and is derived from a crystal oscillator, which is very
stable in frequency.
The block diagram below shows the basic elements and arrangement of a PLL based
frequency synthesizer.

The
key to the ability of a frequency synthesizer to generate multiple frequencies is the divider
placed between the output and the feedback input.
This is usually in the form of a digital counter, with the output signal acting as a clock signal.
The counter is preset to some initial count value, and counts down at each cycle of the clock
signal.
When it reaches zero, the counter output changes state and the count value is reloaded.
This circuit is straightforward to implement using flip-flops.
It is digital in nature.
It is very easy to interface to other digital components or a microprocessor.
This allows the frequency output by the synthesizer to be easily controlled by a digital system.

nated through differential operation.

Limitations:
On the other hand, series sampling suffers from the nonlinearity of the parasitic capacitance at node Y.

The 555 Timer IC

Explain the basic functions of 555 timer IC.

The 555 is a monolithic timing circuit that can produce accurate & highly stable time delays or
oscillation. The timer basically operates in one of two modes: either
(i) Monostable (one - shot) multivibrator or
(ii) Astable (free running) multivibrator
The important features of the 555 timer are these:
(i) It operates on +5v to +18 v supply voltages
(ii) It has an adjustable duty cycle
(iii) Timing is from microseconds to hours
(iv) It has a current o/p

Pin description:
Pin 1: Ground: All voltages are measured with respect to this terminal.
Pin 2: Trigger: The o/p of the timer depends on the amplitude of the external trigger pulse applied to this
pin. Pin 3: Output: There are 2 ways a load can be connected to the o/p terminal either between pin3 &
ground or between pin 3 & supply voltage (Between Pin 3 & Ground ON load) (Between Pin 3 & + Vcc
OFF load)
(i) When the input is low: The load current flows through the load connected between Pin 3 & +Vec in to
the output terminal & is called the sink current.
(ii) When the output is high: The current through the load connected between Pin 3 & +Vcc (i.e. ON load)
is zero. However the output terminal supplies current to the normally OFF load. This current is called the
source current.
 UNIT-5

Pin 4: Reset: The 555 timer can be reset (disabled) by applying a negative pulse to this pin. When the reset
function is not in use, the reset terminal should be connected to +Vcc to avoid any false triggering.
Pin 5: Control voltage: An external voltage applied to this terminal changes the threshold as well as trigger
voltage. In other words by connecting a potentiometer between this pin & GND, the pulse width of the
output waveform can be varied. When not used, the control pin should be bypassed to ground with 0.01
capacitor to prevent any noise problems.
Pin 6: Threshold: This is the non inverting input terminal of upper comparator which monitors the voltage
across the external capacitor.
Pin 7: Discharge: This pin is connected internally to the collector of transistor Q1. When the output is high
Q1 is OFF. When the output is low Q is (saturated) ON.
Pin 8: +Vcc: The supply voltage of +5V to +18V is applied to this pin with respect to ground.

From the above figure, three 5k internal resistors act as voltage divider providing bias voltage of
2/3 Vcc to the upper comparator & 1/3 Vcc to the lower comparator. It is possible to vary time
electronically by applying a modulation voltage to the control voltage input terminal (5).
(i) In the Stable state: The output of the control FF is high. This means that the output is low because of
power amplifier which is basically an inverter. Q = 1; Output = 0
 UNIT-5

(ii) At the Negative going trigger pulse: The trigger passes through (Vcc/3) the output of the lower
comparator goes high & sets the FF. Q = 1; Q = 0
(iii) At the Positive going trigger pulse: It passes through 2/3Vcc, the output of the upper comparator goes
high and resets the FF. Q = 0; Q = 1 The reset input (pin 4) provides a mechanism to reset the FF in a
manner which overrides the effect of any instruction coming to FF from lower comparator.
Monostable Operation
Explain the monostable operation of 555 timer.
 UNIT-5

Initially when the output is low, i.e. the circuit is in a stable state, transistor Q1 is ON & capacitor
C is shorted to ground. The output remains low. During negative going trigger pulse, transistor Q1 is OFF,
which releases the short circuit across the external capacitor C & drives the output high. Now the capacitor
C starts charging toward Vcc through RA.
When the voltage across the capacitor equals 2/3 Vcc, upper comparator switches from low to high.
i.e. Q = 0, the transistor Ql = OFF ; the output is high. Since C is unclamped, voltage across it rises
exponentially through R towards Vcc with a time constant RC (fig b) as shown in below. After the time
period, the upper comparator resets the FF, i.e. Q = 1, Q1 = ON; the output is low.[i.e discharging the
capacitor C to ground potential (fig c)]. The voltage across the capacitor as in fig (b) is given by
Ve = Vcc (1-e-t/RC) (1)
Therefore At t = T, Vc = 2/3
Vcc 2/3 Vcc = Vcc(I-e-T/RC)
or
T = RC ln (1/3)
Or
T = 1.1RC seconds....................(2)
If the reset is applied Q2 = OFF, Q1 = ON, timing capacitor C immediately discharged. The output
now will be as in figure (d & e). If the reset is released output will still remain low until a negative going
trigger pulse is again applied at pin 2.

Astable Multivibrator:
Explain the operation of astable multivibrator sing 555 timer.

An Astable multivibrator, often called a free running multivibrator, is a rectangular wave

generating circuit. Unlike the monostable multivibrator, this circuit does not require an external trigger to
change the state of the output, hence the name free running.
However, the time during which the output is either high or low is determined by 2 resistors and
capacitors, which are externally connected to the 55 timer.
 UNIT-5

The above figures show the 555 timer connected as an astable multivibrator and its model graph.
Initially, when the output is high :
Capacitor C starts charging toward Vcc through RA & RB. However, as soon as voltage across the
capacitor equals 2/3 Vcc. Upper comparator triggers the FF & output switches low.
When the output becomes Low:
Capacitor C starts discharging through RB and transistor Q1, when the voltage across C equals 1/3
Vcc, lower comparator output triggers the FF & the output goes high. Then cycle repeats. The capacitor is
periodically charged & discharged between 2/3 Vcc & 1/3 Vcc respectively. The time during which the
capacitor charges from 1/3 Vcc to 2/3 Vcc equal to the time the output is high & is given by
tc = (RA+RB)C ln 2.................(1) Where [ln 2 = 0.69]
= 0.69 (RA+RB) C
Where RA & RB are in ohms. And C is in farads.
Similarly, the time during which the capacitors discharges from 2/3 Vcc to 1/3 Vcc is equal to the
time, the output is low and is given by,
tc = RB C ln 2
td = 0.69 RB C...........................(2) where RB is in ohms and C is in farads.
Thus the total period of the output waveform
is T = tc + td = 0.69 (RA+2RB) C..............(3)
This, in turn, gives the frequency of oscillation as,f 0 = 1/T = 1.45/(RA+2RB)C.......(4)
Equation 4 indicates that the frequency f 0 is independent of the supply voltage Vcc.
 UNIT-5

Often the term duty cycle is used in conjunction with the astable multivibrator. The duty cycle is the
ratio of the time tc during which the output is high to the total time period T.
It is generally expressed as a percentage.
% duty cycle = (tc / T )* 100
% Duty Cycle = [(RA+RB)/ /(RA*2RB)] * 100

43
This parasitic capacitance introduces distortion to the sample-and hold value, thus mandating that Ch be
much larger than the parasitic capacitance. On top of this disadvantage, the settling time of the S/H circuit
during hold mode is longer for series sampling than for parallel sampling. The reason for this is because
the value of

Vout in series sampling is being reset to VCC (or VDD) for every sample, but this is not the case
for parallel sampling.
Switched Op-Amp Based Sample-and-Hold Circuit:
This S/H technique takes advantage of the fact that when a MOS transistor is in the saturation
region, the channel is pinched off and disconnected from the drain. Therefore, if the hold capacitor is
connected to the drain of the MOS transistor, charge injection will only go to the source junction, leaving
the drain unaffected. Based on this concept, a switched op- amp (SOP) based S/H circuit, as shown in

Figure 4.9

Fig. 4.9 Switched op-amp based sample and hold circuit.

During sample mode, the SOP behaves just like a regular op-amp, in which the value of the
output follows the value of the input. During hold mode, the MOS transistors at the output node of the
SOP are turned off while they are still operating in saturation, thus preventing any channel charge from
flowing into the output of the SOP.
In addition, the SOP is shut off and its output is held at high impedance, allowing the charge on
Ch to be preserved throughout the hold mode. On the other hand, the output buffer of this S/H circuit is
always operational during sample and hold mode and is always providing the voltage on Ch to the output
of the S/H circuit.
S/H circuits that operate in closed loop configuration can achieve high resolution, but their
requirements for high gain circuit block, such as an op-amp, limits the speed of the circuits. As a result,
better and faster S/H circuits must be developed.

44
 The above figure shows a sample and holds circuit with MOSFET as Switch acting as a sampling
device and also consists of a holding capacitor Cs to store the sample values until the next sample comes
in. This is a high speed circuit as it is apparent that CMOS switch has a very negligible propagation delay.
Three S/H circuits to reduce error:
Series sampling,
SOP based S/H circuit,
Bottom plate S/H circuit with bootstrapped switch

Fig. LF 398 IC- Functional Diagram

45
 Fig. Connections of S&H IC

Analog to Digital Converter- Specifications

Explain the specifications used for ADC. (May 2014)

Like DAC, ADCs are also having many important specifications. Some of them are Resolution,
Quantization error, Conversion time, Analog error, Linearity error, DNL error, INL error & Input voltage
range.
Resolution:
The resolution refers to the finest minimum change in the signal which is accepted for conversion,
and it is decided with respect to number of bits. It is given as 1/2n, where ‘n’ is the number of bits in the
digital output word. As it is clear, that the resolution can be improved by increasing the number of bits or
the number of bits representing the given analog input voltage.
Resolution can also be defined as the ratio of change in the value of input voltage Vi, needed to
change the digital output by 1 LSB. It is given as
Resolution n_ )
= ViFS / (2
Where ‘ViFS’ is the full-scale input
voltage. ‘n’ is the number of output
bits.
Quantization error:
If the binary output bit combination is such that for all the values of input voltage Vi between any
is a particular binary combination. This uncertainty is termed as quantization error. Its value is + (1/2) LSB.
And it is given as,
QE = ViFS / 2(2n_ 1)
Where ‘ViFS’ is the full-scale input

46
voltage ‘n’ is the number of output bits.
Maximum the number of bits selected, finer the resolution and smaller the quantization error.

47
Conversion Time:
It is defined as the total time required for an A/D converter to convert an analog signal to digital
output. It depends on the conversion technique and propagation delay of the circuit components.
Analog error:
An error occurring due to the variations in DC switching point of the comparator, resistors,
reference voltage source, ripples and noises introduced by the circuit components is termed as Analog error.
Linearity Error:
It is defined as the measure of variation in voltage step size. It indicates the difference between
the transitions for a minimum step of input voltage change. This is normally specified as fraction of LSB.
Differential Non-Linearity(DNL) Error:
The analog input levels that trigger any two successive output codes should differ by 1 LSB. Any
deviation from this 1 LSB value is called as DNL error.
Integral Non-Linearity (INL) Error:
The deviation of characteristics of an ADC due to missing codes causes INL error. The maximum
deviation of the code from its ideal value after nulling the offset and gain errors is called as Integral Non-
Linearity Error.
Input Voltage Range:
It is the range of voltage that an A/D converter can accept as its input without causing any overflow
in its digital output.
Analog Switches
Explain the different types of analog switches for ADC. (May 2014)

There were two types of analog switches. Series and Shunt switch. The Switch operation is shown
for both the cases VGS=0 VGS= VGs (off)

48
 Fig 4.13 Series and shunt Analog switches

Direct-conversion ADC/Flash type ADC

Explain flash type ADC with neat circuit diagram. (Nov 2015)[Nov/Dec 2021] [Nov/Dec 2022]

16
 This process is extremely fast with a sampling rate of up to 1 GHz. The resolution is however,
limited because of the large number of comparators and reference voltages required. The input signal is fed
simultaneously to all comparators. A priority encoder then generates a digital output that corresponds with
the highest activated comparator.

Successive-approsimation ADCs
Explain Successive approximation type ADC with neat block diagram. (May 2014,
2015) Explain counter type ADC. [Nov/Dec 2021]

Successive-approximation ADC is a conversion technique based on a successiveapproximation register

(SAR). This is also called bit-weighing conversion that employs a comparator to weigh the applied input
voltage against the output of an N-bit digital-to-analog converter (DAC).
The final result is obtained as a sum of N weighting steps, in which each step is a single-bit
conversion using the DAC output as a reference. SAR converters sample at rates up to lMbps, requires a
low supply current, and the cheapest in terms of production cost.
A successive-approximation ADC uses a comparator to reject ranges of voltages, eventually settling
on a final voltage range. Successive approximation works by constantly comparing the input voltage to the
output of an internal digital to analog converter (DAC, fed by the current value of the approximation) until
the best approximation is achieved.
At each step in this process, a binary value of the approximation is stored in a successive approximation
17
register (SAR). The SAR uses a reference voltage (which is the largest signal the ADC is to convert) for
comparisons.

The analogue value is rounded to the nearest binary value below, meaning this converter type is
mid- rise (see above). Because the approximations are successive (not simultaneous), the conversion takes
one clock-cycle for each bit of resolution desired.
The clock frequency must be equal to the sampling frequency multiplied by the number of bits of
resolution desired. For example, to sample audio at 44.1 kHz with 32 bit resolution, a clock frequency of
over
1.4 MHz would be required.
ADCs of this type have good resolutions and quite wide ranges. They are more complex than some
other designs.

18
Dual slope ADC (Integrating ADCs)
Explain dual slope ADC with neat circuit diagram. (May 2016)

In an integrating ADC, a current, proportional to the input voltage, charges a capacitor for a fixed
time interval T charge. At the end of this interval, the device resets its counter and applies an opposite-
polarity negative reference voltage to the integrator input. Because of this, the capacitor is discharged by a
constant current until the integrator output voltage zero again.
The T discharge interval is proportional to the input voltage level and the resultant final count
provides the digital output, corresponding to the input signal. This type of ADCs is extremely slow devices
with low input bandwidths. Their advantage, however, is their ability to reject high-frequency noise and
AC line noise such as 50Hz or 60Hz. This makes them useful in noisy industrial environments and typical
application is in multi-meters.
An integrating ADC (also dual-slope or multi-slope ADC) applies the unknown input voltage to the
input of an integrator and allows the voltage to ramp for a fixed time period (the run-up period). Then a
known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the
integrator output returns to zero (the run-down period).
The input voltage is computed as a function of the reference voltage, the constant run-up time
period, and the measured run-down time period. The run-down time measurement is usually made in units
of the converter's clock, so longer integration times allow for higher resolutions. Likewise, the speed of the
converter can be improved by sacrificing resolution.

19
Use: Converters of this type (or variations on the concept) are used in most digital voltmeters for their
linearity and flexibility.

A/D Using Voltage to Time Conversion

Explain voltage to time conversion based ADC with neat circuit diagram.

The Block diagram shows the basic voltage to time conversion type of A to D converter. Here the
cycles of variable frequency source are counted for a fixed period. It is possible to make an A/D converter

20
by

21
counting the cycles of a fixed-frequency source for a variable period. For this, the analog voltage required to
be converted to a proportional time period.
As shown in the diagram a negative reference voltage -VR is applied to an integrator, whose output
is connected to the inverting input of the comparator. The output of the comparator is at 1 as long as the
output of the integrator Vo is less than Va.
At t = T, Vc goes low and switch S remains open. When VEN goes high, the switch S is closed,
thereby discharging the capacitor. Also the NAND gate is disabled. The waveforms are shown here.

Fig. 4.16 A/D Using Voltage To Time Conversion

Fig.4.17 Conversion process

Sigma-delta ADCs / Over sampling Converters

Explain over sampling ADC. (May 2016) Discuss the g
Si ma-delta converters.[Nov/Dec 2022]
It consists of 2 main parts - modulator and digital filter. The modulator includes an integrator and a
comparator with a feedback loop that contains a l-bit DAC. The modulator oversamples the input signal,
converting it to a serial bit stream with a frequency much higher than the required sampling rate. This is
then transformed by the output filter to a sequence of parallel digital words at the sampling rate. The
characteristics of sigma-delta converters are high resolution, high accuracy, Low noise and low cost.
Typical applications are for speech and audio.
A Sigma-Delta ADC (also known as a Delta-Sigma ADC) oversamples the desired signal by a
large factor and filters the desired signal band. Generally a smaller number of bits than required are
converted using a Flash ADC acer the Filter.
The resulting signal, along with the error generated by the discrete levels of the Flash, is fed back
and subtracted from the input to the filter. This negative feedback has the effect of noise shaping the error
due to the Flash so that it does not appear in the desired signal frequencies.
A digital filter (decimation filter) follows the ADC which reduces the sampling rate, filters off
unwanted noise signal and increases the resolution of the output. (sigma-delta modulation, also called
delta- sigma modulation).

Fig . Sigma-delta ADCs/ Over sampling Converters.

22
 UNIT-4
Two Marks

1. What are the types of ADC and DAC. Types of ADC:

1. Flash (comparator) type converter , 2. Counter type converter , 3. Tracking or servo converter
4. Successive approximation type converter
Types of DAC:
1. Weighted resistor DAC , 2. R-2R Ladder , 3. Inverted R-2R Ladder
2. What is the difference between direct ADC and integrating type ADC.
a) The integrating type of ADC's do not need a sample/Hold circuit at the input.
b) It is possible to transmit frequency even in noisy environment or in an isolated form.
3. Define Resolution.
The resolution of a converter is the smallest change in voltage which may be produced at the output or input
of the converter.
Resolution (in volts)= VFS/2n-1=1 LSB increment. The resolution of an ADC is defined as the smallest
change in analog input for a one bit change at the output.
4. Define Accuracy.
Absolute accuracy:
It is the maximum deviation between the actual converter output & the ideal converter output.
Relative accuracy:
It is the maximum deviation after gain & offset errors have been removed.
The accuracy of a converter is also specified in form of LSB increments or % of full scale voltage.
5. Define Monotonicity .
A monotonic DAC is one whose analog output increases for an increase in digital input.
6. Define Conversion time.
It is defined as the total time required to convert an analog signal into its digital output. It depends on the
conversion technique used & the propagation delay of circuit components.
The conversion time of a successive approximation type ADC is given by
T(n+1) where T---clock period , Tc--conversion time n---no. of bits.
7. Explain the operation of basic sample and hold circuit.
A typical sample and hold circuit stores electric charge in a capacitor and contains at least one fast FET
switch and at least one operational amplifier. To sample the input signal the switch connects the capacitor
to the output of a buffer amplifier. The capacitor is invariably discharged by its own leakage currents and
useful load

23
currents, which makes the circuit inherently volatile, but the loss of voltage (voltage droop) within a specified

24
hold time remains within an acceptable error margin.
8. State the advantages and applications of sample and hold circuits.
A sample and hold circuit is one which samples an input signal and holds on to its last sampled value until
the input is sampled again. This circuit is mainly used in digital interfacing, analog to digital systems, and
pulse code modulation systems.
9. List the drawbacks of binary weighted resistor technique of D/A conversion.
a) Wide range of resistor values needed
b) Difficulty in achieving and maintaining accurate ratios over a wide range of variations
10. What is the advantage and disadvantages of flash type ADC?
Flash type ADC is the fastest as well as the most
expensive.
The disadvantage is the number of comparators needed almost doubles for each added bit (For a n-bit
convertor 2(n-1) comparators, 2n resistors are required).
11. Find the resolution of a 12 bit DAC converter.
Resolution (volts) = VFS/(212-1) = I LSB
increment VFS — Full scale voltage
12. What are the advantages and disadvantages of R-2R ladder DAC.
Advantages:
a) Easier to build accurately as only two precision metal films are required.
b) Number of bits can be expanded by adding more sections of same R/2R
values. Disadvantage:
a) In this type of DAC, when there is a change in the input, changes the current flow in the resistor which
causes more power dissipation which creates non-linearity in DAC.
13. efine start of conversion and end of conversion.
Start of Conversion in ADC (SOC): This is the control signal for start of conversion which initiates A/D
conversion process.
End of Conversion in ADC (EOC): This is the control signal which is activated when the conversion is
completed.
14. What is integrating type converter?
An ADC converter that perform conversion in an indirect manner by firstchanging the analog FP signal
to a linear function of time or frequency and then to adigital code is known as integrating type A/D
converter.
[Link] in brief the principle of operation of successive Approximation ADC.
The circuit of successive approximation ADC consists of a successive approximation register (SAR), to find
25
the required value of each bit by trial & error. With the arrival of START command, SAR sets the MSB bit
to

26
 1. The O/P is converted into an analog signal & it is compared with FP signal. This O/P is low or high.
This process continues until all bits are checked.
16 What are the main advantages of integrating type ADCs?
The integrating type of ADC's do not need a sample/Hold circuit at the input.
It is possible to transmit frequency even in noisy environment or in an isolated
form. 17 Where are the successive approximation type ADC used?
The Successive approximation ADCs are used in applications such as data loggers & instrumentation
where conversion speed is important.
18 What is the main drawback of a dual-slop ADC?
The dual slope ADC has long conversion time. This is the main drawback of dual slope ADC.
[Link] the advantages of dual slope ADC
It provides excellent noise rejection of ac signals whose periods are integral multiples of the
integration time T.
20 What is multiplying DAC?
A digital to analog converter which uses a varying reference voltage VR is called a multiplying
DAC(MDAC). If the reference voltage of a DAC, VR is a sine wave give by V(t)=Vin Cos 2f t
Then, Vo(t)=Vo m Cos(2 f1 + 180°)
21 What is a sample and hold circuit? Where it is used?
A sample and hold circuit is one which samples an input signal and holds onto its last sampled value
until the input is sampled again. This circuit is mainly used in digital interfacing, analog to digital systems,
and pulse code modulation systems.
[Link] sample period and hold period.
The time during which the voltage across the capacitor in sample and hold circuit is equal to the input
voltage is called sample period. The time period during which the voltage across the capacitor is held
constant is called hold period.
23 What is meant by delta modulation?
Delta modulation is a technique capable of performing analog signal quantization with smaller
bandwidth requirements. Here, the binary output representing the most recent sampled amplitude will be
determined on the basis of previous sampled amplitude levels.

24. Define sampling.

Convert analog signal into digital signal is known as sampling.
25. Write the names of the switches used in MOS transistors.
The names of the switches used in MOS transistors.
27
 CMOS Inverter switch
Totem pole MOSFET switch
26. Give the resolution of an 8-bit ADC of by input voltage? [Nov/Dec2021]
Resolution can also be defined as the ratio of change in the value of input voltage Vi, needed to
change the digital output by 1 LSB. It is given as

Resolution = ViFS / (2n_ i)

Where ‘ViFS’ is the full-scale input

voltage. ‘n’ is the number of output bits.
27. What output voltage would be produced by a D/A converter whose output range is 0 to 10V and
whose input binary number is 10111100 (for a 8 bit DAC)? [Nov/Dec 2021]
Output voltage = Resolution * binary number
n
Resolution R = VF t (2 -i)
= 10/ (2 -1)
= 10/255
= 0.039
Output voltage = 0.03 * 10111100
=0.039 * 188
= 7.37 V
28. State applications of ADCs.[Nov/Dec 2022]
1. Digtal Signal Processing.
2. Audio processing
3. Scientific Instruments
4. Micro controllers.

28
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 UNIT-5

UNIT V

Introduction:

The transducer circuit will gives an analog signal. This signal is transmitted through the LPF circuit
to avoid higher frequencycomponents, and then the signal is sampled at twice the frequency of the signal to
avoid the overlapping.
The output of the sampling circuit is applied to A/D converter where the samples are converted into
binary data i.e. 0’s and 1’s. Like this the analog data converted into digital data.
The digital data is again reconverted back into analog by doing exact opposite operation of first half
of the diagram. Then the output of the D/A convertor is transmitted through the smoothing filter to avoid
the ripples.

Digital to analog converter

Basic DAC techniques:

1
 The input of the block diagram is binary data i.e, 0 and 1,it contain ‘n’ number of input bits
designated as d1,d2,d3,.....dn .this input is combined with the reference voltage called Vdd to give an
analog output. Where d1 is the MSB bit and dn is the LSB bit.
2
Vp-K Vrs(di2°'+d22° +.... - - - • •+d 2*‘)

Where , V0- output voltage

VFS- full scale output
voltage K = scaling factor
Digital to Analog Specifications
Explain the specifications of DAC. (May 2013)

D/A converters are available with wide range of specifications specified by manufacturer. Some of
the important specifications are Resolution, Accuracy, linearity, monotonicity, conversion time, settling
time and stability.
Resolution:
Resolution is defined as the number of different analog output voltage levels that can be provided
by a DAC. Or alternatively resolution is defined as the ratio of a change in output voltage resulting for a
change of 1 LSB at the digital input. Simply, resolution is the value of LSB.
Resolution (Volts) = VoFS / (2n ) - 1 LSB increment
Where ‘n’ is the number of input bits
‘VoFS’ is the full scale output voltage.
Example: Resolution for an 8 — bit DAC for example is said to have
: 8 — bit resolution
: A resolution of 0.392 of full-Scale (1/255)
: A resolution of 1 part in 255.

2
Accuracy:
Absolute accuracy is the maximum deviation between the actual converter output and the ideal
converter output. The ideal converter is the one which does not suffer from any problem.
Whereas, the actual converter output deviates due to the drift in component values, mismatches,
aging, noise and other sources of errors.
The relative accuracy is the maximum deviation after the gain and offset errors have been removed.
Accuracy is also given in terms of LSB increments or percentage of full-scale voltage.
Normally, the data sheet of a D/A converter specifies the relative accuracy rather than absolute
accuracy.

Linearity:
Linearity error is the maximum deviation in step size from the ideal step size. Some D/A converters
are having a linearity error as low as 0.001% of full scale. The linearity of a D/A converter is defined as
the precision or exactness with which the digital input is converted into analog output. An ideal D/A
converter produce equal increments or step sizes at output for every change in equal increments of binary
input.
Monotonicity:
A Digital to Analog converter is said to be monotonic if the analog output increases for an increase
in the digital input. A monotonic characteristic is essential in control applications. Otherwise it would
lead to oscillations. If a DAC has to be monotonic, the error should be less than + (1/2) LSB at each
output level. Hence all the D/A converters are designed such that the linearity error satisfies the above
condition.
When a D/A Converter doesn't satisfy the condition described above, then, the output voltage may
decrease for an increase in the binary input.
Conversion Time:
It is the time taken for the D/A converter to produce the analog output for the given binary input
signal. It depends on the response time of switches and the output of the Amplifier. D/A converters
speed can be defined by this parameter. It is also called as setting time.
Settling time:
It is one of the important dynamic parameter. It represents the time it takes for the output to settle
within a specified band + (1/2) LSB of its final value following a code change at the input (Usually a
full- scale change). It depends on the switching time of the logic circuitry due to internal parasitic
capacitances and inductances. A typical settling time ranges from 100 ns to 10 ps depending on the word
length and type of circuit used.

3
Stability:

4
 The ability of a DAC to produce a stable output all the time is called as Stability. The performance
of a converter changes with drift in temperature, aging and power supply variations. So all the parameters
such as offset, gain, linearity error & monotonicity may change from the values specified in the
datasheet. Temperature sensitivity defines the stability of a D/A converter.

Digital To Analog Conversion Binary-

Weighted Resistor DAC
Explain Binary-Weighted Resistor DAC with neat circuit diagram. (May 2014)[Nov/Dec2021]

The binary-weighted-resistor DAC employs the characteristics of the inverting summer Op Amp
circuit. In this type of DAC, the output voltage is the inverted sum of all the input voltages. If the input
resistor values are set to multiples of two: lR, 2R and 4R, the output voltage would be equal to the sum
of V1, V2/2 and V3/4. V1 corresponds to the most significant bit (MSB) while V3 corresponds to the
least significant bit (LSB).

Fig. Binary weighted DAC

The binary inputs, ai (where i = 1, 2, 3 and 4) have values of either 0 or 1. The value, 0, represents

5
an open switch while 1 represents a closed switch.

6
 The operational amplifier is used as a summing amplifier, which gives a weighted sum of the
binary input based on the voltage, Vref.
For a 4-bit DAC, the relationship between Vout and the binary input is as follows:

The negative sign associated with the analog output is due to the connection to a summing
amplifier, which is a polarity-inverting amplifier. When a signal is applied to the latter type of amplifier,
the polarity of the signal is reversed (i.e. a + input becomes -, or vice versa).
For a n-bit DAC, the relationship between Vout and the binary input is as follows:

The LSB, which is also the incremental step, has a value of - 0.625 V while the MSB or the full
scale has a value of - 9.375 V.
Practical Limitations:
The most significant problem is the large difference in resistor values required between the LSB
and MSB, especially in the case of high resolution DACs (i.e. those that has large number of bits).
For example, in the case of a 12-bit DAC, if the MSB is 1 k f2, then the LSB is a staggering 2 MCL
The maintenance of accurate resistances over a large range of values is problematic. With the
current IC fabrication technology, it is difficult to manufacture resistors over a wide resistance
range that maintains an accurate ratio especially with variations in temperature.
R-2R Ladder DAC
Explain R-2R Ladder DAC with neat circuit diagram. (Nov 2014)[Nov/Dec 2021] [Nov/Dec 2022]
An enhancement of the binary-weighted resistor DAC is the R-2R ladder network. This type of
DAC utilizes Thevenin's theorem in arriving at the desired output voltages.
A disadvantage of the former DAC design was its requirement of several different precise input
resistor values: one unique value per binary input bit.
The R-2R network consists of resistors with only two values - R and 2R. If each input is supplied
either 0 volts or reference voltage, the output voltage will be an analog equivalent of the binary value of
the three bits.
Inverted Or Current Mode DAC
Explain current mode DAC with neat circuit diagram.

Current mode DACs operates based on the ladder currents. The ladder is formed by resistance R in
the series path and resistance 2R in the shunt path. Thus the current is divided into il , i2, i3.......in. in each
arm. The currents are either diverted to the ground bus (io) or to the Virtual-ground bus io ).

Fig. Current mode DAC

The currents are given as

6
 .................
i1 = VREF/2R = (VREF/R) 2 ', i2 = (VREF)/2)/2R = (VREF/R) 2 2 in — (VREF/R) 2 n.
And the relationship between the currents are given as
i2 = i1/2
i3 =
i1/4 i4
= i1/8

in = i1/ 2n '
Using the bits to identify the status of the switches, and letting V0 = -Rf io
gives V0 = - (Rf/R) VREF (b1 2 ' + b2 2 2+...+ bn 2 n)
Advantages
1. The major advantage of current mode D/A converter is that the voltage change across each switch is
minimal. So the charge injection is virtually eliminated and the switch driver design is made simpler.
2. In Current mode or inverted ladder type DACs, the stray capacitance do not affect the Speed of response
of the circuit due to constant ladder node voltages. So improved speed performance.

Voltage Mode DAC

This is the alternative mode of DAC and is called so because the 2R resistance in the shunt path is
switched between two voltages named as VL and VH. The output of this DAC is obtained from the
leftmost ladder node. As the input is sequenced through all the possible binary state starting from All 0s
(0.....0) to all
I S (1.........1).

The voltage of this node changes in steps of 2 (VH - VL) from the minimum voltage of Vo = VL
-n
to the maximum of Vo = VH - 2 (vH - VL).

7
 The diagram also shows a non-inverting amplifier from which the final output is taken. Due to this
buffering with a non- inverting amplifier, a scaling factor defined by K = 1 + (R2/R1) results.
Advantages
1. The major advantage of this technique is that it allows us to interpolate between any two
voltages, neither of which need not be a zero.
2. More accurate selection and design of resistors R and 2R are possible and simple construction.
3. The binary word length can be easily increased by adding the required number or R-2R sections.

8
 UNIT-5

Linear Regulators
All electronic circuits need a dc power supply for their operation. To obtain this dc voltage from 230 V
ac mains supply, we need to use rectifier.
Therefore the filters are used to obtain a “steady” dc voltage from the pulsating one.
The filtered dc voltage is then applied to a regulator which will try to keep the dc output voltage constant
in the event of voltage fluctuations or load variation.
The combination of rectifier & filter can produce a dc voltage. But the problem with this type of dc
power supply is that its output voltage will not remain constant in the event of fluctuations in an AC input
or changes in the load current(IL).
The output of unregulated power supply is connected at the input of voltage regulator circuit.
The voltage regulator is a specially designed circuit to keep the output voltage constant. It does not
remain exactly constant. It changes slightly due to changes in certain parameters.
Factors affecting the output voltage:
i) IL (Load Current)
ii) VIN (Input Voltage)
iii) T (Temperature)
IC Voltage Regulators:
They are basically series regulators.
Important features of IC Regulators:
1. Programmable output
2. Facility to boost the voltage/current
3. Internally provided short circuit current limiting
4. Thermal shutdown
5. Floating operation to facilitate higher voltage
output Classifications of IC voltage regulators:

9
 UNIT-5

Fixed & Adjustable output Voltage Regulators are known as Linear Regulator. A series pass transistor is used
and it operates always in its active region.
Switching Regulator:
1. Series Pass Transistor acts as a switch.
2. The amount of power dissipation in it decreases considerably.
3. Power saving result is higher efficiency compared to that of
linear. Adjustable Voltage Regulator:
Advantages of Adjustable Voltage Regulator over fixed voltage regulator are,
1. Adjustable output voltage from 1.2v to 57 v
2. Output current 0.10 to 1.5 A
3. Better load & line regulation
4. Improved overload protection
5. Improved reliability under the 100% thermal overloading
Adjustable Positive Voltage Regulator (LM317)
Explain the operation of positive voltage regulator LM317.

LM317 series adjustable 3 terminal positive voltage regulator, the three terminals are Vin, Vout & adjustment
(ADJ).

voltage is called as
Vref.

will also be constant. Because

resistor R1 sets current 11. It is called “current set” or “program resistor”.
10
 UNIT-5

Resistor R2 is called as “Output set” resistors, hence current through this resistor is the sum of Il & ladj
LM317 is designed in such as that ladj is very small & constant with changes in line voltage & load
current. The output voltage Vo is, Vo RH l +(11+Iadj)R2-(l)
Where Il= Vref/R1
Vo = (Vref/R1) RI + Vref/Rl + ladj R2
= Vref + (Vref/Rl) R2 + ladj R2
Vo = Vref [1 + R2/R1] + ladj R2------------(2)
RI = Current (11) set
resistor R2 = output (Vo)
set resistor.
Vref= I.25v which is a constant voltage between output and ADJ terminals.
Current ladj is very small. Therefore the second term in (2) can be neglected.
Thus the final expression for the output voltage is given by
Vo= l.25v[1 + R2/Rl]---------------(3)
Eqn (3) indicates that we can vary the output voltage by varying the resistance R2. The value of R I is
normally kept constant at 240 ohms for all practical applications.
Practical Regulator using LM317

LN3l7
IB OVT

RI

CI

C2

If LM317 is far away from the input power supply, then 0.1pf disc type or I pf tantalum capacitor
should be used at the input of LM317.
The output capacitor Co is optional. Co should be in the range of 1 to l000qf,
The adjustment terminal is bypassed with a capacitor C2 this will improve the ripple rejection ratio as high
as 80 dB is obtainable at any output level.
When the filter capacitor is used, it is necessary to use the protective diodes.
11
These diodes do not allow the capacitor C2 to discharge through the low current point of the regulator.

12
 UNIT-5

These diodes are required only for high output voltages (above 25v) & ior higher values of output
capacitance 25pf and above.
IC 723 — General Purpose Regulator
Explain the basic operations of IC723 general purpose regulator. [Nov/Dec 2022]
Disadvantages of fixed voltage regulator:
1. Do not have the shot circuit
2. Output voltage is not adjustable
These limitations can be overcomes in IC723.
Features of IC723:
1. Unregulated dc supply voltage at the input between 9.5V & 40V
2. Adjustable regulated output voltage between 2 to 3V.
3. Maximum load current of 150 mA (ILmax = l50mA).
4. With the additional transistor used, ILmax upto l 0A is obtainable.
5. Positive or Negative supply operation
6. Internal Power dissipation of 800mW.
7. Built in short circuit protection.
8. Very low temperature drift.
9. High ripple rejection.
The simplified functional block diagram can be divided in to 4 blocks.
1. Reference Generating block:
The temperature compensated Zener diode, constant current source & voltage reference amplifier together
from the reference generating block. The Zener diode is used to generate a fixed reference voltage internally.
Constant current source will make the Zener diode to operate at affixed point & it is applied to the Non —
inverting terminal of error amplifier. The Unregulated input voltage +Vcc is applied to the voltage reference
amplifier as well as error amplifier.
2. Error Amplifier:
Error amplifier is a high gain differential amplifier with 2 input (inverting & Noninverting). The Non-
inverting terminal is connected to the internally generated reference voltage. The Inverting terminal is
connected to the full regulated output voltage.

13
 UNIT-5

3. Series Pass Transistor:

Q1 is the internal series pass transistor which is driven by the error amplifier. This transistor actually acts
as a variable resistor & regulates the output voltage. The collector of transistor Q1 is connected to the Un-
regulated power supply. The maximum collector voltage of Q1 is limited to 36Volts. The maximum
current which can be supplied by Q1 is l50mA.
4. Circuitry to limit the current:
The internal transistor Q2 is used for current sensing & limiting. Q2 is normally OFF transistor. It turns
ON when the IL exceeds a predetermined limit. Low voltage, Low current is capable of supplying load
voltage which is equal to or between 2 to 7Volts. Vload = 2 to 7V and Iload= 50mA

14
 UNIT-5

IC723 as a LOW voltage LOW current

Explain with neat circuit diagram, IC723 as low voltage regulator.

Lfñ723

A1 1fi0 pF

The Voltage across R2 is connected to the Non — inverting terminal of the regulator IC
Vnon-inv = R2/(R1*R2) Vref
Gain of the internal error amplifier is large Vnon-inv = Vin
Therefore the Vo is connected to the Inverting terminal through R3 & RSC must also be equal to Vnon-
inv Vo = Vnon-inv =R2/(R1+R2) Vref
Rl & R2 can be in the range of 1 KB to l0KD & value of R3 is given
by R3 = Rlll R2 =R1R2/(R1+R2)
Rsc (current sensing resistor) is connected between Cs & CL. The voltage drop across Rsc is proportional
to the IL.
This resistor supplies the output voltage in the range of 2 to 7 volts, but the load current can be higher
than 150mA.
The current sourcing capacity is increased by including a transistor Q in the
circuit. The output voltage , Vo =R2/(Rl+R2) Vref
5.7.2 IC723 as a HIGH voltage LOW Current:
This circuit is capable of supplying a regulated output voltage between the ranges of 7 to 37 volts with a
maximum load current of 150 mA.
The Non — inverting terminal is now connected to Vref through resistance R3.

15
 UNIT-5

The value of R1 & R2 is adjusted in order to get a voltage of Vref at the inverting terminal at the desired
output.
Vin = Vref=R2 /(Rl +R2)
V0 Vo = [1+Rl/R2] Vin
Rsc is connected between CL & Cs terminals as before & it provides the short Circuit current limiting
Rsc =0.6/I1imit
The value of resistors R3 is given by , R3= Rl11 R2 =R1R2/(R1+R2)
IC723 as a HIGH voltage HIGH Current:
Explain with neat diagram IC723 as high voltage regulator.

An external transistor Q is added in the circuit for high voltage low current regulator to improve its
current sourcing capacity.

RKC£f LATED
UTPUT

R2

For this circuit the output voltage varies between 7 & 37V.
Transistor Q increase the current sourcing capacity thus IL (MAX) is greater than 150mA.
The output voltage Vo is given by ,
V0= Vo = [l+R1/R2] Vin
Rsc =0.6/Ilimit

16
 UNIT-5

Switching Regulator:
Explain the basic operation of switching regulator.

An example of general purpose regulator is Motorola's MC1723. It can be used in many different ways, for
example, as a fixed positive or negative output voltage regulator, variable regulator or switching regulator
because of its flexibility.
To minimize the power dissipation during switching, the external transistor used must be a
switching power transistor. To improve the efficiency of a regulator, the series pass transistor is used as a
switch
rather than as a variable resistor as in the linear mode.
A regulator constructed to operate in this manner is called a series switching regulator. In such regulators
the series pass transistor is switched between cut off & saturation at a high frequency which produces a
pulse width modulated (PWM) square wave output.
This output is filtered through a low pass LC filter to produce an average dc output
voltage. Thus the output voltage is proportional to the pulse width and frequency.
The efficiency of a series switching regulator is independent of the input & output differential & can
approach 95%

Switch Filtcrs

Supply +
Voltage Pulse generator
Vin — Vpulse Load

A basic switching regulator consists of 4 major components,

1. Voltage source Vin
2. Switch Sl
3. Pulse generator Vpulse
4. Filter FI
1. Voltage Source Vin:
It may be any dc supply — a battery or an unregulated or a regulated voltage. The voltage source must satisfy
the following requirements.

17
It must supply the required output power & the losses associated with the switching regulator.

18
 UNIT-5

It must be large enough to supply sufficient dynamic range for line & load regulations.
It must be sufficiently high to meet the minimum requirement of the regulator system to be
designed. It may be required to store energy for a specified amount of time during power failures.
2. Switch SI:
It is typically a transistor or thyristor connected as a power switch & is operated in the saturated mode.
The pulse generator output alternately turns the switch ON & OFF
3. Pulse generator Vpulse:
It provides an asymmetrical square wave varying in either frequency or pulse width called frequency
modulation or pulse width modulation respectively. The most effective frequency range for the pulse
generator for optimum efficiency 20 KHz. This frequency is inaudible to the human ear & also well within
the switching speeds of most inexpensive transistors & diodes.
The duty cycle of the pulse wave form determines the relationship between the input & output voltages.
The duty cycle is the ratio of the on time ton, to the period T of the pulse waveform.
Duty cycle = ton/(ton+toffJ = ton/T =ton.f
Where ton = On-time of the pulse waveform toff=off-time of the pulse wave
form T = time period = ton + toff
= 1/frequency or T = 1/f
Typical operating frequencies of switching regulator range from 10 to 50 kHz.
Lower operating frequency improve efficiency & reduce electrical noise, but require large filter components
(inductors & capacitors).
4. Filter F1:
It converts the pulse waveform from the output of the switch into a dc voltage. Since this switching
mechanism allows a conversion similar to transformers, the switching regulator is often referred to as a dc
transformer.
The output voltage Vo of the switching regulator is a function of duty cycle & the input voltage
Vin. Vo is expressed as follows, Vo= ton VimT
This equation indicates that, if time period T is constant, Vo is directly proportional to the ON-time, ton
for a given value of Vin. This method of changing the output voltage by varying ton is referred to as a pulse
width modulation.
Similarly, if ton is held constant, the output voltage Vo is inversely proportional to the period T or
directly proportional to the frequency of the pulse waveform. This method of varying the output voltage is
referred to as frequency modulation (FM).
Switching regulator can operate in any of 3 modes
19
i) Step — Down

20
 UNIT-5

ii) Step — Up
iii) Polarity inverting
Monolithic Switching Regulator [pa78s40]:
The qA78S40 consists of a temperature compensated voltage reference, duty cycle controllable oscillator
with an active current limit circuit, a high gain comparator, a high- current, high voltage output switch, a
power switching diode & an uncommitted op-amp.
Important features of the qA78S40 switching regulators
are: Step up, donc & Inverting operation
Operation from 2.5 to 40V input
80dB line & load regulations
Output adjustable from 1.3 to 40V
Peak current to 1.5A without external resistors
Variable frequency, variable duty cycle device
The internal switching frequency is set by the timing capacitor CT, connected between pinl2 & ground pin 11.
The initial duty cycle is 6:1. The switching frequency & duty cycle can be modified by the current limit circuitry,
IPK sense, pin14, 7 the comparator, pin9 & 10.
Comparator:
The comparator modifies the OFF time of the output switch transistor Q1 & Q2. In the step — up & step
down modes, the non-inverting input(pin9) of the comparator is connected to the voltage reference of 1.3V
(pin8) & the inverting input (pin10) is connected to the output terminal via the voltage divider network.

Diode Cathod a Swkch Collector

Diode Arod+ Driver Colbctor
Switch Emit 'f Ig Sense
Dp Amp Output
V
V Op Amp Thing Capacitor

or NÖ £IÎ fÏV. Gourd

AU
Inv. Input t0Æ

Reference
NoniMv. Input
 UNIT-5
[Link] the performance parameters of IC regulators. [Nov/Dec 2021]
Depending on the application, other parameters may be important, such as output ripple voltage, load
transient response, output noise, and efficiency.

[Link] Voltage and Output Voltage

The first step towards choosing a voltage regulator is knowing about the input voltage and output
voltage that you will be working with. Linear voltage regulators need input voltage that is higher than the
rated output voltage. If the input voltage is less than the desired output voltage, then it leads to the condition
of insufficient voltage that causes the regulator to drop out and provide unregulated output.
2. Dropout Voltage
Dropout voltage is the difference between input and output voltage of the voltage regulator. For
example, min. The input voltage for 7805 is 7V, and the output voltage is 5V, so it has a dropout voltage of
2V. If the input voltage goes below, the output voltage (5V) + dropout voltage (2V) will result in an
unregulated output that can damage your device. So before selecting a voltage regulator, check the dropout
voltage.
Dropout voltage varies with voltage regulators; for example, you can find a range of 5V regulators with
different dropout voltage. Linear regulators can be extremely efficient when they are operated with a very low
input dropout voltage. So if you are using a battery as a power source, then you can use LDO regulators for
better efficiency.
3. Power Dissipation
Linear voltage regulators dissipate more power than switching voltage regulators. Excessive power
dissipation can cause battery drain, overheating, or damage to the product. So if you are using a linear voltage
regulator, first calculate the power dissipation. For linear regulators, power dissipation can be calculated by:
Power = (Input Voltage — Output Voltage) x Current
4. Efficiency
Efficiency is the ratio of output power to input power that is proportional to the ratio of the output
voltage to the input voltage. So the efficiency of Voltage regulators is directly limited by the dropout voltage
and quiescent current because of the higher the dropout voltage, the lower the efficiency.
For higher efficiency, drop out voltage and quiescent current must be minimized, and the voltage
difference between input and output must be minimized.
5. Voltage Accuracy
The overall accuracy of a voltage regulator depends on line regulation, load regulation, reference
voltage drift, error amplifier voltage drift, and temperature coefficient. Typical linear regulators usually have
an output voltage specification that guarantees the regulated output will be within 5% of nominal. So if you
are using the voltage regulator to power the digital ICs, then 5% tolerance is not a big concern.
6. Load Regulation
Load regulation is defined as the circuit's ability to maintain a specified output voltage under varying
load conditions. Load regulation is expressed as:
Load Regulation = AVout/ Shut
7. Line Regulation
Line regulation is defined as the circuit's ability to maintain the specified output voltage with the
varying input voltage. Line regulation is expressed as:
Load Regulation = AVout' Vin

Frequency to Voltage (F-V) and voltage to frequency convertors (V-

F) Explain the basic operations of F-V and V-F converters.
F-V convertors applications: Tachometer in motor speed control Rotational speed measurement.
Two types of it: Pulse integrating Phase locked loop
F-V convenor produces an output voltage whose amplitude is a function of input signal
frequency. V0=kf fi kf is sensitivity of F-V convenor
It is basically a FM discriminator.

26
 UNIT-5

Input frequency is applied to comparator A. Resistor R acts as feedback element.

Capacitor Ci enables charge-balancing, High pass network conditions input signal For negative spike of
V01, comparator COMP triggers one shot multivibrator with threshold 7.5V The output of multivibrator
closes the switch SW, for a time TH, this causes voltage Vo to build up and inject thru R and this
continues until current out of summing input of opamp is equal to that injected by Vo through R
continuously.
Vo=10-3 *TH *R*fi as TH =7.5 C /1X10-3
Ripple Voltage, Vr(max) =7.5 C /Ci
Voltage to frequency convertor
Principle: Charge balancing technique-the process of charging and discharging results in frequency
proportional to input signal F0= k Vi
Operation: Op-amp A converts input Vi to current E = Vi/R into summing junction. When switch SW is
open the current flows into capacitor Ci and charges it, and node voltage Vol produce ramp down.
When V01 =0 CMP triggers and sends a triggering signal to one shot multivibrator that closes the switch
SW and turns transistor Q ON for time TH.
The threshold of mono shot = 7.5 V and TH= 7.5 C/10-3
During TH , V01 ramps upward by amount fi 01=(1mA-Ii) TH
/Ci Time duration TL for vol to return to 0 is TL = CA 01/E
TL+TH = lmA TH /Ii = T
27
F0=Vi/7.5 RC

28
UNIT-5
 UNIT-5

Unit-5
Two Marks
1. Mention any two audio frequency oscillators.
RC phase shift oscillator
Wein bridge oscillator
2. What are the requirements of producing sustained oscillation in feedback circuits?
For sustained oscillations, The total phase shift around the loop must be zero at the desired frequency
of oscillation fo. i.e , AB = 0 ( or ) 360°. At fo, the magnitude of the loop gain | A § | should be equal to
unity
3. What is a multivibrator?
Multivibrators are a group of regenerative circuits that are used extensively in timing applications. It
is a wave shaping circuit which gives symmetric or asymmetric square output. It has two states either
stable or quasi- stable depending on the type of multivibrator.
4. What do you mean by monostable multivibrator?
Monostable multivibrator is one which generates a single pulse of specified duration in response to
each external trigger signal. It has only one stable state. Application of a trigger causes a change to the
quasi- stable state. An external trigger signal generated due to charging and discharging of the capacitor
produces the transition to the original stable state.
5 What is an astable multivibrator?
Astable multivibrator is a free running oscillator having two quasistable states. Thus, there is
oscillations between these two states and no external signal are required to produce the change in state.
5 What is a bistable multivibrator?
Bistable multivibrator is one that maintains a given output voltage level unless an external trigger is
applied . Application of an external trigger signal causes a change of state, and this output level is
maintained indefinitely until an second trigger is applied . Thus, it requires two external triggers before it
returns to its initial state.
[Link] some applications of 555 timer:
Oscillator, pulse generator, ramp and square wave generator, mono-shot multivibrator, burglar
alarm, Traffic light control.
7. List the applications of 555 timer in monostable mode of operation:
Missing pulse detector, Linear ramp generator, Frequency divider, Pulse width modulation.
8. List the applications of 555 timer in Astable mode of operation:
FSK generator, Pulse-position modulator
34
 UNIT-5

9. List the applications of 555 timer in monostable mode of operation:

Missing pulse detector, Linear ramp generator, Frequency divider, Pulse width modulation.
10. List the applications of 555 timer in Astable mode of operation:
FSK generator, Pulse-position modulator
11. What is a voltage regulator?
A voltage regulator is an electronic circuit that provides a stable dc voltage independent of the load
current, temperature, and ac line voltage variations.
12 Give the classification of voltage regulators:
Series / Linear regulators, Switching regulators.
13. What is opto coupler?
An opto-isolator, also called an optocoupler, photocoupler, or optical isolator, is "an electronic
device designed to transfer electrical signals by utilizing light waves to provide coupling with electrical
isolation between its input and output”. The main purpose of an opto-isolator is "to prevent voltages or
rapidly changing voltages on one side of the circuit from damaging components or distorting transmissions
on the other side
14 What is a linear voltage regulator? (Nov/Dec 2022]
Series or linear regulator uses a power transistor connected in series between the unregulated dc
input and the load and it conducts in the linear region .The output voltage is controlled by the continuous
voltage drop taking place across the series pass transistor.
14 What is a switching regulator?
Switching regulators are those which operate the power transistor as a high frequency on/off switch,
so that the power transistor does not conduct current continuously. This gives improved efficiency over
series regulators.
[Link] are the advantages of IC voltage regulators?
Low cost, High reliability, Reduction in size, Excellent performance
16 Give some examples of monolithic IC voltage regulators:
78XX series fixed output, positive voltage regulators, 79XX series fixed output, negative voltage
regulators, 723 general purpose regulator.
17. What is the purpose of having input and output capacitors in three terminal IC regulators?
A capacitor connected between the input terminal and ground cancelsthe inductive effects due to long
distribution lea ds. The output capacitor improvesthe transient response.
18. Define line regulation.
Line regulation is defined as the percentage change in the output voltage for a change in the input
35
voltage. It is expressed in milli volts or as a percentage of the output voltage.

36
 UNIT-5

19 Define load regulation.

Load regulation is defined as the change in output voltage for a change in load current. It is
expressed in millivolts or as a percentage of the output voltage.
20 What is meant by current limiting?
Current limiting refers to the ability of a regulator to prevent the load currentfrom increasing above a
preset value.
21 Give the drawbacks of linear regulators: [Nov/Dec 2022]
The input step down transformer is bulky and expensive because of low line frequency.
Because of low line frequency, large values of filter capacitors are required to decrease the ripple.
Efficiency is reduced due to the continuous power dissipation by the transistor as it operates in the
linear region.
21 What is the advantage of switching regulators?
Greater efficiency is achieved as the power transistor is made to operate as low impedance switch.
Power transmitted across the transistor is in discrete pulses rather than as a steady current flow. By using
suitable switching loss reduction technique, the switching frequency can be increased so as to reduce the
size and weight of the inductors and capacitors.
22 What is an opto-coupler IC? Give examples.
Opto-coupler IC is a combined package of a photo-emitting device and aphoto- sensing device.
Examples for opto-coupler circuit: LED and a photo diode, LED and photo transistor, LED and
Darlington. Examples for opto-coupler IC: MCT 2F , MCT 2E .
23. Mention the advantages of opto-couplers.
Better isolation between the two stages, Impedance problem between the stages is eliminated.
Wide frequency response, Easily interfaced with digital circuit, Compact and light weight.
Problems such as noise, transients, contact bounce, are eliminated.
24 What is an isolation amplifier?
An isolation amplifier is an amplifier that offers electrical isolation between its input and output
terminals.
25 What is the need for a tuned amplifier?
In radio or TV receivers, it is necessary to select a particular channel among all other available
channels. Hence some sort of frequency selective circuit is needed that will allow us to amplify the
frequency band required and reject all the other unwanted signals and this function is provided by a tuned
amplifier.

37
 Low Drop Out (LDO) Regulators
Voltage regulators are used to provide a stable power supply voltage independent of load
impedance, input-voltage variations, temperature, and time. Low-dropout regulators are distinguished
by their ability to maintain regulation with small differences between supply voltage and load
voltage. For example, as a lithium-ion battery drops from 4.2 V (fully charged) to 2.7 V (almost
discharged), an LDO can maintain a constant 2.5 V at the load.
The increasing number of portable applications has thus led designers to consider LDOs to
maintain the required system voltage independently of the state of battery charge. But portable
systems are not the only kind of application that might benefit from LDOs. Any equipment that
needs constant and stable voltage, while minimizing the upstream supply (or working with wide
fluctuations in upstream supply), is a candidate for LDOs. Typical examples include circuitry with
digital and RF loads.
A “linear” series voltage regulator (Figure 1) typically consists of a reference voltage, a
means of scaling the output voltage and comparing it to the reference, a feedback amplifier, and a
series pass transistor (bipolar or FET), whose voltage drop is controlled by the amplifier to
maintain the output at the required value. If, for example, the load current decreases, causing the
output to rise incrementally, the error voltage will increase, the amplifier output will rise, the
voltage across the pass transistor will increase, and the output will return to its original value.

Figure 1. Basic enhancement-mode PMOS LDO.

In Figure 1, the error amplifier and PMOS transistor form a voltage-controlled current
source. The output voltage, VoUr, is scaled down by the voltage divider (fii, ñ2) and compared to
the reference voltage (VHF). The error amplifier's output controls an enhancement-mode PMOS
transistor.
The dropout voltage is the difference between the output voltage and the input voltage at
which the circuit quits regulation with further reductions in input voltage. It is usually considered to
be reached when the output voltage has dropped to 100 mV below the nominal value. This key
factor, which characterizes the regulator, depends on load current and junction temperature of the
pass transistor.
 The source of the input voltage needs to be considered in order to choose a suitable category
of LDO. In battery-powered applications, LDOs must maintain the required system voltage as the
battery discharges. If the dc input voltage is pro› ided from a rectified ac source, the dropout
voltage may not bc critical, so a standard regulator—which may be chcapcr and can provldc morc
load current—could be a better choice. But an LDO could be the right choice if lower power
dissipation or a more precise output › oltage is necessary.
The regulator should, of course, be able to provide enough current to the load with
specifiecl accuracy under worst-case conditions.

LDO Topologies
In Figure 1, the pass device is a PMOS transistor. However, a v ariety of pass devices are
a› ailable, and LDOs can be classified depending on which type of pass device is used. Their
differing structures and characteristics offer various advantages and drawbacks.
Examples of four types of pass devices are shown in Figure 3, including NPN and PNP
bipolar transistors, Darlington circuits, and PMOS transistors.

For a gi›•en supply voltage, the bipolar pass devices can deliver the highest output current.
A PNP is preferred to an NPN, because the base of the PNP can be pulled to ground, fully
saturating the transistor if ncccssary. The basc of thc NPN can only bc pullcd as high as thc supply
voltagc, limiting the minimum voltage drop to one VBE. Therefore, NPN and Darlington pass
devices can't provide dropout voltages below I V. They can be valuable, however, where wide
bandwidth and immunity to capacitive loading are necessary (thanks to their characteristically low
ZOUT).
PMOS and PNP transistors can be effectively saturated, minimizing the voltage loss and the
power dissipated by the pass device, thus allowing low dropout, high-efficiency › oltage regulators.
PMOS pass devices can provide the lowest possible dropout voltage drop, approximately RD.
(os)
It. They also allow the quiescent cur1'ent flow to be minimized.
 The main drawback is that the MOS transistor is often an external component—especially
for controlling high currents—thus making the IC a controller, rather than a complete self-
contained regulator.
The power loss in a complete regulator is

The first part of this relationship is the dissipation of the pass device; the second part is the
power consumption of the controller portion of the circuit. The ground current in some regulators,
especially those using saturable bipolar transistors as pass devices, can peak during power-up.

LDO frequency amplitude response.

 PART B

1. Write note on optocoupler. [Nov/Dec 2022]

Opto-coupler is an electronic component that transfers electrical signals between two isolated
circuits. Optocoupler also called Opto-isolator, photo coupler or optical isolator.
Optocoupler is used to isolate circuitry to prevent electrical collision chances or to exclude
unwanted noises.
In present commercial market, we can buy Opto-coupler with 10 kV to 20 kV input to output
withstand voltage capacity, with a specification of 25 kV / uS voltage transients.

Types of Optocouplers
There are many different types of Optocouplers are available commercially based on their needs and
switching capabilities. Depending on the use there are mainly four types of optocouplers are available.

1. Opto-coupler which use Photo Transistor.

2. Opto-coupler which use Photo Darlington Transistor.
3. Opto-coupler which use Photo TRIAC.
4. Opto-coupler which use Photo
SCR. Photo-Transistor Optocoupler

In the upper image the internal construction is shown inside a Photo-transistor Optocoupler. The
Transistor type can be anything whether PNP or NPN.
Photo-Transistor can be further of two types depending on the output pin availability. On the
second image on the left, there is additional pin out which is internally connected with transistor's
base. This pin 6 is used to control the sensitivity of the photo-transistor. Often the pin is used to
connect with ground or negative using a high value resistor. In this configuration, false triggering due
to noise or electrical transients can be controlled effectively.
Also, before using Photo-transistor based optocoupler, the user must know the maximum rating of
the transistor. PC816, PC817, LTV817, K847PH are few widely used photo-transistor based
optocoupler. Photo — Transistor based opto-coupler is used in DC circuit related isolation.

Photo-Darlington Transistor Optocoupler

Darlington Transistor is two transistor pair, where one transistor controls other transistor base.
In this configuration the Darlington Transistor provide high gain ability. As usual the LED emits
infrared led and controls the base of the pair transistor.
This type of opto-coupler also used in DC circuit related area for the isolation. The 6th pin which is
internally connected to the base of the transistor, used to control the sensitivity of the transistor as
discussed previously in photo-transistor description. 4N32, 4N33, H21B1, H21B2, H21B3 are few
photo- Darlington based opto-coupler example.

Photo-TRIAC Optocoupler
TRIAC is mainly used where AC based control or switching is needed. The led can be
controlled using DC, and the TRIAC used to control AC. Opto-coupler provide excellent isolation in
this case too. Here is one Triac Applicati The photo-TRIAC based opto-coupler examples
areIL420, 4N35 etc are example of TRIAC based opto-coupler.

Photo-SCR based Optocoupler

SCR stand for Silicon controlled rectifier, SCR also referred as Thyristor. Same as like other
opto-coupler the LED emit Infrared. The SCR is controlled by the intensity of the LED. Photo-SCR
based Opto-coupler used in AC related circuitry. Learn more about Thyristor here.
Few Examples of photo-SCR based opto-couplers are:- MOC307 l, IL400, MOC3072 etc.

Applications of Optocoupler
Opto-coupler can be used for AC detection, DC control related operations. Let's see few
applications of Opto-transistors.
2. Write note on video amplifier. [Nov/Dec 2022]

A video amplifier is a device or module that amplifies buffers and filters analog video signals to
maintain signal fidelity across 75W cabling. Typical applications include video cable extension, video
recording systems, floppy disk head amplifiers, pulsed amplifiers in communications.
 The R1-R2 divider network adjusts the DC level of the video, while the R5-R6 divider
network adjusts the gain. You may replace both the dividers with two 4.7-kilo-ohm (or 5-kilo-ohm)
trimpots for proper adjustment of the DC level and the gain. The 75-ohm resistor (R3) may be
discarded if you feed the video from a high-output-impedance stage.
Although the resistive load in the collector of the transistor provides reasonably good
bandwidth, a peaking coil of 20 to 30 uH can be added in series with R4 to improve its performance
at higher frequencies. With lVPk-Pk signal as the input, the given circuit outputs 3.5VPk-Pk
maximum amplitude at 6.25 MHz without the peaking coil.

3. Draw the functional block diagram of MF 10. [Nov/Dec 2022]

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