M.

Tech Digital Communications

MTDC 16(c)

EMBEDDED SYSTEM DESIGN

Complete Study Material for Semester Examination

Beginner-Friendly | Theory + Formulas + Diagrams | Quick Revision

University Exam 100 Marks

Sessional 50 Marks

Duration 3 Hours

Instruction 3 Periods per week

 UNIT I: Introduction to Embedded Systems

1.1 What is an Embedded System?

An embedded system is a computer system designed to perform a SPECIFIC, dedicated function —
embedded inside a larger device. Examples everywhere: • Washing machine controller → runs wash cycle
program • Automotive ECU → controls engine, brakes, airbags • Smartphone → dozens of embedded
processors! • ATM machine, smart TV, medical devices, industrial robots Key characteristics: • Real-time
operation (must respond within deadline) • Resource-constrained (limited RAM, CPU, power, cost) •
Dedicated function (not general-purpose like PC) • Reliability-critical (often can't crash or restart easily)

1.2 Embedded System Architecture

Typical embedded system block diagram: [Sensors/Inputs] → [Microprocessor/Microcontroller] →
[Actuators/Outputs] ↕ [Memory: ROM, RAM, Flash] [I/O Peripherals: Timer, UART, SPI, I2C]
[Real-Time Clock] Harvard Architecture: Separate buses for instructions and data (most embedded
systems) Von Neumann Architecture: Single bus for instructions and data (general PCs)

1.3 Processor Selection for Embedded Systems

Factors to consider: • Processing power required (MIPS, MFLOPS) • Power consumption (µA for battery
devices!) • On-chip peripherals (do you need timers, ADC, UART built in?) • Memory (on-chip ROM/RAM
vs external) • Cost per unit (microcontrollers from $0.10 to $50) • Development tools availability Types: •
Microcontroller (MCU): CPU + memory + peripherals on ONE chip (e.g., Arduino ATmega328, STM32) •
Microprocessor (MPU): CPU only, needs external memory/peripherals (e.g., ARM Cortex-A) • DSP:
Optimized for signal processing with MAC (multiply-accumulate) hardware • FPGA: Programmable
hardware; very fast parallel processing

1.4 Memory Organization

Memory types in embedded systems: ROM (Read Only Memory): Non-volatile, holds program code.
Types: • Mask ROM: Programmed at manufacture (cheapest but inflexible) • EEPROM: Electrically
erasable/programmable • Flash: Block-erased EEPROM (most common today; can store program AND
data) RAM (Random Access Memory): Volatile (data lost on power off), used for variables/stack • SRAM:
Fast, used in cache; 6 transistors per bit (expensive) • DRAM: Slower, needs refresh; 1 transistor +
capacitor (cheaper, denser) Memory Map: How processor addresses different memory regions Typical
map: ROM at 0x0000 (reset vector here), RAM at 0x8000, Peripherals at 0xFFFF region

1.5 System-on-Chip (SoC)

A SoC integrates ALL major components of a computer on a SINGLE chip: CPU core(s) + GPU + Memory
controller + Communication interfaces + Analog blocks Examples: • Qualcomm Snapdragon
(smartphones) • Apple M1/M2/M3 (Mac computers) • Raspberry Pi's Broadcom BCM2711 Benefits:
Smaller size, lower power, lower cost, faster communication between components
 UNIT II: Device Buses & Networking

2.1 I/O Devices Overview

Timer/Counter: Counts clock pulses; used for: • Generating precise time delays • PWM (Pulse Width
Modulation) for motor control • Measuring pulse widths ADC (Analog-to-Digital Converter): Converts
analog sensor signals to digital numbers. Resolution: N bits → 2^N levels. 12-bit ADC → 4096 levels.
UART (Universal Asynchronous Receiver/Transmitter): Serial communication, 2 wires (TX, RX).
Common for debugging. Speeds: 9600, 115200 baud typical. I2C: 2-wire (SDA + SCL), supports multiple
devices, slow (100kHz-1MHz), used for sensors. SPI: 4-wire (MOSI, MISO, SCK, CS), faster (up to 50
MHz), used for SD cards, displays.

2.2 I2C Protocol in Detail

I2C (Inter-Integrated Circuit) by Philips (now NXP): Bus signals: • SDA: Serial Data • SCL: Serial
Clock (master generates) Communication: 1. START condition: SDA goes LOW while SCL is HIGH 2.
7-bit device address + R/W bit 3. ACK bit from slave (pulls SDA low) 4. Data bytes (8 bits each) +
ACK after each 5. STOP condition: SDA goes HIGH while SCL is HIGH Up to 128 devices on same
2-wire bus (using addresses 0-127)

2.3 CAN Bus (Controller Area Network)

CAN bus is the STANDARD for automotive and industrial embedded systems. Features: •
Multi-master, message-based protocol • Speeds: 125 kbps to 1 Mbps (classic CAN), 8 Mbps (CAN
FD) • ERROR detection: CRC + acknowledgment + frame check • PRIORITY-based access: Lower
message ID = higher priority CAN frame: | SOF | ID(11-bit) | Control | Data(0-8 bytes) | CRC | ACK |
EOF | Used in: Every modern car (100+ ECUs connected by CAN), factory automation, medical
devices

2.4 Advanced Buses: ISA, PCI, PCI-X

ISA (Industry Standard Architecture): Old PC bus, 8/16 bit, 8 MHz. PCI (Peripheral Component
Interconnect): 32/64-bit, 33/66 MHz, 132-528 MB/s. PCI-X: Extended PCI, up to 133 MHz, 1066 MB/s.
PCIe (PCI Express): Current standard, serial lanes (x1, x4, x8, x16), PCIe 5.0 × 16 = 128 GB/s. Used for
GPU, NVMe SSD, high-speed networking.
 UNIT III: Embedded Software Development

3.1 Real-Time Programming Models

Real-time means the system must respond within a GUARANTEED time bound (deadline). Hard
real-time: Missing deadline = catastrophic failure (airbag controller, pacemaker) Soft real-time: Missing
deadline = degraded performance (video streaming, audio) Firm real-time: Missing deadline = result
useless but not catastrophic Programming models: • Round-robin (superloop): while(1) {
check_sensor(); update_display(); send_data(); } • Round-robin with interrupts: Interrupts for urgent
events, background loop for rest • Foreground/Background: ISRs run foreground; main loop is
background • RTOS-based: Multiple tasks with priorities, preemptive scheduling

3.2 Software Development Life Cycle

SDLC phases for embedded: 1. Requirements: What must system do? Timing requirements? Interfaces?
2. Architecture Design: Partition into tasks/modules; choose RTOS if needed 3. Detailed Design:
Design each module; state machines; flowcharts 4. Implementation: Write code (C is dominant language;
assembly for critical sections) 5. Testing: Unit test, integration test, hardware-in-loop testing 6.
Maintenance: Bug fixes, feature updates via firmware updates UML (Unified Modeling Language) is used
to model embedded systems: • State diagrams for control flow • Sequence diagrams for interactions •
Class diagrams for software structure

3.3 Multiprocessor System Software

With multiple processors (MPSoC - Multi-Processor SoC): Software partitioning: Decide which tasks run
on which processor. Criteria: Load balancing, communication overhead, timing constraints.
Inter-processor communication: • Shared memory (fastest; need synchronization) • Message passing
(safer but slower) • Hardware mailboxes/semaphores Complexity: O(n²) communication paths for n
processors → need careful design!
 UNIT IV: RTOS & Inter-Process Communication

4.1 RTOS Fundamentals

An RTOS (Real-Time Operating System) is a lightweight OS that provides: • Task management (create,
schedule, delete tasks) • Memory management • Inter-task communication (queues, semaphores,
mailboxes) • Timer services Popular RTOSs: FreeRTOS (open source, tiny), VxWorks (Tornado),
µC/OS-II, Zephyr, RTEMS RTOS vs General OS: • RTOS: Deterministic, small footprint (few KB), priority
scheduling, real-time guarantees • Linux/Windows: Large, not deterministic (non-RT version), heavy

4.2 Task Scheduling

Preemptive scheduling: Higher priority task can interrupt lower priority task at ANY time. Priority
levels: Each task has a priority (e.g., 0-255, higher number = higher priority) Real-time scheduling
algorithms: • Rate Monotonic (RM): Assign priority based on period (shorter period = higher priority)
Schedulability test: Σ(Ci/Ti) ≤ n(2^(1/n) - 1) ≤ 0.693 (for n tasks) • Earliest Deadline First (EDF): At
any instant, run task with closest deadline Schedulability: Σ(Ci/Ti) ≤ 1 (can use 100% CPU!) Context
switch: Save CPU registers of current task → load registers of next task Typical context switch time:
1-10 µs

4.3 Interrupt Service Routines (ISRs)

Interrupt: Hardware signal that causes CPU to stop and run ISR. Types: • Hardware interrupt: From
external device (timer overflow, UART receive, button press) • Software interrupt: Triggered by
instruction (system call, trap) • Exception: CPU-generated (divide by zero, invalid opcode) ISR rules: •
Keep ISRs SHORT — just set a flag, signal semaphore, put data in buffer • Never use blocking calls in ISR
• Save and restore all registers Interrupt latency: Time from interrupt to first ISR instruction Interrupt
response time: Time from interrupt to when system actually handles it (includes scheduling)

4.4 Synchronization & Resource Management

Semaphore: Counter variable for signaling and mutual exclusion. • Binary semaphore (0/1): Like a
mutex; protect shared resources • Counting semaphore: Count available resources Operations: •
wait(s) / P(s): Decrement; if <0, block calling task • signal(s) / V(s): Increment; if waiting tasks, wake
one up Priority Inversion: Low priority task holds resource needed by high priority task → high
priority task BLOCKED! Solution: Priority Inheritance Protocol — temporarily raise low priority task's
priority. Deadlock: Two tasks each hold a resource the other needs → both stuck forever! Prevention:
Always acquire resources in same ORDER.

4.5 Embedded Linux

Linux kernel has been adapted for embedded use. Key components: • Device drivers: Software interface
between OS and hardware (character, block, network) • Linux kernel: Core OS; handles scheduling,
memory management, file systems • Bootloader: U-Boot is most common embedded bootloader • Root
filesystem: Minimal filesystem with required libraries and tools Building embedded Linux: Yocto Project or
Buildroot → cross-compilation → boot image for target hardware For security: SELinux for access control,
secure boot for bootloader verification
 QUICK REVISION TABLE

Topic Key Points Formula/Keyword

Embedded System Dedicated function; resource-constrained Real-time, reliable

MCU vs MPU MCU=CPU+mem+periph on chip; MPU=CPU only Arduino=MCU, Pi=MPU

SoC CPU+GPU+comms on single chip Snapdragon, Apple M-series

UART Serial; 2-wire (TX,RX); async 115200 baud typical

I2C 2-wire (SDA,SCL); up to 128 devices 100kHz-1MHz

CAN bus Automotive multi-master; priority based 1 Mbps; used in all cars

RTOS Deterministic; preemptive; lightweight FreeRTOS, VxWorks

Rate Monotonic Shorter period=higher priority Σ(C/T)≤0.693

Priority Inversion Low task blocks high task Fix: Priority Inheritance

Semaphore P(s)/V(s); synchronization wait=P; signal=V