Introduction to

CMOS VLSI
Design

Layout, Fabrication, and

Elementary Logic Design
 Introduction
❑ Integrated circuits: many transistors on one chip.
– Very Large Scale Integration (VLSI): very many
❑ Metal Oxide Semiconductor (MOS) transistor
– Fast, cheap, low-power transistors
– Complementary: mixture of n- and p-type leads to less power
❑ Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
❑ Rest of the course: How to build a good CMOS chip

Fabrication and Layout CMOS VLSI Design Slide 2

 Silicon Lattice
❑ Transistors are built on a silicon substrate
❑ Silicon is a Group IV material
❑ Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

Fabrication and Layout CMOS VLSI Design Slide 3

 Dopants
❑ Silicon is a semiconductor
❑ Pure silicon has no free carriers and conducts poorly
❑ Adding dopants increases the conductivity
❑ Group V: extra electron (n-type)
❑ Group III: missing electron, called hole (p-type)

Fabrication and Layout CMOS VLSI Design Slide 4

 p-n Junctions
❑ A junction between p-type and n-type semiconductor forms a diode.
❑ Current flows only in one direction

p-type n-type

anode cathode

Fabrication and Layout CMOS VLSI Design Slide 5

 nMOS Transistor
❑ Four terminals: gate, source, drain, body
❑ Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS) capacitor
– Even though gate is Source Gate Drain
Polysilicon
no longer made of metal SiO2

n+ n+

p bulk Si

Fabrication and Layout CMOS VLSI Design Slide 6

 nMOS Operation
❑ Body is commonly tied to ground (0 V)
❑ When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

Fabrication and Layout CMOS VLSI Design Slide 7

 nMOS Operation
❑ When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from source through
channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

Fabrication and Layout CMOS VLSI Design Slide 8

 pMOS Transistor
❑ Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

Fabrication and Layout CMOS VLSI Design Slide 9

 Power Supply Voltage
❑ GND = 0 V
❑ In 1980’s, VDD = 5V
❑ VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
❑ VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

Fabrication and Layout CMOS VLSI Design Slide 10

 Transistors as Switches
❑ We can view MOS transistors as electrically controlled switches
❑ Voltage at gate controls path from source to drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

Fabrication and Layout CMOS VLSI Design Slide 11

 CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
Fabrication and Layout CMOS VLSI Design Slide 12
 CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND
Fabrication and Layout CMOS VLSI Design Slide 13
 CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
Fabrication and Layout CMOS VLSI Design Slide 14
 CMOS NAND Gate
A B Y
0 0
0 1 Y
1 0 A
1 1
B

Fabrication and Layout CMOS VLSI Design Slide 15

 CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF

Fabrication and Layout CMOS VLSI Design Slide 16

 CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1
B=1
ON

Fabrication and Layout CMOS VLSI Design Slide 17

 CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF

Fabrication and Layout CMOS VLSI Design Slide 18

 CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON

Fabrication and Layout CMOS VLSI Design Slide 19

 CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

Fabrication and Layout CMOS VLSI Design Slide 20

 3-input NAND Gate
❑ Y pulls low if ALL inputs are 1
❑ Y pulls high if ANY input is 0

Fabrication and Layout CMOS VLSI Design Slide 21

 3-input NAND Gate
❑ Y pulls low if ALL inputs are 1
❑ Y pulls high if ANY input is 0

Y
A
B
C

Fabrication and Layout CMOS VLSI Design Slide 22

 CMOS Fabrication
❑ CMOS transistors are fabricated on silicon wafer
❑ Lithography process similar to printing press
❑ On each step, different materials are deposited or etched
❑ Easiest to understand by viewing both top and cross-section of wafer in
a simplified manufacturing process

Fabrication and Layout CMOS VLSI Design Slide 23

 Inverter Cross-section
❑ Typically use p-type substrate for nMOS transistor
– Requires n-well for body of pMOS transistors
– Several alternatives: SOI, twin-tub, etc.
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

Fabrication and Layout CMOS VLSI Design Slide 24

 Well and Substrate Taps
❑ Substrate must be tied to GND and n-well to VDD
❑ Metal to lightly-doped semiconductor forms poor connection called
Shottky Diode
❑ Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

Fabrication and Layout CMOS VLSI Design Slide 25

 Inverter Mask Set
❑ Transistors and wires are defined by masks
❑ Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

Fabrication and Layout CMOS VLSI Design Slide 26

 Detailed Mask Views
❑ Six masks n well

– n-well
– Polysilicon
Polysilicon

– n+ diffusion
– p+ diffusion n+ Diffusion

– Contact p+ Diffusion

– Metal Contact

Metal

Fabrication and Layout CMOS VLSI Design Slide 27

 Fabrication Steps
❑ Start with blank wafer
❑ Build inverter from the bottom up
❑ First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

Fabrication and Layout CMOS VLSI Design Slide 28

 Oxidation
❑ Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

Fabrication and Layout CMOS VLSI Design Slide 29

 Photoresist
❑ Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

Fabrication and Layout CMOS VLSI Design Slide 30

 Lithography
❑ Expose photoresist through n-well mask
❑ Strip off exposed photoresist

Photoresist
SiO2

p substrate

Fabrication and Layout CMOS VLSI Design Slide 31

 Etch
❑ Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
❑ Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

Fabrication and Layout CMOS VLSI Design Slide 32

 Strip Photoresist
❑ Strip off remaining photoresist
– Use mixture of acids called piranah etch
❑ Necessary so resist doesn’t melt in next step

SiO2

p substrate

Fabrication and Layout CMOS VLSI Design Slide 33

 n-well
❑ n-well is formed with diffusion or ion implantation
❑ Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
❑ Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2

n well

Fabrication and Layout CMOS VLSI Design Slide 34

 Strip Oxide
❑ Strip off the remaining oxide using HF
❑ Back to bare wafer with n-well
❑ Subsequent steps involve similar series of steps

n well
p substrate

Fabrication and Layout CMOS VLSI Design Slide 35

 Polysilicon
❑ Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
❑ Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

Fabrication and Layout CMOS VLSI Design Slide 36

 Polysilicon Patterning
❑ Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

Fabrication and Layout CMOS VLSI Design Slide 37

 Self-Aligned Process
❑ Use oxide and masking to expose where n+ dopants should be diffused
or implanted
❑ N-diffusion forms nMOS source, drain, and n-well contact

n well
p substrate

Fabrication and Layout CMOS VLSI Design Slide 38

 N-diffusion
❑ Pattern oxide and form n+ regions
❑ Self-aligned process where gate blocks diffusion
❑ Polysilicon is better than metal for self-aligned gates because it doesn’t
melt during later processing

n+ Diffusion

n well
p substrate

Fabrication and Layout CMOS VLSI Design Slide 39

 N-diffusion
❑ Historically dopants were diffused
❑ Usually ion implantation today
❑ But regions are still called diffusion

n+ n+ n+

n well
p substrate

Fabrication and Layout CMOS VLSI Design Slide 40

 N-diffusion
❑ Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

Fabrication and Layout CMOS VLSI Design Slide 41

 P-Diffusion
❑ Similar set of steps form p+ diffusion regions for pMOS source and
drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate

Fabrication and Layout CMOS VLSI Design Slide 42

 Photolithography

Fabrication and Layout CMOS VLSI Design Slide 43

 Contacts
❑ Now we need to wire together the devices
❑ Cover chip with thick field oxide
❑ Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

Fabrication and Layout CMOS VLSI Design Slide 44

 Metallization
❑ Sputter on aluminum over whole wafer
❑ Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

Fabrication and Layout CMOS VLSI Design Slide 45

 Metallization

Fabrication and Layout CMOS VLSI Design Slide 46

 Encapsulation

Fabrication and Layout CMOS VLSI Design Slide 47

 Layout
❑ Chips are specified with set of masks
❑ Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power)
❑ Feature size f = distance between source and drain
– Set by minimum width of polysilicon
❑ Feature size improves 30% every 3 years or so
❑ Normalize for feature size when describing design rules
❑ Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process

Fabrication and Layout CMOS VLSI Design Slide 48

 Simplified Design Rules
❑ Conservative rules to get you started

Fabrication and Layout CMOS VLSI Design Slide 49

 Inverter Layout
❑ Transistor dimensions specified as Width / Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– For 0.6 mm process, W=1.2 mm, L=0.6 mm

Fabrication and Layout CMOS VLSI Design Slide 50

 Summary
❑ MOS Transistors are stack of gate, oxide, silicon
❑ Can be viewed as electrically controlled switches
❑ Build logic gates out of switches
❑ Draw masks to specify layout of transistors

❑ Now you know everything necessary to start designing schematics and

layout for a simple chip!

Fabrication and Layout CMOS VLSI Design Slide 51

Oxidation of Silicon
Oxidation of Silicon
Functions of Silicon
Functions of Silicon
Functions of Silicon
Functions of Silicon
Functions of Silicon
Techniques of Oxidation
Thermal Oxidation
Wet Vs Dry Oxidation
 Static CMOS Inverter DC Characteristics
Relationships between voltages for the three regions of operation of a CMOS inverter

Circuits and Layout CMOS VLSI Design Slide 64

 Static CMOS Inverter DC Characteristics
Relationships between voltages for the three regions of operation of a CMOS inverter

Summary of CMOS inverter operation

Circuits and Layout CMOS VLSI Design Slide 65

 Static CMOS Inverter DC Characteristics
Noise Margin
This parameter allows you to determine the allowable
noise voltage on the input of a gate so that the output
will not be corrupted.

NML is defined as the difference in maximum LOW input

voltage recognized by the receiving gate and the maximum
LOW output voltage produced by the driving gate

The value of NMH is the difference between the minimum

HIGH output voltage of the driving gate and the minimum
HIGH input voltage recognized by the receiving gate.

Circuits and Layout CMOS VLSI Design Slide 66

SUM OF PRODUCTS (SOP) FORM AND IN
PRODUCT OF SUMS (POS) FORM
 CMOS Technology Logic Circuit Structures

❑ Many different logic circuits utilizing CMOS technology have been

invented and used in various applications. These can be divided into
three types or families of circuits:
– Complementary Logic
• Standard CMOS
• Clocked CMOS (C2MOS)
• BICMOS (CMOS logic with Bipolar driver)
– Ratio Circuit Logic Dynamic Logic:
• Pseudo-NMOS CMOS Domino Logic
• Saturated NMOS Load NP Domino Logic (also called Zipper CMOS)
NORA Logic
• Saturated PMOS Load Cascade voltage Switch Logic (CVSL)
• Depletion NMOS Load (E/D) Sample-Set Differential Logic (SSDL)
• Source Follower Pull-up Logic (SFPL) Pass-Transistor Logic

Circuits and Layout CMOS VLSI Design Slide 68

 Enhancement and Depletion Type MOSFETs

Circuits and Layout CMOS VLSI Design Slide 69

 Logic Styles Comparison
(Ratioed Circuits)

Conceptually, the ratioed gate consists of an nMOS pulldown

network and some pullup device called the static load

Resistive Load Enhancement Load Depleted Load Pseudo-nMOS

Circuits and Layout CMOS VLSI Design Slide 70

 Logic Styles Comparison
(Ratioed Circuits)
Power
Logic Style Structure Speed Area Noise Margin Applications
Consumption
Uses complementary PMOS
Low (static) but Larger due to dual High (rail-to-rail Digital circuits, low-
CMOS and NMOS transistors for pull- Moderate to high
higher dynamic transistors swing) power systems
up and pull-down networks.
Pull-down network is NMOS, Higher (static Faster than CMOS
Pseudo- Smaller due to fewer Moderate (lower
and pull-up is a single PMOS power (due to fewer High-speed circuits
NMOS transistors than CMOS)
transistor always ON. dissipation) transistors)
Uses only NMOS transistors;
Enhancement High (static and Slower (pull-up Low (weaker pull-up Early digital circuits,
requires external pull-up Smaller than CMOS
NMOS dynamic) limited by resistors) strength) low complexity
resistors.
NMOS pull-down network with
Resistive- a resistive load (external Low (limited voltage Early integrated
Moderate to high Moderate Compact
load NMOS resistor or transistor in linear swing) circuits
region).
NMOS pull-down network with Lower than
Depletion- Higher than High-density NMOS
a depletion-mode NMOS as resistive-load Compact Moderate
load NMOS resistive-load NMOS circuits
the load device. NMOS

Circuits and Layout CMOS VLSI Design Slide 71

 Logic Styles Comparison
Cascode Voltage Switch Logic (CVSL)

It uses both true and complementary input signals and

computes both true and complementary outputs using a
pair of nMOS pulldown networks.

The pulldown network f implements the logic function as

in a static CMOS gate, while f uses inverted inputs
feeding transistors arranged in the conduction
complement.

For any given input pattern, one of the pulldown

networks will be ON and the other OFF

Circuits and Layout CMOS VLSI Design Slide 72

 AOI (AND-OR-INVERT) CMOS Gate

• AOI complex CMOS gate can be used to directly implement a sum-of-

products Boolean function
• The pull-down N-tree can be implemented as follows:
– Product terms yield series-connected NMOS transistors
– Sums are denoted by parallel-connected legs
– The complete function must be an inverted representation
• The pull-up P-tree is derived as the dual of the N-tree

Circuits and Layout CMOS VLSI Design Slide 73

 OAI (OR-AND-INVERT) CMOS Gate

• An Or-And-Invert (OAI) CMOS gate is similar to the AOI gate

except that it is an implementation of product-of-sums
realization of a function
• The N-tree is implemented as follows:
– Each product term is a set of parallel transistors for each input in
the term
– All product terms (parallel groups) are put in series
– The complete function is again assumed to be an inverted
representation
• The P-tree can be implemented as the dual of the N-tree
• Note: AO and OA gates (non-inverted function representation)
can be implemented directly on the P-tree if inverted inputs are
available

Circuits and Layout CMOS VLSI Design Slide 74

 CMOS Gate Design
❑ Activity:
– Sketch a 4-input CMOS NAND gate

Circuits and Layout CMOS VLSI Design Slide 75

 CMOS Gate Design
❑ Activity:
– Sketch a 4-input CMOS NOR gate

A
B
C
D
Y

Circuits and Layout CMOS VLSI Design Slide 76

 Complementary CMOS
❑ Complementary CMOS logic gates
– nMOS pull-down network pMOS

– pMOS pull-up network pull-up

network
inputs
– a.k.a. static CMOS output

nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

Circuits and Layout CMOS VLSI Design Slide 77

 Series and Parallel
❑
a a a a
nMOS: 1 = ON g1
a
0 0 1 1

❑
g2
pMOS: 0 = ON b
0
b
1
b
0
b
1
b
(a) OFF OFF OFF ON

❑ Series: both must be ON a a a a a

❑ Parallel: either can be ON g1

g2
0

0
0

1
1

0
1

1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

Circuits and Layout CMOS VLSI Design Slide 78

 Conduction Complement
❑ Complementary CMOS gates always produce 0 or 1
❑ Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS Y
A
B
❑ Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel

Circuits and Layout CMOS VLSI Design Slide 79

 Compound Gates
❑ Compound gates can do any inverting function
❑ Ex: Y = (A.B + C.D)’

A
B
C
D
Y

Circuits and Layout CMOS VLSI Design Slide 80

 Example: O3AI
❑ Y = ((A+B+C).D)’

Circuits and Layout CMOS VLSI Design Slide 81

 Example: O3AI
❑ Y = ((A+B+C).D)’

pMOS
pull-up
network
inputs
output

nMOS
pull-down
network

Circuits and Layout CMOS VLSI Design Slide 82

 Signal Strength
❑ Strength of signal
– How close it approximates ideal voltage source
❑ VDD and GND rails are strongest 1 and 0
❑ nMOS pass strong 0
– But degraded or weak 1
❑ pMOS pass strong 1
– But degraded or weak 0
❑ Thus nMOS are best for pull-down network

Circuits and Layout CMOS VLSI Design Slide 83

 Pass Transistors
❑ Transistors can be used as switches
a a a a a
0 0 1 1
g1
g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON

a a a a a
0 0 1 1
g1
g2
0 1 0 1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

Circuits and Layout CMOS VLSI Design Slide 84

 Pass Transistors
❑ Transistors can be used as switches

Y
A
B

Circuits and Layout CMOS VLSI Design Slide 85

 Transmission Gates
❑ Pass transistors produce degraded outputs
❑ Transmission gates pass both 0 and 1 well

Circuits and Layout CMOS VLSI Design Slide 86

 Transmission Gates
❑ Pass transistors produce degraded outputs
❑ Transmission gates pass both 0 and 1 well
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)

Circuits and Layout CMOS VLSI Design Slide 87

 Tristates
❑ Tristate buffer produces Z when not enabled

EN A Y A
0 0
B
0 1
1 0 C D
1 1 Y
D
A B C

Circuits and Layout CMOS VLSI Design Slide 88

 Tristates
❑ Tristate buffer produces Z when not enabled

EN A Y A
0 0 Z
B
0 1 Z
1 0 0 C D
1 1 1 Y
D
A B C

Circuits and Layout CMOS VLSI Design Slide 89

 Nonrestoring Tristate
❑ Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y
g

s d

s d

Circuits and Layout CMOS VLSI Design Slide 90

 Tristate Inverter
❑ Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
g g=0 Input g = 1 Output
s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output

g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1

Circuits and Layout CMOS VLSI Design Slide 91

 Tristate Inverter
❑ Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

Circuits and Layout CMOS VLSI Design Slide 92

 Multiplexers
❑ 2:1 multiplexer chooses between two inputs

EN

A Y
S D1 D0 Y
0 X 0 EN

0 X 1 A Y

1 0 X EN

1 1 X

Circuits and Layout CMOS VLSI Design Slide 93

 Multiplexers
❑ 2:1 multiplexer chooses between two inputs

EN

A Y
S D1 D0 Y
0 X 0 0 EN

0 X 1 1 A Y

1 0 X 0 EN

1 1 X 1

Circuits and Layout CMOS VLSI Design Slide 94

 Gate-Level Mux Design
EN

❑ A

EN
Y

❑ How many transistors are needed?

Circuits and Layout CMOS VLSI Design Slide 95

 Gate-Level Mux Design
EN

❑ A

EN
Y

❑ How many transistors are needed? 20

A
EN
Y
EN

Circuits and Layout CMOS VLSI Design Slide 96

 Transmission Gate Mux
❑ Nonrestoring mux uses two transmission gates

Circuits and Layout CMOS VLSI Design Slide 97

 Transmission Gate Mux
❑ Nonrestoring mux uses two transmission gates
– Only 4 transistors
A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A

Circuits and Layout CMOS VLSI Design Slide 98

 Inverting Mux
❑ Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
❑ Noninverting multiplexer adds an inverter

D0 0
Y
D1 1

Circuits and Layout CMOS VLSI Design Slide 99

 4:1 Multiplexer
❑ 4:1 mux chooses one of 4 inputs using two selects

Circuits and Layout CMOS VLSI Design Slide 100

 4:1 Multiplexer
❑ 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates

Y = SD1 + SD0 (to many transistors)

Circuits and Layout CMOS VLSI Design Slide 101