OPERATORS:

1)Arithmetic:

module hello;
reg [7:0] a ;
reg [7:0] b;
wire [31:0] sum , diff , mul , mod;
assign sum=a+b;
assign diff=a-b;
assign mul=a*b;
assign mod=a%b;
initial
begin
a=6.8;
b=3.4;
$display("a + b = %d",sum);
$display("a - b = %d",diff);
$display("a * b = %d",mul);
$display("a % b = %d",mod);
$finish;
end
endmodule
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
2) Bitwise:

module hello;
reg [7:0] a ;
reg [7:0] b;
initial
begin
a=8'b10101010;
b=8'b11001100;
$display("a&b=%b",a&b);
$display("a&b=%d",a&b);
$display("a|b=%b",a|b);
$display("a|b=%d",a|b);
$display("a^b=%b",a^b);
$display("a^b=%d",a^b);
$display("~a=%b",~a);
$display("~a=%d",~a);
$finish;
end
endmodule

OUTPUT:
a&b=10001000
a&b=136
a|b=11101110
a|b=238
a^b=01100110
a^b=102
~a=01010101
~a= 85
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
LOOPING STATEMENTS:

3)Relational:
module hello;
reg [31:0] a, b;

initial begin
a = 45;
b = 10;
if (a > b) begin
$display("A is greater:%d", a);
end
else begin
$display("B is greater: %d", b);
end
$finish;
end
endmodule

OUTPUT:
A is greater: 45

3-2)Cascaded if:

module num;
reg[7:0] result;
reg[7:0] a,b;
initial begin
a=45;
b=67;
if(a>b) begin
result=a-b;
end
else if (a<b) begin
result=b-a;
end
else begin
result=0;
end
$display(result);
end
endmodule

OUTPUT:
22
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
4)Nested-if:

module hello;
reg [7:0] a, b;
reg [7:0] result;
initial begin
a = 45;
b = 10;
if (a > b) begin
if(a-b>10) begin
result =a-b;
end
else begin
result =b-a;
end
 end
else begin
result=0;
end
$display(result);
$finish;
end
endmodule

OUTPUT:
35
---------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
5)Switch:

module num;
reg [7:0] a, b;
reg [7:0] result;
initial begin
a = 2;
b = 10;
case(a)
0: result=b+1;
1: result=b+2;
2: result=b+3;
3: result=b+4;
4: result=b+5;
endcase
$display(result);
$finish;
end
endmodule

OUTPUT:
13
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
6) For loop:

module hello;
reg [7:0] a, b;
reg [7:0] result;
initial begin
a = 5;
b = 3;
result=0;
repeat(a) begin
result=result+b;
end
$display(result);
$finish;
end
endmodule

OUTPUT
15

2nd Method:

module hello;
reg [7:0] a, b,i;
reg [7:0] result;
initial begin
a = 5;
b = 3;
result=0;
for(i=0;i<a;i++)begin
result=result+b;
end
$display(result);
$finish;
end
endmodule

OUTPUT:
15
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
7)While loop:

module hello;
reg [7:0] a, b,i;
reg [7:0] result;
initial begin
a = 10;
b = 15;
result=a;
while(result<=b) begin
$display(result);
result=result+1;
end
$finish;
end
endmodule

OUTPUT:
10
11
12
13
14
15
----------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------
DATA TYPES::

1)Integer :

module num;
integer a, b;
integer sum,sub,mul;
initial begin
a=45;
b=65;
sum=a+b;
sub=a-b;
mul=a*b;
$display(sum);
$display(sub);
$display(mul);
 $finish;
end
endmodule
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
2)Float:

module num;
real a, b;
real sum,sub,mul;
initial begin
a=45.87;
b=65;
sum=a+b;
sub=a-b;
mul=a*b;

$display(sum);
$display(sub);
$display(mul);
$finish;
end
endmodule
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
3)String:

module num;
reg[8*11:1] a;
reg[8*5:1] b;
reg[8*11:1]c;
initial begin
a="sathvika";
b="hai mahesh";
c="hai sathviaa";
$display("%s",a);
$display("%s",b);
$display("%s",c);
$finish;
end
endmodule

OUTPUT:

1) sathvika ---------->for reg[8*11:1] a; reg[8*5:1] b ;reg[8*11:1]c;

ahesh
ai sathviaa

2) sathvika ----------->reg[8*31:1] a; reg[8*5:1] b; reg[8*1:1]c;

ahesh
a
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
5)Time:

module num;
time a;
initial begin
a=$time;
$display("%t",a);
 $finish;
end
endmodule

OUTPUT: 0
-----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
ARRAYS:

1)print array elements:

module num;
parameter size=5;
reg [7:0] i;
reg[7:0] a[0:size-1];
initial begin
a[0]=45;
a[1]=65;
a[2]=45;
a[3]=15;
a[4]=12;
i=0;
while(i<size) begin
$display("%d",a[i]);
i=i+1;
end
$finish;
end
endmodule

OUTPUT:
45
65
45
15
12
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
FUNCTION:

1)Basic function program:

module num;
function [31:0] add;
input[31:0] a,b;
begin
add=a+b;
end
endfunction
reg [31:0] a ,b;
integer sum;
initial begin
a=89;
b=24;
sum=add(a,b);
$display(sum);
$finish;
end
endmodule
OUTPUT:
113
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
** AND PROGRAM with GTKWAVE:

module and_gate(
input wire a,
input wire b,
output wire out
);
assign out = a&b;
endmodule

////testbench program:

module and_gate_tb;
reg a,b;
wire out;
and_gate uut(
.a(a),
.b(b),
.out(out)
);
initial begin
$dumpfile("and_gate_tb.vcd");
$dumpvars(0,and_gate_tb);
a=0;b=0;
#10;
a=0;b=1;
#10;
a=1;b=0;
#10;
a=1;b=1;
#10;
$finish;
end
endmodule

OUTPUT:STEPS
iverilog -o [Link] ./and.v ./and_tb.v
vvp ./[Link]
gtkwave and_gate_tb.vcd
->output in gtkwave.
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
** OR PROGRAM with GTKWAVE:

module or_gate(
input wire a,
input wire b,
output wire out
);
assign out = a|b;
endmodule

////testbench program:

module or_gate_tb;
reg a,b;
wire out;
and_gate uut(
.a(a),
.b(b),
.out(out)
);
initial begin
$dumpfile("or_gate_tb.vcd");
$dumpvars(0,or_gate_tb);
a=0;b=0;
#10;
a=0;b=1;
#10;
a=1;b=0;
#10;
a=1;b=1;
#10;
$finish;
end
endmodule

OUTPUT:STEPS
iverilog -o [Link] ./or.v ./or_tb.v
vvp ./[Link]
gtkwave or_gate_tb.vcd
->output in gtkwave.

***similar program for NAND,NOR,XOR..etc.

----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
**HALF ADDER:

module half_adder(
input wire a,
input wire b,
output wire sum,
output wire carry
);
assign sum=a^b;
assign carry=a&b;
endmodule

////testbench:

module half_adder_tb;
reg a,b;
wire sum, carry;
half_adder uut(
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
initial begin
$dumpfile("half_adder_tb.vcd");
$dumpvars(0,half_adder_tb);
$display("testing half adder");
a=0;b=0;
#10;
$display("input: %b + %b,sum : %b,carry : %b", a , b , sum , carry);
 a=0;b=1;
#10;
$display("input: %b + %b,sum : %b,carry : %b", a , b , sum , carry);
a=1;b=0;
#10;
$display("input: %b + %b,sum : %b,carry : %b", a , b , sum , carry);
a=1;b=1;
#10;
$display("input: %b + %b,sum : %b,carry : %b", a , b , sum , carry);
$finish;
end
endmodule
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
**FULL ADDER:

module full_adder(
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire carry
);
assign sum=a^b^cin;
assign carry=(a&b)|(b&cin)|(a&cin);
endmodule

//testbench:
module full_adder_tb;
reg a,b,cin;
wire sum, carry;
full_adder uut(
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.carry(carry)
);
initial begin
$dumpfile("full_adder_tb.vcd");
$dumpvars(0,full_adder_tb);
$display("testing full adder");
a=0;b=0;cin=0;
#10;
$display("input: %b + %b + %b, sum : %b,carry : %b", a , b , cin, sum , carry);
a=0;b=0;cin=1;
#10;
$display("input: %b + %b + %b, sum : %b,carry : %b", a , b , cin, sum , carry);
a=0;b=1;cin=0;
#10;
$display("input: %b + %b + %b, sum : %b,carry : %b", a , b , cin, sum , carry);
a=0;b=1;cin=1;
#10;
$display("input: %b + %b + %b, sum : %b,carry : %b", a , b , cin, sum , carry);
a=1;b=0;cin=0;
#10;
$display("input: %b + %b + %b, sum : %b,carry : %b", a , b , cin, sum , carry);
a=1;b=0;cin=1;
#10;
$display("input: %b + %b + %b, sum : %b,carry : %b", a , b , cin, sum , carry);
 a=1;b=1;cin=0;
#10;
$display("input: %b + %b + %b, sum : %b,carry : %b", a , b , cin, sum , carry);
a=1;b=1;cin=1;
#10;
$display("input: %b + %b + %b, sum : %b,carry : %b", a , b , cin, sum , carry);
$finish;
end
endmodule
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
**HALF SUBTRACTOR:

module half_sub(
input wire a,
input wire b,
output wire diff,
output wire borrow
);
assign diff=a^b;
assign borrow=(~a)&b;
endmodule

//testbench:

module half_sub_tb;
reg a,b;
wire diff, borrow;
half_sub uut(
.a(a),
.b(b),
.diff(diff),
.borrow(borrow)
);
initial begin
$dumpfile("half_sub_tb.vcd");
$dumpvars(0,half_sub_tb);
$display("testing half subtractor");
a=0;b=0;
#10;
$display("input: %b - %b,diff : %b,borrow : %b", a , b , diff , borrow);
a=0;b=1;
#10;
$display("input: %b - %b,diff : %b,borrow : %b", a , b , diff , borrow);
a=1;b=0;
#10;
$display("input: %b - %b,diff : %b,borrow : %b", a , b , diff , borrow);
a=1;b=1;
#10;
$display("input: %b - %b,diff : %b,borrow : %b", a , b , diff , borrow);
$finish;
end
endmodule
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
**FULL SUBTRACTOR:

module full_sub(
input wire a,
input wire b,
 input wire bin,
output wire diff,
output wire bout
);
assign diff=a^b^bin;
assign bout=((~a)&(bin))|((~a)&(b))|((b)&(bin));
endmodule

//testbench:
module full_sub_tb;
reg a,b,bin;
wire diff, bout;
full_sub uut(
.a(a),
.b(b),
.bin(bin),
.diff(diff),
.bout(bout)
);
initial begin
$dumpfile("full_sub_tb.vcd");
$dumpvars(0,full_sub_tb);
$display("testing full subtractor");
a=0;b=0;bin=0;
#10;
$display("input: %b - %b - %b, diff : %b,bout : %b", a , b , bin, diff , bout);
a=0;b=0;bin=1;
#10;
$display("input: %b - %b - %b, diff : %b,bout : %b", a , b , bin, diff , bout);
a=0;b=1;bin=0;
#10;
$display("input: %b - %b - %b, diff : %b,bout : %b", a , b , bin, diff , bout);
a=0;b=1;bin=1;
#10;
$display("input: %b - %b - %b, diff : %b,bout : %b", a , b , bin, diff , bout);
a=1;b=0;bin=0;
#10;
$display("input: %b - %b - %b, diff : %b,bout : %b", a , b , bin, diff , bout);
a=1;b=0;bin=1;
#10;
$display("input: %b - %b - %b, diff : %b,bout : %b", a , b , bin, diff , bout);
a=1;b=1;bin=0;
#10;
$display("input: %b - %b - %b, diff : %b,bout : %b", a , b , bin, diff , bout);
a=1;b=1;bin=1;
#10;
$display("input: %b - %b - %b, diff : %b,bout : %b", a , b , bin, diff , bout);
$finish;
end
endmodule
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
**FULL SUBTRACTOR USING HALF SUBTRACTOR:

//1st half sub:

module half_sub(
input wire a,
input wire b,
output wire diff,
output wire borrow
);
assign diff=a^b;
assign borrow=(~a)&b;
endmodule

2nd full_sub_using_half:
module full_sub_using_half(
input wire a,
input wire b,
input wire bin,
output wire diff,
output wire borrow
);
wire diff1, borrow1, borrow2;
half_sub uut1 (
.a(a),
.b(b),
.diff(diff1),
.borrow(borrow1)
);

half_sub uut2 (
.a(diff1),
.b(bin),
.diff(diff),
.borrow(borrow2)
);
assign borrow = borrow1 | borrow2;
endmodule

3rd testbench:
module full_sub_using_half_tb;
reg a, b, bin;
wire diff, borrow;
full_sub_using_half uut (
.a(a),
.b(b),
.bin(bin),
.diff(diff),
.borrow(borrow)
);
initial begin
$dumpfile("full_sub_using_half_tb.vcd");
$dumpvars(0, full_sub_using_half_tb);
$display("Testing Full Subtractor using Half Subtractors");

// Test cases
a = 0; b = 0; bin = 0;
#10;
$display("input: %b - %b - %b, diff: %b, borrow: %b", a, b, bin, diff, borrow);

a = 0; b = 0; bin = 1;
#10;
$display("input: %b - %b - %b, diff: %b, borrow: %b", a, b, bin, diff, borrow);

a = 0; b = 1; bin = 0;
#10;
$display("input: %b - %b - %b, diff: %b, borrow: %b", a, b, bin, diff, borrow);

a = 0; b = 1; bin = 1;
 #10;
$display("input: %b - %b - %b, diff: %b, borrow: %b", a, b, bin, diff, borrow);

a = 1; b = 0; bin = 0;
#10;
$display("input: %b - %b - %b, diff: %b, borrow: %b", a, b, bin, diff, borrow);

a = 1; b = 0; bin = 1;
#10;
$display("input: %b - %b - %b, diff: %b, borrow: %b", a, b, bin, diff, borrow);

a = 1; b = 1; bin = 0;
#10;
$display("input: %b - %b - %b, diff: %b, borrow: %b", a, b, bin, diff, borrow);

a = 1; b = 1; bin = 1;
#10;
$display("input: %b - %b - %b, diff: %b, borrow: %b", a, b, bin, diff, borrow);

$finish;
end
endmodule
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
**FULL ADDER USING HALF:

->half adder:
module half_adder(
input wire a,
input wire b,
output wire sum,
output wire carry
);
assign sum=a^b;
assign carry=a&b;
endmodule

->full adder using half:

module full_adder_using_half(
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire carry
);
wire sum1, carry1, carry2;
half_adder uut1 (
.a(a),
.b(b),
.sum(sum1),
.carry(carry1)
);
half_adder uut2 (
.a(sum1),
.b(cin),
.sum(sum),
.carry(carry2)
);
assign carry = carry1 | carry2;
endmodule
-> testbench:
module full_adder_using_half_tb;
reg a, b, cin;
wire sum, carry;
full_adder_using_half uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.carry(carry)
);
initial begin
$dumpfile("full_adder_using_half_tb.vcd");
$dumpvars(0, full_adder_using_half_tb);
$display("Testing Full adder using Half adder");

// Test cases
a = 0; b = 0; cin = 0;
#10;
$display("input: %b + %b + %b, sum: %b, carry: %b", a, b, cin, sum, carry);

a = 0; b = 0; cin = 1;
#10;
$display("input: %b + %b + %b, sum: %b, carry: %b", a, b, cin, sum, carry);

a = 0; b = 1; cin = 0;
#10;
$display("input: %b + %b + %b, sum: %b, carry: %b", a, b, cin, sum, carry);

a = 0; b = 1; cin = 1;
#10;
$display("input: %b + %b + %b, sum: %b, carry: %b", a, b, cin, sum, carry);

a = 1; b = 0; cin = 0;
#10;
$display("input: %b + %b + %b, sum: %b, carry: %b", a, b, cin, sum, carry);

a = 1; b = 0; cin = 1;
#10;
$display("input: %b + %b + %b, sum: %b, carry: %b", a, b, cin, sum, carry);

a = 1; b = 1; cin = 0;
#10;
$display("input: %b + %b + %b, sum: %b, carry: %b", a, b, cin, sum, carry);

a = 1; b = 1; cin = 1;
#10;
$display("input: %b + %b + %b, sum: %b, carry: %b", a, b, cin, sum, carry);
$finish;
end
endmodule
-----------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
**MUX(4:1):

module mux(
input wire a,
input wire b,
input wire c,
input wire d,
 input wire s0,
input wire s1,
output reg out
);
always @(*) begin
case ({s0,s1})
2'b00: out=a;
2'b01: out=b;
2'b10: out=c;
2'b11: out=d;
endcase
end

//testbench:

module mux_tb;
reg a,b,c,d ,s0,s1;
wire out;
mux uut(
.a(a),
.b(b),
.c(c),
.d(d),
.s0(s0),
.s1(s1),
.out(out)
);
initial begin
$dumpfile("mux_tb.vcd");
$dumpvars(0,mux_tb);
$display("testing mux-4:1");
a=0; b=0; c=0; d=1; s0=0; s1=0;
#10;
$display("input=%d %d %d %d, output=%b",a,b,c,d,out);
a=0; b=0; c=1; d=1; s0=0; s1=1;
#10;
$display("input=%d %d %d %d, output=%b",a,b,c,d,out);
a=0; b=1; c=0; d=1; s0=1; s1=0;
#10;
$display("input=%d %d %d %d, output=%b",a,b,c,d,out);
a=1; b=1; c=1; d=1; s0=1; s1=1;
#10;
$display("input=%d %d %d %d, output=%b",a,b,c,d,out);
$finish;
end
endmodule
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
**DEMUX(1:4):

module demux(
input wire in,
input wire s0,
input wire s1,
output reg a,
output reg b,
output reg c,
output reg d
);
always @(*) begin
 a = 0;
b = 0;
c = 0;
d = 0;

case ({s0,s1})
2'b00: a = in;
2'b01: b = in;
2'b10: c = in;
2'b11: d = in;
endcase
end
endmodule

//testbench:
module demux_tb;
reg in,s0,s1;
wire a,b,c,d;
demux uut(
.a(a),
.b(b),
.c(c),
.d(d),
.s0(s0),
.s1(s1),
.in(in)
);
initial begin
$dumpfile("demux_tb.vcd");
$dumpvars(0,demux_tb);
$display("testing demux-4:1");
in=1; s0=0; s1=0;
#10;
$display("input=%d, sel=%d %d, output=%b %b %b %b",in,s0,s1,a,b,c,d);
in=1; s0=0; s1=1;
#10;
$display("input=%d, sel=%d %d, output=%b %b %b %b",in,s0,s1,a,b,c,d);
in=1; s0=1; s1=0;
#10;
$display("input=%d, sel=%d %d, output=%b %b %b %b",in,s0,s1,a,b,c,d);
in=1; s0=1; s1=1;
#10;
$display("input=%d, sel=%d %d, output=%b %b %b %b",in,s0,s1,a,b,c,d);
$finish;
end
endmodule
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
**ENCODER(4x2):

module encoder(
input wire d,
input wire c,
input wire b,
input wire a,
output reg x,
output reg y
);
always @(*) begin
 x = 0;
y = 0;
case ({a, b, c, d})
4'b0001: {x, y} = 2'b00;
4'b0010: {x, y} = 2'b01;
4'b0100: {x, y} = 2'b10;
4'b1000: {x, y} = 2'b11;
default: {x, y} = 2'b00;
endcase
end
endmodule

//testbench:
module encoder_tb;
wire x,y;
reg a,b,c,d;
encoder uut(
.a(a),
.b(b),
.c(c),
.d(d),
.x(x),
.y(y)
);
initial begin
$dumpfile("encoder_tb.vcd");
$dumpvars(0,encoder_tb);
$display("testing encoder-4:2");
a=0;b=0;c=0;d=1;
#10;
$display("input=%d %d %d %d ,output= %d %d ",a,b,c,d,x,y);
a=0;b=0;c=1;d=0;
#10;
$display("input=%d %d %d %d ,output= %d %d ",a,b,c,d,x,y);
a=0;b=1;c=0;d=0;
#10;
$display("input=%d %d %d %d ,output= %d %d ",a,b,c,d,x,y);
a=1;b=0;c=0;d=0;
#10;
$display("input=%d %d %d %d ,output= %d %d ",a,b,c,d,x,y);
$finish;
end
endmodule
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
**DECODER:

module decoder(
output reg d,
output reg c,
output reg b,
output reg a,
input wire x,
input wire y
);
always @(*) begin
a = 0;
b = 0;
c = 0;
 d = 0;

case ({x,y})
2'b00: {a,b,c,d} = 4'b0001;
2'b01: {a,b,c,d} = 4'b0010;
2'b10: {a,b,c,d} = 4'b0100;
2'b11: {a,b,c,d} = 4'b1000;
default: {a,b,c,d} = 4'b0000;
endcase
end
endmodule

//testbench:
module decoder_tb;
reg x, y;
wire a, b, c, d;
decoder uut (
.x(x),
.y(y),
.a(a),
.b(b),
.c(c),
.d(d)
);

initial begin
$dumpfile("decoder_tb.vcd");
$dumpvars(0, decoder_tb);
$display("Testing decoder");

// Test cases
x = 0; y = 0;
#10;
$display("input: x=%b, y=%b, output: a=%b, b=%b, c=%b, d=%b", x, y, a, b, c, d);

x = 0; y = 1;
#10;
$display("Input: x=%b, y=%b, Output: a=%b, b=%b, c=%b, d=%b", x, y, a, b, c, d);

x = 1; y = 0;
#10;
$display("Input: x=%b, y=%b, Output: a=%b, b=%b, c=%b, d=%b", x, y, a, b, c, d);

x = 1; y = 1;
#10;
$display("Input: x=%b, y=%b, Output: a=%b, b=%b, c=%b, d=%b", x, y, a, b, c, d);

$finish;
end
endmodule
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
**PRIORITY ENCODER:

module priority_encoder(
input wire d,
input wire c,
input wire b,
input wire a,
output reg x,
 output reg y,
output reg valid
);

always @(*) begin

x = 0;
y = 0;
valid = 0;

if (d) begin
x = 1'b1;
y = 1'b1;
valid = 1'b1;
end
else if (c) begin
x = 1'b1;
y = 1'b0;
valid = 1'b1;
end
else if (b) begin
x = 1'b0;
y = 1'b1;
valid = 1'b1;
end
else if (a) begin
x = 1'b0;
y = 1'b0;
valid = 1'b1;
end
else begin
valid = 1'b0;
end
end
endmodule

//testbench:
module priority_encoder_tb;
wire x,y,valid;
reg a,b,c,d;
priority_encoder uut(
.a(a),
.b(b),
.c(c),
.d(d),
.x(x),
.y(y),
.valid(valid)
);
initial begin
$dumpfile("priority_encoder_tb.vcd");
$dumpvars(0,priority_encoder_tb);
$display("testing priority_encoder-4:2");
a=0;b=0;c=0;d=1;
#10;
$display("input=%d %d %d %d ,output= %d %d ",a,b,c,d,x,y);
a=0;b=0;c=1;d=0;
#10;
$display("input=%d %d %d %d ,output= %d %d ",a,b,c,d,x,y);
a=0;b=1;c=0;d=0;
#10;
 $display("input=%d %d %d %d ,output= %d %d ",a,b,c,d,x,y);
a=1;b=0;c=0;d=0;
#10;
$display("input=%d %d %d %d ,output= %d %d ",a,b,c,d,x,y);
$finish;
end
endmodule
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
**2-bit MAGNITUDE COMPARATOR:

module mag_comparator(
input wire a1,
input wire a0,
input wire b1,
input wire b0,
output reg a_eq_b,
output reg a_lt_b,
output reg a_gt_b
);
always @(*) begin
if ({a1, a0} == {b1, b0}) begin
a_eq_b = 1;
a_lt_b = 0;
a_gt_b = 0;
end
else if ({a1, a0} < {b1, b0}) begin
a_eq_b = 0;
a_lt_b = 1;
a_gt_b = 0;
end
else if ({a1, a0} > {b1, b0}) begin
a_eq_b = 0;
a_lt_b = 0;
a_gt_b = 1;
end
end
endmodule

//testbench:
module mag_comparator_tb;
reg a1,a0,b0,b1;
wire a_eq_b,a_gt_b,a_lt_b;
mag_comparator uut(
.a1(a1),
.a0(a0),
.b1(b1),
.b0(b0),
.a_eq_b(a_eq_b),
.a_gt_b(a_gt_b),
.a_lt_b(a_lt_b)
);
initial begin
$dumpfile("mag_comparator.vcd");
$dumpvars(0,mag_comparator_tb);
$display("testing 2-bit mag_comparator");
a1=0;a0=0;b1=0;b0=0;
#10;
$display("input : %d %d %d %d , output : %d %d %d ",a1,a0,b1,b0,a_eq_b,a_gt_b,a_lt_b);
a1=0;a0=0;b1=0;b0=1;
 #10;
$display("input : %d %d %d %d , output : %d %d %d ",a1,a0,b1,b0,a_eq_b,a_gt_b,a_lt_b);
a1=0;a0=0;b1=1;b0=0;
#10;
$display("input : %d %d %d %d , output : %d %d %d ",a1,a0,b1,b0,a_eq_b,a_gt_b,a_lt_b);
a1=0;a0=0;b1=1;b0=1;
#10;
$display("input : %d %d %d %d , output : %d %d %d ",a1,a0,b1,b0,a_eq_b,a_gt_b,a_lt_b);
a1=1;a0=1;b1=1;b0=1;
#10;
$display("input : %d %d %d %d , output : %d %d %d ",a1,a0,b1,b0,a_eq_b,a_gt_b,a_lt_b);
$finish;
end
endmodule
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
**EVEN PARITY:

module even_parity(
input wire a,
input wire b,
input wire c,
output reg x
);
always @(*) begin
x = a^b^c;
end
endmodule

//testbbench:
module even_parity_tb;
reg a,b,c;
wire x;
even_parity uut(
.a(a),
.b(b),
.c(c),
.x(x)
);
initial begin
$dumpfile("even_parity.vcd");
$dumpvars(0,even_parity_tb);
$display("testing even parity");
a=0;b=0;c=0;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=0;b=0;c=1;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=0;b=1;c=0;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=0;b=1;c=1;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=0;b=0;c=0;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=1;b=0;c=0;
#10;
 $display("input : %d %d %d , output:%d",a,b,c,x);
a=1;b=0;c=1;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=1;b=1;c=0;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=1;b=1;c=1;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
$finish;
end
endmodule
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
**ODD PARITY:

module odd_parity(
input wire a,
input wire b,
input wire c,
output reg x
);
always @(*) begin
x = ~(a^b^c);
end
endmodule

//testbbench:
module odd_parity_tb;
reg a,b,c;
wire x;
odd_parity uut(
.a(a),
.b(b),
.c(c),
.x(x)
);
initial begin
$dumpfile("odd_parity.vcd");
$dumpvars(0,odd_parity_tb);
$display("testing odd parity");
a=0;b=0;c=0;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=0;b=0;c=1;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=0;b=1;c=0;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=0;b=1;c=1;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=0;b=0;c=0;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=1;b=0;c=0;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
 a=1;b=0;c=1;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=1;b=1;c=0;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
a=1;b=1;c=1;
#10;
$display("input : %d %d %d , output:%d",a,b,c,x);
$finish;
end
endmodule
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
**EVEN PARITY CHECKER:

module even_parity_checker_3bit(
input wire [2:0] data_in,
output reg parity_even
);

always @(*) begin

parity_even = data_in[0] ^ data_in[1] ^ data_in[2];
end

endmodule

//testbench:
module even_parity_checker_3bit_tb;

reg [2:0] data_in;

wire parity_even;

// Instantiate the even parity checker module

even_parity_checker_3bit uut (
.data_in(data_in),
.parity_even(parity_even)
);

// Initialize inputs
initial begin
$dumpfile("even_parity_checker_3bit.vcd");
$dumpvars(0, even_parity_checker_3bit_tb);

// Test case 1: Even parity

data_in = 3'b000;
#10;
$display("Input: %b, Parity even: %b", data_in, parity_even);

// Test case 2: Odd parity

data_in = 3'b011;
#10;
$display("Input: %b, Parity even: %b", data_in, parity_even);

// Test case 3: Even parity

data_in = 3'b111;
#10;
$display("Input: %b, Parity even: %b", data_in, parity_even);

// Test case 4: Odd parity

 data_in = 3'b110;
#10;
$display("Input: %b, Parity even: %b", data_in, parity_even);

// End simulation
#10;
$finish;
end

endmodule
----------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------
**ODD PARITY CHECKER:

module odd_parity_checker_3bit(
input wire [2:0] data_in,
output reg parity_odd
);

always @(*) begin

parity_odd = ~(data_in[0] ^ data_in[1] ^ data_in[2]);
end

endmodule

//testbench:
module odd_parity_checker_3bit_tb;

reg [2:0] data_in;

wire parity_odd;

// Instantiate the odd parity checker module

odd_parity_checker_3bit uut (
.data_in(data_in),
.parity_odd(parity_odd)
);

// Initialize inputs
initial begin
$dumpfile("odd_parity_checker_3bit.vcd");
$dumpvars(0, odd_parity_checker_3bit_tb);

// Test case 1: Odd parity

data_in = 3'b000;
#10;
$display("Input: %b, Parity odd: %b", data_in, parity_odd);

// Test case 2: Even parity

data_in = 3'b111;
#10;
$display("Input: %b, Parity odd: %b", data_in, parity_odd);

// Test case 3: Odd parity

data_in = 3'b101;
#10;
$display("Input: %b, Parity odd: %b", data_in, parity_odd);

// Test case 4: Even parity

data_in = 3'b010;
#10;
 $display("Input: %b, Parity odd: %b", data_in, parity_odd);

// End simulation
#10;
$finish;
end

endmodule
-------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
**SHIFT REGISTER:(siso,sipo)--> left to right:

module shift_reg(
input wire d,
input wire clk,
input wire reset,s
output wire so,
output wire[4:0] po
);
reg [4:0] shift_reg; ///5-bit register
always @(posedge clk or posedge reset) begin
if(reset) begin
shift_reg<= 5'b0;
end
else begin
shift_reg <= {d,shift_reg[4:1]};
end
end
assign so = shift_reg[0];
assign po = shift_reg;
endmodule

//testbench:
module shift_reg_tb;
reg d, clk, reset;
wire so;
wire [4:0]po;
shift_reg uut (
.d(d),
.clk(clk),
.reset(reset),
.so(so),
.po(po)
);
always #5 clk = ~clk;
initial begin
clk = 0;
reset = 0;
d = 0;
reset = 1;
#10;
reset = 0;
#10; d = 1;
#10; d = 0;
#10; d = 1;
#10; d = 1;
#10; d = 0;
$finish;
end
initial begin
 $display("Testing of shift_reg");
$monitor("TIME= %d, po= %b, so = %b", $time, po, so);
end
endmodule
OUTPUT:
TIME= 0: parallel output =00000,serial output=0
TIME=25: parallel output =00001,serial output=0
TIME=35: parallel output =00010,serial output=0
TIME= 45: parallel output =00101,serial output=0
TIME=55: parallel output =01011,serial output=0
TIME= 65: parallel output =10110,serial output=1
TIME=75: parallel output =01100,serial output=0
TIME=85: parallel output =11000,serial output=1
TIME= 95: parallel output =10000,serial output=1
TIME=105: parallel output =00000,serial output=0
-----------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------
**UNIVERSAL SHIFT_REG:

module universal_shift_reg(
input wire [1:0] d,
input wire clk,
input wire rst,
input wire sp1, //left shift
input wire sp2, //right shift
input wire [4:0] pp1,//pout
output reg [4:0] out //pout
);

always @(posedge clk or posedge rst) begin

if(rst) begin
out <= 5'b0;
end
else begin
case (d)
2'b00:out<=out;
2'b01:out<={sp2,out[4:1]};
2'b10:out<={out[3:0],sp1};
2'b11:out<=pp1;
default:out<=out;
endcase
end
end
endmodule

//testbench:
module universal_shift_reg_tb;
reg [1:0] d;
reg clk, rst;
reg sp1, sp2;
reg [4:0] pp1;
wire [4:0] out;

// Instantiate the universal_shift_reg module

universal_shift_reg uut (
.d(d),
.clk(clk),
.rst(rst),
.sp1(sp1),
.sp2(sp2),
 .pp1(pp1),
.out(out)
);

// Clock generation: Toggle clk every 5 time units

always #5 clk = ~clk;

// Initial block for stimulus

initial begin
clk = 0;
rst = 0;
d = 2'b00;
sp1 = 0;
sp2 = 0;
pp1 = 5'b0;
rst = 1;
#10;
rst = 0;
pp1 = 5'b10101;
#10;
d = 2'b11;
#10;
d = 2'b00; //stop
d = 2'b01;
sp2 = 1;
#10;
sp2 = 0;
#10;
d = 2'b01;
sp1 = 1;
#10;
sp1 = 0; //stop
#50;
$finish;
end

// Display and monitor the output

initial begin
$monitor("TIME=%d: pp =%b , d=%b", $time, pp1, d);
end
endmodule

OUTPUT:
TIME= 0: pp =00000 , d=00
TIME=10: pp =10101 , d=00
TIME=20: pp =10101 , d=11
TIME=30: pp =10101 , d=01
---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
**COUNTER:

module counter(
input wire en,
input wire clk,
input wire rst,
output reg [3:0] out
);
always @(posedge clk or posedge rst) begin
if(rst) begin
out <=4'b0000;
 end
else if (en) begin
out<=out+1;
end
end
endmodule

//testbench:
module counter_tb;
reg clk,en,rst;
wire [3:0] out;
counter uut(
.en(en),
.clk(clk),
.rst(rst),
.out(out)
);
always #5 clk=~clk;
initial begin
en=0;
clk=0;
rst=0;

rst=1;
#10;
rst=0;

en=1;
#50;
en=0;
#50;

$finish;
end
initial begin
$monitor("time=%d,output=%b",$time,out);
end
endmodule

OUTPUT:
time=0,output=0000
time=15,output=0001
time=21,output=0010
time=27,output=0011
time=33,output=0100
time=39,output=0101
time=45,output=0110
time=51,output=0111
time=57,output=1000
--------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
**RANGE_COUNTER:(2-10):

module range_counter(
input wire en,
input wire clk,
input wire rst,
input wire [3:0] min,
input wire [3:0] max,
output reg [3:0] out
);

always @(posedge clk or posedge rst) begin

if (rst) begin
out <= min;
end
else if (en) begin
if (out == max) begin
out <= min;
end
else begin
out <= out + 1;
end
end
end

endmodule

//testbench:

module range_counter_tb;
reg clk,en,rst;
reg [3:0] min;
reg [3:0] max;
wire [3:0] out;
range_counter uut(
.en(en),
.clk(clk),
.rst(rst),
.out(out),
.min(min),
.max(max)
);
always #3 clk=~clk;
initial begin
en=0;
clk=0;
rst=0;
min=4'b0010; //print 2 to 10
max=4'b1010;

rst=1; //apply reset

#10;
rst=0;

en=0; //apply enable

#100;
en=1;
#50;
en=0;
#50;
$finish;
end
initial begin
$monitor("time=%d,output=%b",$time,out);
end
endmodule

OUTPUT:
time=0,output=0010
time=111,output=0011
time=117,output=0100
time=123,output=0101
time=129,output=0110
time=135,output=0111
time=141,output=1000
time= 147,output=1001
time= 153,output=1010
time= 159,output=0010
---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
**RAM:

`define addr_width 6
`define data_width 32
`define depth 64

module ram (
input wire clk,
input wire rst,
input wire en,
input wire wr_rd,
input wire [`data_width-1:0] data_in,
input wire [`addr_width-1:0] addr,
output reg [`data_width-1:0] data_out,
output reg out_en
);
// Declaration of memory
reg [`data_width-1:0] mem [`depth-1:0];

// Initialize memory with zeros at startup (optional)

integer i;
initial begin
for (i = 0; i < `depth; i = i + 1) begin
mem[i] = 0;
end
end

always @(posedge clk or posedge rst) begin

if (rst) begin
// Reset memory to zero if needed
for (i = 0; i < `depth; i = i + 1) begin
mem[i] <= 0;
end
data_out <= 0;
out_en <= 0;
end else if (en) begin
if (wr_rd) begin
// Write operation
mem[addr] <= data_in;
end else begin
// Read operation
data_out <= mem[addr];
out_en <= 1;
end
end else begin
// Disable output when not enabled
out_en <= 0;
end
end
endmodule

//testbench:

`define addr_width 6
`define data_width 32
`define depth 64

module ram_tb;
reg clk, rst, en, wr_rd;
reg [`data_width-1:0] data_in;
reg [`addr_width-1:0] addr;
wire [`data_width-1:0] data_out;
wire out_en;
reg [`data_width-1:0] temp [`depth-1:0];
reg [`addr_width-1:0] addr_1;
reg [`data_width-1:0] data_out_1;

ram uut (
.clk(clk),
.rst(rst),
.en(en),
.addr(addr),
.wr_rd(wr_rd),
.data_in(data_in),
.data_out(data_out),
.out_en(out_en)
);

initial begin
clk = 0;
forever #5 clk = ~clk;
end

initial begin
en = 1;
rst = 0;
#10;
rst = 1;
#10;
rst = 0;
end

initial begin
#20; // Wait for reset to de-assert
write();
#50;
read();
#50;
comp();
#50;
$finish;
end

task write();
begin
wr_rd = 1;
addr = $random % `depth;
data_in = $random;
addr_1 = addr;
 temp[addr_1] = data_in;
@(posedge clk);
$display("write operation: en = %h, wr_rd = %h, addr = %h, data_in = %h", en, wr_rd, addr, data_in);
end
endtask

task read();
begin
wr_rd = 0;
addr = addr_1;
@(posedge clk);
wait (out_en) begin
data_out_1 = data_out;
end
$display("read operation: en = %h, wr_rd = %h, addr = %h, data_out = %h", en, wr_rd, addr, data_out);
end
endtask

task comp();
begin
if (temp[addr_1] == data_out_1) begin
$display("ram is pass");
$display("temp[%h] = %h, data_out_1 = %h", addr_1, temp[addr_1], data_out_1);
end else begin
$display("ram is fail");
end
end
endtask
endmodule
---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
**SEQ_DETECT:
module seq_detect(
input clk,
input rst,
input in,
output reg out
);
reg [2:0] current_state, next_state;
localparam s0 = 3'b000,
s1 = 3'b001,
s2 = 3'b010,
s3 = 3'b011,
s4 = 3'b110;

// State registers

always @(posedge clk or posedge rst) begin

if(rst) begin
current_state<=s0;
end
else begin
current_state<=next_state;
end
end

// Combinational logic for next state and output

always @(*)begin
next_state = current_state;
out = 0;
 case(current_state)
s0: begin
if(in) next_state = s1;
else next_state = s0;
end
s1: begin
if(in) next_state = s2;
else next_state = s0;
end
s2: begin
if(in) next_state = s3;
else next_state = s0;
end
s3: begin
if(in) next_state = s4;
else next_state = s0;
end
s4: begin
out = 1;
if(in) next_state = s1;
else next_state = s2;
end
endcase
end

endmodule

//testbench:
module seq_detect_tb;
reg clk, rst, in;
wire out;

seq_detect uut (
.clk(clk),
.rst(rst),
.in(in),
.out(out)
);

initial begin
clk = 0;
forever #5 clk = ~clk; // Clock generation
end

initial begin
rst = 1;
in = 0;
#10;
rst = 0;
#10 in = 1;
#10 in = 0;
#10 in = 0;
#10 in = 1;
#10 in = 1;
#10 in = 0;
#10 in = 0;
#10 in = 1;
#10;
$finish;
end
 initial begin
$monitor("time=%0d, reset=%b, input=%b, output=%b, state=%b", $time, rst, in, out, uut.current_state);
end
endmodule