COMPUTER ORGANIZATION (23ISPC205)

Module- 1

Functional units
A computer consists of five functionally independent main parts input, memory, arithmetic
logic unit (ALU), output and control unit.

Input device accepts the coded information as source program i.e. high level language. This
is either stored in the memory or immediately used by the processor to perform the desired
operations. The program stored in the memory determines the processing steps. Basically
the computer converts one source program to an object program. i.e. into machine language.
Finally the results are sent to the outside world through output device. All of these actions
are coordinated by the control unit.

Input unit: The source program/high level language program/coded information/simply data
is fed to a c omputer through input devices keyboard is a most common type. Whenever a
key is pressed, one corresponding word or number is translated into its equivalent binary
code over a cable & fed either to memory or processor. Joysticks, trackballs, mouse, scanners
etc are other input devices.

Memory unit: Its function into store programs and data. It is basically to two types

1. Primary memory

2. Secondary memory
1. Primary memory: - Is the one exclusively associated with the processor and operates at the
electronics speeds programs must be stored in this memory while they are being executed. The
memory contains a large number of semiconductors storage cells. Each capable of storing one bit of
information. These are processed in a group of fixed site called word. To provide easy access to a
word in memory, a distinct address is associated with each word location. Addresses are numbers
that identify memory location. Number of bits in each word is called word length of the computer.
Programs must reside in the memory during execution. Instructions and data can be written into
the memory or read out under the control of processor.

Memory in which any location can be reached in a short and fixed amount of time after specifying
its address is called random-access memory (RAM). The time required to access one word in called
memory access time. Memory which is only readable by the user and contents of which can’t be
altered is called read only memory (ROM) it contains operating system.

Caches are the small fast RAM units, which are coupled with the processor and are aften contained
on the same IC chip to achieve high performance. Although primary storage is essential it tends to
be expensive.

2 Secondary memory: Is used where large amounts of data & programs have to be stored,
particularly information that is accessed infrequently. Examples: - Magnetic disks & tapes, optical
disks (ie CD-ROM’s), floppies etc.,

Arithmetic logic unit (ALU): Most of the computer operators are executed in ALU of the processor
like addition, subtraction, division, multiplication, etc. the operands are brought into the ALU from
memory and stored in high speed storage elements called register. Then according to the
instructions the operation is performed in the required sequence.

The control and the ALU are may times faster than other devices connected to a computer system.
This enables a single processor to control a number of external devices such as key boards, displays,
magnetic and optical disks, sensors and other mechanical controllers.

Output unit: These actually are the counterparts of input unit. Its basic function is to send the
processed results to the outside world. Examples: - Printer, speakers, monitor etc.

Control unit: It effectively is the nerve center that sends signals to other units and senses their
states. The actual timing signals that govern the transfer of data between input unit, processor,
memory and output unit are generated by the control unit.
Q) With neat diagram explain Basic operational concepts clearly indicating Processor
registers and Processor memory interaction.

The following figure shows how memory & the processor can be connected. In addition to the ALU
& the control circuitry, the processor contains a number of registers used for several different
purposes.

Different registers used include:

The instruction register (IR):- Holds the instruction that is currently being executed. Its output
is available for the control circuits which generates the timing signals that control the execution of
instruction.

The program counter PC:- This is another specialized register that keeps track of execution of a
program. It contains the memory address of the next instruction to be executed.

Besides there are n-general purpose registers R0 through Rn-1, among them R0 is also called as
Accumulator used as an operand in arithmetic & Logic operations.

The other two registers which facilitate communication with memory are: -

1. MAR – (Memory Address Register):- It holds the address of the location to be accessed.

2. MDR – (Memory Data Register):- It contains the data to be written into or read out of the
address location.

To perform a given task an appropriate program consisting of a list of instructions is stored in

the memory. Individual instructions are brought from the memory into the processor, and executed
in a sequential manner one after another.

Example: - Consider the instruction Add LOCA, R0

This instruction adds the operand at memory location LOCA, to operand in register R0 & places the
sum into register. This instruction requires the performance of several steps,

1. First the instruction is fetched from the memory into the processor.
2. The operand at LOCA is fetched and added to the contents of R0
3. Finally the resulting sum is stored in the register R0

Operating steps in detail are:

1. Execution of the program starts when the PC is set to the first instruction of the program.
2. Contents of PC are transferred to MAR and a Read Control Signal is sent to the memory.
3. After some time, the word is read out of the memory and loaded into the MDR.
4. Now contents of MDR are transferred to the IR for decoding and execution.
5. If the instruction involves an operation by the ALU, it is necessary to obtain the operands.
6. An operand in the memory is fetched by sending its address to MAR & Initiating a read
cycle.
7. When the operand has been read from memory to MDR, it is transferred from MDR to the
ALU.
8. After one or two cycles, the ALU can perform the desired operation.
9. If the result of this operation is to be stored in the memory, the result is sent to MDR.
10. Address of location where the result is stored is sent to MAR & a write cycle is initiated.
11. The contents of PC are incremented so that PC points to the next instruction to be executed.

Q) Explain the Single Bus structure.

The bus is the simplest and most common way of interconnecting various parts of the computer.
It is a group of lines that serve as a connecting port for several devices. In addition to the lines
that carry the data, the bus must have lines for address and control purpose. The simplest way
to interconnect is to use the single bus as shown below:

INPUT MEMORY PROCESSOR OUTPUT

Since the bus can be used for only one transfer at a time, only two units can actively use the bus
at any given time. Bus control lines are used to arbitrate multiple requests for use of one bus.

Single bus structure has low cost and is very flexible for attaching peripheral devices. Multiple
bus structure certainly increases the performance but also increases the cost significantly.
Q) Derive the basic performance equation. How to improve the performance? Explain

The most important measure of the performance of a computer is how quickly it can execute
programs. The speed with which a computer executes program is affected by the design of its
hardware.

The performance is also affected by the speed of the processor, the disk and the printer. The
time needed to execute an instruction is called the processor time. Just as the elapsed time for the
execution of a program depends on all units in a computer system, the processor time depends on
the hardware involved in the execution of individual machine instructions.

For best performance, it is necessary to design the compiles, the machine instruction set, and
the hardware in a coordinated way.

Let ‘T’ be the processor time required to execute a program that has been prepared in some
high-level language. The compiler generates a machine language program. Assume that complete
execution of the program requires the execution of N machine language instructions.

Suppose that the average number of basic steps needed to execute one machine language
instruction is S, where each basic step is completed in one clock cycle. If clock rate is ‘R’ cycles per
second, the program execution time is given by

NS
T=
R

This is often referred to as the basic performance equation.

The performance of the computer can be improved by

1. Clock Rate: Processor circuits are controlled by a timing signal called clock. The clock
includes the regular time intervals called clock cycles. To execute a machine instruction the
processor divides the action to be performed into a sequence of basic steps that each step can
be completed in one clock cycle. The length P of one clock cycle is an important parameter
that affects the processor performance. Improving the IC technology makes logical circuit
faster, which reduces the time of execution of basic steps. This allows the clock rate R to be
increased, thereby improving the performance of the computer.

2. Cache Memory: The internal speed of performing the basic steps of instruction processing
on chip is very high and is considerably faster than the speed at which the instruction and
data can be fetched from the main memory. A program will be executed faster if the
movement of instructions and data between the main memory and the processor is
minimized, which is achieved by using the cache. Hence by using Cache, we can improve the
performance.

Main Memory Processor

Cache

Memory
Q) What is Performance measurement? Explain overall SPEC rating for computers.

It is very important to be able to access the performance of a computer, designers use

performance estimates to evaluate the effectiveness of new features. The performance of a computer
is given by the execution time T, for the program of interest.

In spite of the performance equation being so simple, the evaluation of ‘T’ is highly complex.
Moreover the parameters like the clock speed and various architectural features are not reliable
indicators of the expected performance.

Hence measurement of computer performance using bench mark programs is done to make
comparisons possible.

A nonprofit organization called SPEC- System Performance Evaluation Corporation

selects and publishes bench marks.

The program selected range from game playing, compiler, and data base applications to
numerically intensive programs in astrophysics and quantum chemistry. In each case, the program
is compiled under test, and the running time on a real computer is measured. The same program is
also compiled and run on one computer selected as reference.

The ‘SPEC’ rating is computed as follows.

Running time on the reference computer

SPEC rating =
Running time on the computer under test

If the SPEC rating = 50 Means that the computer under test is 50 times as fast as the ultra
sparc 10. This is repeated for all the programs in the SPEC suit, and the geometric mean of the
result is computed.

Let SPECi be the rating for program ‘i’ in the suite. The overall SPEC rating for the computer is given
by
1
n n
SPEC rating =   SPECi
 i =1 
Where ‘n’ = number of programs in suite.

The execution time is measured by the SPEC rating is a measure of the combined effect of all
factors affecting performance, including the compiler, the OS, the processor and the memory of the
computer being tested.

Problem:
Q) Explain Memory locations, addresses and encoding of information in a word.

The memory consists of many millions of storage cells, each of which can store a bit of
information having the value 0 or 1. The memory is organized so that a group of n bits can be stored
or retrieved in a single, basic operation. Each group of n bits is referred to as a word of information,
and n is called the word length. The memory of a computer can be schematically represented as a
collection of words as shown in figure

n bits
First word

Second word

Last word

Accessing the memory to store or retrieve a single item of information, a word or a byte,
requires distinct names or addresses for each location. It is customary to use numbers from 0
through 2K-1, for some suitable values of k, as the addresses of successive locations in the memory.
The 2k addresses constitute the address space of the computer.

Modern computers have word lengths that typically range from 16 to 64 bits. If the word length
of a computer is 32 bits, a single word can store a 32-bit 2’s complement number as shown below.

32 bits

b31 b30 ……. b1 b0

Sign bit: b31 = 0 for positive numbers

b31 = 1 for negative numbers

If the word length of a computer is 32 bits, four ASCII characters, each occupying 8 bits can be
stored in it as shown below.

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

Q) Explain Big-endian and Little-endian assignments.
Usually for convenience memory addresses are made Byte addressable. Each memory location
stores a byte. Such computers are called byte addressable computers.
However the word length of the computer may range between 16 to 64 bits. In that case the
larger number has to be divided in to bytes in order to enable it to be stored in the byte addressable
memory.
There are two ways that byte addresses can be assigned across words. They are Big-endian and
Little-endian assignments which are shown below.

Word Address Byte address Word Address Byte address

0 1 2 3 3 2 1 0
0 0

4 4 5 6 7 4 7 6 5 4

….

…. ….

…. ….

….

(a) Big-endian assignment (b) Little-endian assignment

The name big-endian is used when lower byte addresses are used for the more significant bytes
(the leftmost bytes) of the word. The name little-endian is used for the opposite ordering, where the
2k-4 2k-3 2k-2 2k-1
lower byte addresses are used for the less significant bytes (the rightmost bytes) of the word.
2k-1 2k-2 2k-3 2k-4
Example:
Q) Explain different memory related operations.

Both program instructions and data operands are stored in the memory. To execute an
instruction, the processor control circuits must cause the word containing the instruction to be
transferred from the memory to the processor. Operands and results must also be moved between
the memory and the processor. Thus, two basic operations involving the memory are needed,
namely, Load (or Read or Fetch) and Store (or Write).
The load operation transfers a copy of the contents of a specific memory location to the
processor. The memory contents remain unchanged. To start a Load operation, the processor sends
the address of the desired location to the memory and requests that its contents be read. The
memory reads the data stored at that address and sends them to the processor.
The store operation transfers an item of information from the processor to a specific memory
location, destroying the former contents of that location. The processor sends the address of the
desired location to the memory, together with the data to be written into that location.

Q) Brief about Register transfer notation and Assembly language notation.

Register Transfer notation: Generally there will be transfer of information from one part of
the computer system to another. Possible locations that may be involved in such transfers are
memory locations, processor registers, or registers in the I/O subsystem. Most of the time, we
identify a location by a symbolic name standing for its hardware binary address. Example, names
for the addresses of memory locations may be LOC, PLACE, processor registers names may be R0,
R5.
The contents of a location are denoted by placing square brackets around the name of the
location. Thus, the expression R1  [LOC] means that the contents of memory location LOC are
transferred into register R1.
As another example, consider the operation that adds the contents of registers R1 and R2, and
then places their sum into register R3. This action is indicated as R3  [R1] + [R2]

Assembly Language notation: In this, we use an assembly language format. For example, an
instruction that causes the transfer described above, from memory location LOC to processor
register R1, is specified by the statement Move LOC, R1
The contents of LOC are unchanged by the execution of this instruction, but the old contents of
register R1 are overwritten.
The second example of adding two numbers contained in processor registers R1 and R2 and
placing their sum in R3 can be specified by the assembly language statement Add R1, R2, R3
Q) What are the basic assembly instruction types?

The operation of adding two numbers is a fundamental capability in any computer. The
statement C = A + B; in a high-level language program is a command to the computer to add the
current values of the two variables called A and B, and to assign the sum to a third variable, C.

To carry out this action, the contents of memory locations A and B are fetched from the memory and
transferred into the processor where their sum is computed. This result is then sent back to the
memory and stored in location C.

This operation can be performed using different types of instructions.

1. Three-Address instruction: There will be 3 operands.

Add A, B, C ; Operands A and B are called the source operands, C is called the destination

operand, and Add is the operation to be performed on the operands.

A general instruction of this type has the format is

Operation Source1, Source 2, Destination

2. Two-Address instruction: There will be 2 operands

Add B, A ; add operands A and B, result stored in A

Move A, C ; Store the result in C.

A general instruction of this type has the format is

Operation Source, Destination

3. One-Address instruction: There will be 1 operand

Load A ; Load A to accumulator

Add B ; Add B with accumulator

Store C ; Store accumulator content (result) in C.

A general instruction of this type has the format is Operation Source

4. Zero-Address instruction: There will be 0 operands.

ADD ; Add two stack locations.

A general instruction of this type has the format is Operation

 INSTRUCTION EXECUTION & STRAIGHT LINE SEQUENCING
• The program is executed as follows:
1) Initially, the address of the first instruction is loaded into PC (Figure 2.8).
2) Then, the processor control circuits use the information in the PC to fetch
and execute instructions, one at a time, in the order of increasing addresses.
This is called Straight-Line sequencing.
3) During the execution of each instruction, PC is incremented by 4 to point to next
instruction.
• There are 2 phases for Instruction Execution:
1) Fetch Phase: The instruction is fetched from the memory-location and placed in the
IR.
2) Execute Phase: The contents of IR is examined to determine which
operation is to be performed. The specified-operation is then performed by the
processor.

Program Explanation
• Consider the program for adding a list of n numbers (Figure 2.9).
• The Address of the memory-locations containing the n numbers are symbolically given as
NUM1, NUM2…..NUMn.
• Separate Add instruction is used to add each number to the contents of register R0.
• After all the numbers have been added, the result is placed in memory-location SUM.
BRANCHING
• Consider the task of adding a list of „n‟ numbers (Figure 2.10).
• Number of entries in the list „n‟ is stored in memory-location N.
• Register R1 is used as a counter to determine the number of times the loop is executed.
• Content-location N is loaded into register R1 at the beginning of the program.
• The Loop is a straight line sequence of instructions executed as many
times as needed. The loop starts at location LOOP and ends at the
instruction Branch>0.
• During each pass,
→ address of the next list entry is determined and
→ that entry is fetched and added to R0.
• The instruction Decrement R1 reduces the contents of R1 by 1 each time through the loop.
• Then Branch Instruction loads a new value into the program counter. As a result,
the processor fetches and executes the instruction at this new address called the
Branch Target.
• A Conditional Branch Instruction causes a branch only if a specified condition is
satisfied. If the condition is not satisfied, the PC is incremented in the normal way,
and the next instruction in sequential address order is fetched and executed.

CONDITION CODES
• The processor keeps track of information about the results of various operations. This is
accomplished by recording the required information in individual bits, called Condition Code Flags.
• These flags are grouped together in a special processor-register called the condition code register (or
statue register). Four commonly used flags are:
1) N (negative) set to 1 if the result is negative, otherwise cleared to 0.
2) Z (zero) set to 1 if the result is 0; otherwise, cleared to 0.
3) V (overflow) set to 1 if arithmetic overflow occurs; otherwise, cleared to 0.
4) C (carry) set to 1 if a carry-out results from the operation; otherwise cleared to 0.
Q) Explain different Addressing Modes with examples.

Various schemes for specifying addresses of operands in an instruction have been introduced.
Such schemes are collectively known as Addressing Modes. The addressing mode specifies a rule or
method for interpreting or modifying the address field of the instruction before the operand is
actually accessed for manipulation. Different addressing modes include: Immediate mode, Register
mode, Absolute (Direct) mode, Indirect mode, Indexed mode, Relative mode, Auto increment mode
and Auto decrement mode.

➢ Immediate mode: Here the operand is specified in the instruction itself. An instruction that
follows immediate mode has an operand field rather than an address field.
A common convention, sharp symbol # has to precede the value of an immediate operand
Ex: Move #50, R0 ; R0=50 (Immediate number 50 is loaded into register R0)

➢ Register mode: In this scheme, name of the register (code of a general purpose register)
appears in the address field of an instruction. In this mode both operands are in the CPU
general purpose registers.
Ex: Move R2, R0 ; R2→R0 (Move content of register R2 into register R0)

➢ Absolute or Direct Mode: Here operand resides in Memory and its address is given explicitly
in the address field of an instruction.

Ex: Move LOC, R0 ; LOC→ R0 (content of memory location LOC is loaded into R0)
This scheme needs only one memory reference and no further calculation is required.

➢ Indirect Mode: The effective address of the operand is the content of a register called indirect
register or pointer which appears in the instruction.
Ex: Move (R1), R0 ; (R1)→ R0 (content of memory whose address is in R1 is loaded into R0)
The use of parenthesis indicates a memory reference.

➢ Indexed Mode: In this mode, effective address of the operand is generated by adding a
constant value to the contents of indirect register. This constant value is called offset value or
displacement. Indexed addressing mode is symbolically represented as X(R). Here X denotes a
constant and R is name of the indirect register.
Effective address EA of the operand is given as EA = X + [R]
Ex: Move 1040(R1), R0 ; (R1+1040)→ R0
A = 1040 = X; constant X corresponds to a memory location (R) = 20 i.e. Index or offset value
EA = A + (R) = 1040 + 20 = 1060 at which you will find desired operand 50.
➢ Relative Mode: This scheme supplies the relative position of the memory operand to be
located.
It’s like indexed mode only but program counter register PC substitutes for indirect register.
Relative Mode specify Effective Address by a notation: X (PC)
Effective address is EA = [PC] + X
Ex: Branch > 0 loop ; here jump value / displacement ± X

➢ Auto increment Mode: Here contents of indirect register specified in the instruction are
incremented to denote effective address of next operand in successive memory location.
After accessing the operand, the contents of this register are incremented automatically to point
to the next operand. Use of Auto Increment mode instruction eliminates the use of explicit
increment instruction.
Notation for Auto Increment Mode: (Ri) +
Ex: Move (R2) +, R0 ; (R2)→ R0 and R2=R2+1

➢ Auto decrement Mode: Here contents of indirect register specified in the instruction are
decremented to denote effective address of next operand in successive memory location.
Before accessing the operand, the contents of this register are decremented automatically to
point to the next operand. Use of Auto decrement mode instruction eliminates the use of explicit
decrement instruction.
Notation for Auto Increment Mode: - (Ri)
Ex: Move -(R2) , R0 ; R2=R2-1 and (R2)→ R0

Q) Brief about Assembly Language and Assembler directives.

Usually, symbolic codes are used to represent machine instructions. These symbolic codes are called
as mnemonics. Mnemonics are abbreviations that represent operation code of an instruction in a
compact and meaningful symbolic form. For example MOVE is used to Move the data, ADD is used
to perform addition. A complete set of mnemonics, symbolic names for register & memory locations
and a list of rules for their use form a programming language called an Assembly Language. The
set of rules for using the mnemonics in the specification of complete instructions and programs is
called the Syntax of the language. Programs written in an assembly language can be
automatically translated into a sequence of machine instructions by a program called an
Assembler. The user program in its original alphanumeric text formal is called a Source
Program, and the assembled machine language program is called an Object Program. The
assembly language syntax suggests that a move instruction to appear as follows: MOVE R0, SUM
➢ The opcode mnemonic MOVE is followed by at least one blank space.
➢ The source operand is in register R0 (register operand).
 ➢ The destination operand is in the memory location SUM

Assembler Directives are the assembler commands to the assembler concerning the program
being assembled. These commands are neither translated into machine opcode nor assigned any
memory location in the object program.

Thus, an assembly language program is said to be a complete one and acceptable to an

assembler for translation and for further assignment of memory locations – if it is associated with
necessary assembler directives. Consider the following Assembly Language program.

• EQU informs the assembler about the value of an identifier.

Ex: SUM EQU 200; I n f o r m s assembler the name SUM should be replaced by value 200.
• ORIGIN tells the assembler the starting-address of memory-area to place the data block.
Ex: ORIGIN 204; Instructs assembler to initiate data-block at memory- starting from 204.
• DATAWORD directive tells the assembler to load a value into the location.
Ex: N DATAWORD 100; Informs the assembler to load data 100 into the memory-location N
• RESERVE directive is used to reserve a block of memory.
Ex: NUM1 RESERVE 400 ; declares a memory-block of 400 bytes is to be reserved for data.

• END directive tells the assembler that this is the end of the source-program text.
• RETURN directive identifies the point at which execution of the program should be
terminated.
• Any statement that makes instructions or data being placed in a memory-location may be
given a label. The label (say N or NUM1) is assigned a value equal to the address of that
location.
Q) Apply indirection and pointers for adding a list of numbers.
Indirect Mode
• The EA of the operand is the contents of a register(or memory-location).
• The register (or memory-location) that contains the address of an operand is called a Pointer.
• We denote the indirection by
→ name of the register or
→ new address given in the instruction.
E.g: Add (R1),R0 ;The operand is in memory. Register R1 gives the effective-
address (B) of the operand.

• To execute the Add instruction in fig 2.11 (a), the processor uses the value
which is in register R1, as the EA of the operand.
• It requests a read operation from the memory to read the contents of location
B. The value read is the desired operand, which the processor adds to the contents
of register R0.
• Indirect addressing through a memory-location is also possible as shown in fig
2.11(b). In this case, the processor first reads the contents of memory-location A,

then requests a second read operation using the value B as an address to obtain the
operand.
Program Explanation
In above program, Register R2 is used as a pointer to the numbers in the list, and
the operands are accessed indirectly through R2.
The initialization-section of the program loads the counter-value n from memory-
location N into R1 and uses the immediate addressing-mode to place the address
value NUM1, which is the address of the first number in the list, into R2. Then it
clears R0 to 0.
The first two instructions in the loop implement the unspecified instruction block starting at
LOOP. The first time through the loop, the instruction Add (R2), R0 fetches the operand at
location NUM1 and adds it to R0. The second Add instruction adds 4 to the contents of the
pointer R2, so that it will contain the address value NUM2 when the above instruction is
executed in the second pass through the loop.
Q) Illustrate indexing with the help of a example program.

Indexed mode
• The operation is indicated as X(Ri)
where X=the constant value which defines an offset(also called a displacement).
Ri=the name of the index register which contains address of a new location.
• The effective-address of the operand is given by EA=X+[Ri]
• The contents of the index-register are not changed in the process of generating the effective-
address.
• The constant X may be given either
→ as an explicit number or
→ as a symbolic-name representing a numerical value.

• Fig(a) illustrates two ways of using the Index mode. In fig(a), the index register, R1, contains the
address of a memory-location, and the value X defines an offset(also called a displacement) from this
address to the location where the operand is found.
• To find EA of operand: Eg: Add 20(R1), R2
EA=>1000+20=1020
• An alternative use is illustrated in fig(b). Here, the constant X corresponds to a memory address, and
the contents of the index register define the offset to the operand. In either case, the effective-address is the
sum of two values; one is given explicitly in the instruction, and the other is stored in a register.
Q) Differentiate between RISC and CISC processors

We have two different architectures of processors called RISC and CISC.

CISC: A computer or a processor with a large number of instructions and incorporating variable –
length instruction formats (i.e. using multiple words for instructions) is termed a Complex
Instruction Set Computer abbreviated as CISC

Salient feature of CISC architecture include:

➢ Support large number of instructions – 100 to 250

➢ Support wide variety of addressing modes – 5 to 20
➢ Comprises variable length instructions
➢ Provide instructions for direct manipulation of operands residing in memory
➢ Examples of CISC processors are Intel 8086, 80386, 80486, Pentium processors.

RISC:A computer or processor with relatively small set of instruction and incorporating fixed –
length instruction format most of them being a register – to –register operations, is termed as
Reduced Instructions Set Computer abbreviated as RISC.

Salient feature of RISC architecture include:

➢ Support relatively few instructions and are less complex

➢ Support few addressing modes
➢ Comprises fixed length instructions that can be easily decoded
➢ A restriction to perform all operations in processor registers
➢ Ability to execute one instruction per clock cycle
✓ Examples of RISC processors are Power PC 601, 603, 604, 620

RISC CISC
Simple instructions taking one cycle. Complex instructions taking multiple cycle.
Instructions are executed by hardwired control Instructions are executed by
unit. microprogrammed control unit.
Few instructions. Many instructions.
Fixed format instructions. Variable format instructions.
Few addressing modes, and most instructions Many addressing modes.
have register to register addressing mode.
Multiple register set. Single register set.
Highly pipelined. No pipelined or less pipelined.
Review Questions

1. Explain with neat diagram the typical operating steps involved in execution of an
instruction.
2. Derive the basic performance equation. Explain the methods to improve the
performance.
3. Develop an assembly code segment using three address instruction and two address
instruction formats to perform C = A + B
4. What is a byte addressable computer? Illustrate Big-endian and Little-endian
schemes with an example.
5. Build a straight line sequencing to implement the task C [A] + [B].
6. Illustrate the usage of branching to perform addition of N numbers.
7. Explain any 4 addressing modes with example.
8. Apply indirection and pointers for adding a list of numbers.
9. Given a list of n students records containing student ID located at memory address
LIST followed by 3 test scores. Apply indexing and arrays to add students scored in
test1, test2, test3 in the location SUM1, SUM2 and SUM3 respectively. Assume word
length to be 32 Bits.
10. Explain any 5 assembler directives with example.
11. List and explain difference between RISC and CISC