Experiment No 1

Vanshika Jagdale
UEC2023128
A2

Exp- Introduction to Vivado Software & Boolean Boards FPGA Spartan-7 Kits

[Link] a Design Flow of Vivado Software starting from designing to implementation Ans-
Step 1: Launch Vivado

● Open Vivado Design Suite on your computer.

Step 2: Create a New Project

1. Click on Create New Project.

2. Enter Project Name: AND_Gate.
3. Select a suitable Project Location (directory).
4. Check Create project subdirectory.
5. Click Next.

Step 3: Select Project Type

● Choose RTL Project (Register Transfer Level). ●

Click Next.

Step 4: Select Default Part or Board

1. In the Parts tab, search for the FPGA part number:

○ Part: xc7s50csga324-1 (for Spartan-7 board).
2. Select the part and click Next, then Finish.

Step 5: Add Verilog Source and Constraints

(a) Add Design Sources

● Right-click on Design Sources → Add Sources.

● Choose Add or Create Design Sources.
● Create a new Verilog file named and_gate.v and write the AND gate code.

(b) Add Simulation Sources

● Right-click on Simulation Sources → Add Sources.

● Create a new Verilog testbench file named tb_and.v for simulation.
Step 6: Write Verilog Code
 ● Write the Verilog code for the AND gate and its testbench.

Step 7: Simulate the Design

1. Go to Flow Navigator → Simulation → Run Simulation → Run Behavioral Simulation.

2. Observe the waveform for signals a, b, and y.
3. Verify that the simulation output matches the truth table of the AND gate.

Step 8: Synthesize the Design

1. Go to Flow Navigator → Synthesis → Run Synthesis.

2. Click Run.
3. After completion, click Open Synthesized Design to analyze the synthesized circuit.

Step 9: Assign I/O Ports (I/O Planning)

1. In the Flow Navigator, under Open Synthesized Design, click I/O Planning.
2. The I/O Ports window will show the ports (a, b, y).
3. Assign FPGA pins according to the Boolean Board’s .xdc file:
○ a → K1
○ b → K2
○ y → A1 (LED output)
4. Set IOSTANDARD = LVCMOS33 for all ports.
5. Save the constraints file as and_gate_constraints.xdc.
6. This constraints file will be used during implementation.

Step 10: Implement the Design

1. Go to Flow Navigator → Implementation → Run Implementation.

2. Click Run.
3. After completion, click Open Implemented Design to review the layout.

Step 11: Generate Bitstream

1. In Flow Navigator, click Generate Bitstream.

2. Wait until the bitstream generation completes.
3. When prompted, click Open Hardware Manager.

Step 12: Program the Device

1. Connect your Boolean Board (FPGA) via USB cable.

2. In Hardware Manager:
○ Click Open Target → Auto Connect.
 Experiment No 2
Vanshika Jagdale
UEC2023128
A4

Aim: To design and simulate 8:1 Multiplexer using Vivado Software and implement it on
Digital

Boolean Board (Spartan-7 FPGA Kit)

1. Write a Verilog code for 8:1 mux using structural style of modeling.
CODE FOR 2:1 MUX module
mux2 (
input a, b,
input s,

output y
);
assign y = (s) ? b : a;
endmodule

CODE FOR 8:1 MUX

module mux8( input D[7:0], input S[2:0], output Y);
wire y0, y1, y2, y3, y4, y5; mux2 m0(D[0],
D[1], S[0], y0); mux2 m1(D[2], D[3], S[0],
y1); mux2 m2(D[4], D[5], S[0], y2); mux2
m3(D[6], D[7], S[0], y3);

mux2 m4(y0, y1, S[1], y4);

mux2 m5(y2, y3, S[1], y5);
mux2 m6(y4, y5, S[2], Y);
endmodule

[Link] both the behaviour and structural modelling styles of designing.

 Experiment No 3
Vanshika Jagdale
UEC2023128
A4

Aim: To design and simulate 4 Bit up down counter using Vivado Software
and implement it on Digital Boolean Board (Spartan-7 FPGA Kit)

1. Differentiate between synchronous and asynchronous counters and comment

on which type of counter is used in your coding.

2. Draw the circuit diagram of 4bit up-down synchronous counter using flip-flop
and explain it.
4 Bit UP-DOWN counter using JK FF
● Four JK flip-flops (FF0, FF1, FF2, FF3) are connected in series.
● Clock input is common to all flip-flops (synchronous).
● Up/Down control line decides the counting direction:
o In Up mode: Flip-flop toggling depends on previous outputs (Q).
o In Down mode: Flip-flop toggling depends on inverted outputs (~Q).

Working go the 4-bit UD counter:

1. Reset clears all flip-flops (counter = 0000).
2. Up counting (UD=1): Counter increases from 0000 → 1111 (0 to 15).
3. Down counting (UD=0): Counter decreases from 1111 → 0000 (15 to
0). Since all flip-flops are driven by the same clock, the counter is synchronous.
Experiment No 4
Bhagyashri Deshmukh UEC2023116 A1

Aim: To design and simulate FIFO buffer using Vivado Software and implement it on
Digital Boolean Board (Spartan-7 FPGA Kit)

1. Explain the need/application of FIFO memory or buffer

FIFO memory is commonly used for temporary data storage and synchronization between
systems operating at different speeds. It preserves the order of data by ensuring that
information is read in the same sequence it was written, thereby preventing data loss or
corruption. Typical applications include buffering in communication systems, network
routers, UARTs, audio/video streaming, and inter-process communication in processors.

2. Circular queue is preferred over a linear queue to implement FIFO buffer, Justify
A circular queue is preferred as it makes efficient use of memory by wrapping around to the
beginning when the end of the queue is reached. In contrast, a linear queue prevents insertion
once the rear reaches the end, even if space is available at the front due to deletions. By
reusing these freed-up locations, a circular queue overcomes this limitation, making it highly
suitable for FIFO buffer implementation in hardware.
 Experiment No 5
Vanshika Jagdale
UEC2023128
A4

Aim: To design CMOS Inverter using 120nm technology. Comment on equal rise and fall
time.

1. Justify the difference between Rise Time & fall Time in the output of inverter. How to
make it equal.
Ans - Rise Time (tr): Time taken for output voltage to rise from low to high (e.g., 10% to 90% of
final value).
Fall Time (tf): Time taken for output voltage to fall from high to low (e.g., 90% to 10% of final
value).
Difference arises due to:
● Asymmetry in transistor switching characteristics (PMOS vs NMOS strength).
● Different load capacitances during charging (rise) and discharging (fall).
● Unequal mobility of carriers (electrons vs holes).
To make rise and fall times equal:
● Adjust transistor sizing (width-to-length ratio) to balance PMOS and NMOS drive strengths.

2. Effect of capacitor on the power dissipation .

Ans - Capacitor increases power dissipation during switching because it charges and
discharges each cycle.
● Dynamic power dissipation is proportional to C·V²·f(where C = capacitance, V = voltage, f =
frequency).
● Larger capacitance → more charge/discharge → higher dynamic power loss.
● Static power dissipation remains unaffected by capacitor.
● High capacitance slows down circuit speed due to longer charging/discharging times.
● Minimizing capacitance helps reduce overall power consumption.

3. Why NAND gate is preferred over NOR gate for designing.

Ans - NAND gates are preferred over NOR gates because they generally switch faster and
consume less power. This is mainly due to the use of NMOS transistors in the pull-down
network of NAND gates, which have higher electron mobility compared to the PMOS transistors
dominating the pull-up network of NOR gates. Additionally, NAND gates require fewer or smaller
transistors, making them more area- and power-efficient. For these reasons, NAND gates are
more commonly used in digital circuit design.
4. Draw 2D cross section of P-MOS, N-MOS, & CMOS .
5. Draw V-TC & explain different operation regions.

V-TC (Voltage Transfer Characteristics) of a CMOS inverter is the plot of output voltage (V_out)
vs input voltage (V_in). The regions of operation: Cut-off region: When input voltage is low,
NMOS is off and PMOS is on, output is high (logic 1). Linear/Transition region: Both NMOS and
PMOS conduct partially, the output voltage transitions from high to low. Saturation region: When
input voltage is high, NMOS is on and PMOS is off, output is low (logic 0).

6. Why P-MOS is connected in Pull-Up network & N-MOS is connected in Pull-Down

network.
Ans - PMOS transistors are connected in the pull-up network because they can efficiently pass
a strong high voltage (logic ‘1’) from the supply to the output. When the gate of a PMOS is low, it
turns on and connects the output to the positive supply voltage (VDD), pulling the output up.
NMOS transistors, on the other hand, are used in the pull-down network because they conduct
well when their gate is high and can pull the output down to ground (logic ‘0’) effectively. NMOS
devices have higher electron mobility, making them better at sinking current and providing a
strong low output. This complementary arrangement (PMOS for pull-up and NMOS for pull-
down) forms the basis of CMOS technology, offering low power consumption and efficient
switching
 Experiment No 6
Vanshika Jagdale
UEC2023128
A4

Aim: Design of Boolean equation using CMOS Logic.

1. Justify that Implementation of Inverted logic is easy in CMOS.

Ans= In CMOS technology, every logic gate is naturally implemented along with its inverted form
because of the complementary action of NMOS and PMOS transistors. NMOS passes logic 0
efficiently, while PMOS passes logic 1 efficiently. When we design pull-down networks (using
NMOS), the dual pull-up network (using PMOS) automatically produces the inverted logic. For
example, a CMOS inverter uses only two transistors (one NMOS and one PMOS) and gives
high noise margin, low static power, and full voltage swing. Thus, CMOS inherently supports
inversion, making inverted logic expressions simpler and more efficient to realize compared to
direct logic forms.

2. What are the design rules to implement the Boolean Expression.

Ans= When implementing Boolean functions using CMOS logic, the following design rules are
followed:
Complementary Rule: For every NMOS network, a complementary PMOS network must exist
(dual structure).
Pull-Down Network (PDN): Implement the logic function that pulls the output to ground using
NMOS [Link] → NMOS in series, OR → NMOS in parallel
Pull-Up Network (PUN): Implement the exact dual of the PDN using PMOS transistors. AND in
NMOS ↔ OR in PMOS, OR in NMOS ↔ AND in PMOS
Inputs Driven Directly: Each input must drive both NMOS and PMOS gates directly (no need of
inversion unless required by function).
One Output Node: Both PDN and PUN are connected to a common output node, ensuring that
only one conducts at a time.
No Short Path: At no condition should both networks create a direct path between VDD and
GND (avoids short-circuit current).
Transistor Sizing: PMOS devices are usually made wider than NMOS (Wp ≈ 2–2.5 Wn) to
balance delays.

3. Explain different layout design rules.

Ans= Transistor: minimum width/length, proper contacts.
Diffusion: minimum area, spacing, contact enclosure.
Poly: min width/spacing, overlap with active.
Contact/Via: min size, proper overlap. Metal: min width/spacing, density limits.
Well: min width, spacing, enclosure
 Experiment No 7
Vanshika Jagdale
UEC2023128
A4

Assignment Questions :

1. different approaches to construct 2:1 MUX in the selected CMOS technology & calculate
the no. of transistors required
.
Ans:
Conventional Logic Gates: Based on the Boolean equation Y = (A ⋅ S') + (B ⋅ S).
This is the largest, requiring 20 transistors.
Pass-Transistor Logic: Uses single NMOS transistors as switches. It's the smallest with
only
4 transistors but suffers from signal degradation (it passes a "weak 1").

Transmission Gate Logic: Uses NMOS/PMOS pairs as switches. This is the best method,
requiring only 6 transistors while providing a full-swing output without any signal
degradation.

2. Differentiate between PASS Transistor Logic & Transmission Gate.

3. Explain Transmission Gate & Its advantages over CMOS Inverter as a switch.

Ans: A Transmission Gate is a true bidirectional switch that passes a signal through without
changing it. A CMOS Inverter is a unidirectional logic gate that always inverts the
[Link], a Transmission Gate is a superior switch because its purpose is to simply
pass a signal, while an inverter's purpose is to fundamentally alter it.
4. Write the applications of transmission gates.
Ans: Their main application is building compact and fast Multiplexers (MUX). They are also
essential for creating memory elements like latches and flip-flops. As perfect switches, they are
ideal for routing analog signals without distortion. Furthermore, they enable the design of very
small logic gates like XOR/XNOR. Their ability to pass strong signals without degradation
makes them superior.
This versatility is crucial for creating modern, low-power digital circuits.
 Experiment No 8
Vanshika Jagdale
UEC2023128
A4

Assignment questions :
1. Justify that Implementation of Inverted logic is easy in CMOS.

Ans: Inverted logic is easier in CMOS because the fundamental structure of a CMOS gate
is naturally inverting. The most direct way to build a gate is with a pull-down network that
inherently inverts the logic function. This makes inverting gates like NAND and NOR very
compact (e.g., 4 transistors). To create non-inverting gates like AND or OR, you must first
build the inverting gate and then add an extra inverter, making them larger (6 transistors),
slower, and less efficient.

2. What are the design rules to implement the Boolean Expression.

To implement a Boolean expression in CMOS, you design two complementary transistor

networks:
1. Pull-Down Network (NMOS): Create this network to connect the output to Ground.
○ AND logic is built with series NMOS transistors.
○ OR logic is built with parallel NMOS transistors.
2. Pull-Up Network (PMOS): Create this network to connect the output to VDD by building
the dual of the pull-down network.
○ Series NMOS connections become parallel PMOS connections.
○ Parallel NMOS connections become series PMOS connections.

3. Explain different layout design rules.

Ans: Layout design rules are the geometric "building code" for manufacturing
integrated circuits, defining the minimum dimensions and spacing to ensure chips work
reliably and can be produced with a high yield.
There are two main types:
● Lambda (λ)-Based Rules: A scalable approach using a single parameter (λ). It's
simple and portable, making it ideal for academic and learning purposes.
● Micron (μm)-Based Rules: An absolute approach using fixed dimensions. It's
highly optimized for maximum density and is the standard for all commercial and industrial
 Experiment No 9
Vanshika Jagdale
UEC2023128
A4

Aim: Design of CMOS single bit SRAM cell layout and verify the
functionality by simulation Assignment Questions :

1. Distinguish between Static RAM & Dynamic RAM

Static RAM (SRAM): SRAM uses flip-flops made of transistors to store each bit. It retains data
as long as power is supplied without needing refresh cycles. SRAM is faster, more reliable, and
more expensive due to its complex transistor structure. It consumes less power in idle mode.

Dynamic RAM (DRAM): DRAM stores each bit as a charge in a capacitor, which leaks over
time. Therefore, DRAM requires periodic refresh cycles to maintain the stored data.
It has a simpler design and higher density, making it cheaper but slower than SRAM.
DRAM consumes more power because of refresh operations.

2. Which RAM is faster & why Static RAM or Dynamic RAM ?

Static RAM is faster than Dynamic RAM because SRAM stores data using flip-flop circuits
made from transistors, allowing for quick access without needing refresh cycles. In contrast,
DRAM stores data as charge in capacitors, which leak over time and require frequent refreshing,
introducing delays and reducing speed. Therefore, SRAM’s stable storage mechanism enables
quicker read and write times, making it suitable for cache memory and high-speed applications.