BITS ESZG512 :

Embedded System
Design
BITS Pilani Jagadeesha P
WILP Division, BITS-Pilani
Pilani Campus
 BITS Pilani
Pilani Campus

ESZG512/MELZG526/SEZG516
L-2: Embedded System Design
Note: Students are requested to NOT to rely on PPTs/Recorded sessions as their only source of knowledge, explore sources
within your own organization or web for any specific topic; attend classes regularly and involve in discussions;
PLEASE DO NOT PRINT PPTs, Save the Environment!

Source PPT Courtesy: Some of the contents of this PPT is sourced from Presentations by Prof. Manoj S Kakade, BITS-Pilani
 BITS Pilani
Pilani Campus

Break : 9.30 – 9.35 am (5 Minutes)

Processor Architectures
➢ Based on number of memory and data buses used there are 3
types of architectures for the processor.

1. Von Neumann Architecture

2. Harvard Architecture
3. Super-Harvard Architecture

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 Von Neumann Architecture (Princeton)
• The von Neumann architecture—also known as the von Neumann
model or Princeton architecture.
• Program and data memory share the same address and data buses and
are hence both within the same memory map.
• One memory chip which stores both instruction and data.
• Processor interact with memory through address and data buses to
fetch instructions and data.
• Single memory address for either program code or data, but not for
both.
• No separation between data and program memory. Program and data
fetches are done using time division multiplexing which affect the
performance.
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Von Neumann Architecture (Princeton)

• Time sharing the data bus

Address Bus between both the instruction
and data means that
INSTRUCTION maximum speed of executing
CPU & a program will always be
Data Bus DATA MEMORY
limited, as each has to use the
bus in turn.
“Von Neumann Bottleneck”

Example :
1. Motorola 68HC11 Microcontroller
2. 8085 Microprocessor

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Harvard Architecture
• Use two separate memories for program and data with their
independent address and data buses.
• Because of two different streams of data and program, there is
no need to have any time division multiplexing of address and
data buses.
• This architecture is much more efficient because accessing of
data and instruction simultaneously, so very fast.
• Uses same address in different memories for code and data.
• Common in embedded systems and real-time applications where
performance is critical.

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Harvard Architecture
Program Memory Data Memory Address
Address Bus
Bus

PROGRAM
CPU DATA MEMORY
MEMORY Program Memory Data
Data Memory Data

Bus Bus

Example :
1. MCS 51 family of microcontrollers by Intel
2. PIC microcontrollers by Microchip
3. Digital signal processor

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Super Harvard Architecture
• Cache used to store instructions, leaving both instruction bus
and data bus free to fetch operands.
• Harvard Architecture + cache = Extended Harvard Architecture
or Super Harvard Architecture.
• In Harvard data memory is accessed more frequently than
program memory. Provision has to made to store some
secondary data in program memory to balance the load on both
memory blocks.
• This architecture is proposed by Analog Devices, used
extensively in Digital Signal Processors.

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Super Harvard Architecture
Program Memory Data Memory Address
Address Bus
Bus

Program Memory
(Instruction & CPU Data Memory Data
Data Memory
Secondary Data) Program Memory
Data Bus Bus
Inst.
cache

Example :
1. SHARC DSP,
Tiger SHARC

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Super Harvard Architecture
Harvard Architecture Von-Neumann Architecture

Separate buses for Instruction and Data fetching Single shared bus for Instruction and Data fetching

Easier to Pipeline, so high performance can be Low performance Compared to Harvard

achieved Architecture

Comparatively high cost Cheaper

No memory alignment problems Allows self modifying codes

Since data memory and program memory are Since data memory and program memory
stored physically in different locations, no chances are stored physically in same chip,
for accidental corruption of program memory chances for accidental corruption of program
memory

Limited power saving options Lot of power saving features

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CISC and RISC Architectures
➢ Comple Instruction Set Computer
• Large number of complex instructions.
• Low level.
• Facilitate the extensive manipulation of low level computational
elements and events such as memory, binary arithmetic and
addressing.
➢ Examples of CISC processors are the
• System/360 (excluding the 'scientific' Model 44),
• VAX,
• PDP-11,
• Motorola 68000 family,
• Intel x86 architecture-based processors.

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 CISC and RISC Architectures
➢ Pro’s
• Emphasis on hardware.
• Includes multi-clock complex instructions.
• Memory to memory: "LOAD" and "STORE" incorporated in instructions.
• Small code sizes, high cycles per second.
• Transistors used for storing complex instructions.
➢ Cons’s
• The incorporation of older instruction sets into new generations of
processors tended to force growing complexity.
• Many specialized CISC instructions were not used frequently enough to justify
their existence.
• Because each CISC command must be translated by the processor into tens or
even hundreds of lines of microcode, it tends to run slower than an equivalent
series of simpler commands that do not require so much translation.
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 RISC Architectures
➢ Reduced Instruction Set Computer
• Small number of instructions.
• Instruction size constant.
• Bans the indirect addressing mode.
• Retains only those instructions that can be overlapped and made to
execute in one machine cycle or less.
➢ Examples of RISC processors are the
• Apple iPods (custom ARM7TDMI SoC) and iPhone (Samsung ARM1176JZF),
• Palm and PocketPC PDAs and smartphones (Intel XScale family,
Samsung SC32442-ARM9),
• Nintendo Game Boy Advance (ARM7),
• Nintendo DS (ARM7, ARM9),
• Sony Network Walkman (Sony in-house ARM based chip)

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 RISC Architectures
➢ Pro’s
• Emphasis on software.
• Single-clock, reduced instruction only.
• Register to Register: "LOAD" and "STORE" are independent instructions.
• Large code sizes, low cycles per second.
• Spends more transistors on memory registers.

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 CISC and RISC Architectures
➢ Performance
• The CISC approach attempts to minimize the number of
instructions per program, sacrificing the number of cycles per
instruction.
• RISC does the opposite, reducing the cycles per instruction at
the cost of the number of instructions per program.

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 RISC V/s CISC Processors/Controllers
RISC CISC

Lesser no. of instructions Greater no. of Instructions

Instruction Pipelining and increased execution speed Generally, no instruction pipelining feature
Orthogonal Instruction Set (Allows each Non-Orthogonal Instruction Set (All instructions are not
instruction to operate on any register and use any addressing allowed to operate on any register and use any addressing
mode) mode. It is instruction specific)
Operations are performed on registers only, Operations are performed on registers or memory
the only memory operations are load and store depending on the instruction
Large number of registers are available Limited number of general-purpose registers
Programmer needs to write more code to execute a task Instructions are like macros in C language. A
since the instructions are simpler ones programmer can achieve the desired functionality with a
single instruction which in turn provides the effect of using
more simpler single instructions in RISC
Single, Fixed length Instructions Variable length Instructions
Less Silicon usage and pin count More silicon usage since more additional decoder
logic is required to implement the complex instruction
decoding
With Harvard Architecture Can be Harvard or Von-Neumann Architecture

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 Big-Endian V/S Little-Endian Processors
➢ Endianness specifies the order in which the data is stored in the memory by
processor operations in a multi-byte system (Processors whose word size is
greater than one byte)
➢ Suppose the word length is two byte then data can be stored in memory in
two different ways
• Higher-order of data byte at the higher memory and lower-order of data byte at
location just below the higher memory.
• Lower-order of data byte at the higher memory and higher-order of data byte at
location just below the higher memory.
➢ Little-Endian means the lower-order byte of the data is stored in memory at
the lowest address, and the higher-order byte at the highest address. (The little
end comes first)
➢ Big-Endian means the higher-order byte of the data is stored in memory at
the lowest address, and the lower-order byte at the highest address. (The big
end comes first)
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 Big-Endian V/S Little-Endian Processors
Address: 00 01 02 03 Base Address + 0 Byte 0 Byte 0 0x20000 (Base Address + 0)

Data: 78 56 34 12 Base Address + 1 Byte 1 Byte 1 0x20001 (Base Address + 1)

Base Address + 2 Byte 2 Byte 2 0x20002 (Base Address + 2)

Base Address + 3 Byte 3 Byte 3 0x20003 (Base Address + 3)

Little-Endian Operation

Example: For the hexadecimal number 0x12345678, it is stored as 78 56 34 12 in

memory. Base Address + 0 Byte 3 Byte 3 0x20000 (Base Address + 0)
Address: 00 01 02 03 Base Address + 1 Byte 2 Byte 2 0x20001 (Base Address + 1)
Data: 12 34 56 78 Base Address + 2 Byte 1 Byte 1 0x20002 (Base Address + 2)

Base Address + 3 Byte 0 Byte 0 0x20003 (Base Address + 3)

Big-Endian Operation

Example: For the hexadecimal number 0x12345678, it is stored as 12 34 56 78 in

memory.
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 Memory
➢ There are different types of memories available to be used in computers as
well as embedded system. In an embedded system, it’s a physical storage for
program code and data.

Int RAM

Ext RAM

Cache

Flash Memory/EEPROM Ext/Int

System Ports

ROM/PROM

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 Memory
Random Access Memory (RAM):
• Volatile memory used for actively running programs and data.
• It is a volatile memory since it stores information based on the power
supply. If the power supply fails/ interrupted/stopped, all the data and
information on this memory will be lost.
• SRAM (Static RAM): Uses transistors and the circuits of this memory are
capable of retaining their state as long as the power is applied. This memory
consists of the number of flip flops with each flip flop storing 1 bit. It has
less access time and hence, it is faster.
• DRAM (Dynamic RAM): Uses capacitors and transistors and stores the data
as a charge on the capacitors. They contain thousands of memory cells. It
needs refreshing of charge on capacitor after a few milliseconds. This
memory is slower than SRAM.

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 Memory
Read Only Memory (ROM):
• Non-volatile memory that stores permanent instructions for starting the
computer. The data cannot be easily overwritten by the computer.
• It is a non-volatile memory since it stores information even when there is a
power supply failed/ interrupted/stopped.
• PROM (Programmable Read Only Memory): This read-only memory is
modifiable once by the user. The user purchases a blank PROM and uses a
PROM program to put the required contents into the PROM. Its content
can't be erased once written.
• EEPROM (Electrically Erasable Programmable Read Only Memory): Here
the written contents can be erased electrically. We can delete and reprogram
EEPROM up to 10,000 times. Erasing and programming take very little
time, i.e., nearly 4 -10 ms. Any area in an EEPROM can be wiped and
programmed selectively.
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 Memory
Cache Memory:
• A very fast, high-speed memory that holds frequently used data for the CPU to
access quickly.
• Between the CPU and the main memory, it serves as a buffer. It is used to store the
data and programs that the CPU uses the most frequently.
• When compared to the main memory, it takes less time to access it.
• It stores data for temporary use.
System Ports:
• Interfaces to memory that allow multiple accessors, like processors, to read or write
data simultaneously.
• A single-port memory has one interface, while a multi-port memory has two or more.
• Dual-port memory is a common type that has two independent ports, allowing two
devices to access the same memory at the same time, sometimes even the same
location.

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Memory
Specifications:

Cache Main Memory

• 64K x 32 • Memory Address – 32 bits
• Organized as 128 0.5K • 256K x 32
Blocks • Organized as 4 Pages –
• Direct Mapped Each Page has 128 0.5K
Blocks

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 Memory
➢ To organize 64 K (kilobytes) of memory as 128 units of 0.5 K, we can
follow this approach:
1. Calculate Total Memory Size :
a. 64 K = 64,000 bytes (approximation, since K generally stands for
1024 in a binary context, this equals 64 * 1024 = 65,536 bytes).
2. Calculate the Size of Each Unit :
a. 0.5 K = 0.5 * 1024 bytes = 512 bytes.
3. Calculate the Total Number of Units :
a. 64 K memory can be divided by the size of each unit:
b. 65,536 bytes / 512 bytes per unit = 128 units.
Therefore, 64 K of memory can indeed be organized into 128 separate
units of 0.5 K each. Each unit would represent a block of 512 bytes, and when we have
128 blocks, they collectively occupy the entire 64 K of memory.
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Memory – Direct Mapped Cache
Page 0 ………………............... Page 3
Block 0 Data 0 Block 0 Block 0 Block 0 Block 0 Data 0

Data 511 Data 511

Block 1 Data 0 Block 1 Block 1 Block 1 Block 1 Data 0

Data 511 Data 511

Block 127 Data 0 Block 127 Block 127 Block 127 Block 127 Data 0

Data 511 Data 511

Cache Main Memory

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 Cache Mapping
Page 0 Block 0 Block 0
Block 1 Block 1
Block N Block N
Page 1 Block 0
Block 1 Cache
Block N
Page 2 Block 0
Block 1
Block N
Page 3 Block 0
Block 1
Block N

Main Memory
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 Cache Mapping
Valid Tag Data
Cache Block 1
Cache Block 2

Cache Block 3

Cache Block 4

Address • Dirty Bit

Tag Index Offset • Write Back
• Write Through
= Value
Hit
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Memory – Set Associative Mapped Cache
Cache Organization :

Cache Main Memory

256 K x 32
64K x 32 512 Blocks -m
128 0.5 K blocks 64 Groups –n
Two sets Group No m mod n

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Memory – Set Associative Mapped Cache
Main Memory Organization :

Block Group

0 64 448 0
1 65 449 1

2 66 450 2

63 127 511 63

T0 T1 T7

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Memory – Set Associative Mapped Cache
Block

Tag

Bank 1 Bank 1 Bank N

Bank Select

Data
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Memory Map

Memory Mapped I/O

INSTRUCTIONS

RAM

NVRAM

Stack

System

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Other Hardware Components
Specific Operation Range

Range of Voltages

• 5.0±0.25 V
• 3.3 ±0.3
• 2.0 ±0.2
• 1.5 ±0.2 V
• Additionally, EEPROM/ RS232 C –12 V
Usual Pattern of Power Distribution
• 2 pins of VDD+ VSS
• Distributes power to all sections and reduces
interference
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Other Hardware Components
Ext I/O
Separation
Timers
of Power
Clock + Reset
Lines
Analog to Digital Converter

• VDD, VSS, AGnd, AREF, AIP

Some Devices use charge pumps – no
external power supply

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Power and Performance
Propagation Delay in Gates – 1/V

Power consumed in CMOS circuits – V2

An ES has to perform tasks continuously

Power Saving Important

Wait State / Stop State

• 2.5 mW /100 KHz

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Power and Performance
SA 1100 –2 Low Power Modes
• Normal Consumes Max Power
Run

• Saves power by stopping the

CPU clock
Idle

• Turns off all units except Power-0

• Keeps Power unit thro’ I/O power supply line
Sleep

• Low speed clock available for power manager

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Power and Performance

400 mW
Run

10 us 10 us 90 us
160 ms
Idle Sleep
90 us
50 mW 0.16 mW

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Clock Oscillator Circuits and
Clocking Units
Clock Source

• Crystal - highest stability - despite temp drifts

• Internal Ceramic Resonator - reasonable stability
• External IC based Oscillator - more driving power
required

RTC/Timers/Counters

• At least one counter in every ES

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Reset Circuit, Power up Reset,
Watchdog Reset

Activated only for a few clock cycles

System reset -
CPU in synch with the reset of rest of the devices

Sources of reset

• Power on reset
• Reset
- IC
- RC
• S/w Instruction /Comp Operating Properly/ Clk
Monitor
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Interrupt Controller
Most Embedded Systems are Real-Time

No. of Interrupts
• HW
• Event Driven
Priority
Latency

Default Priorities
• COP Watchdog
• External Interrupts
• Timer
• Serial I/f
• ADC BITS Pilani, Pilani Campus
ADC, DAC

ADC multi channel

Vref + , Vref
DAC – PWM

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Software in Embedded System

S/w particular to an application

Processor of ES handles inst/data

Final stage → ROM Image

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ROM Image

➢Boot-up program
➢Stack/ Addr pointers
➢Appln Tasks
➢ISR
➢RTOS
➢ i/p data
➢Vector address

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Options for Building Embedded
Systems

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Major Application Areas of
Embedded Systems
➢ Consumer Electronics : Camcorders, Cameras etc.
➢ Household Appliances : Television, DVD players, Washing machine, Fridge, Microwave
Oven etc.
➢ Home Automation and Security Systems: Air conditioners, sprinklers, Intruder detection
alarms, Closed Circuit Television Cameras, Fire alarms etc.
➢ Automotive Industry : Anti-lock breaking systems (ABS), Engine Control, Ignition
Systems, Automatic Navigation Systems etc.
➢ Telecom : Cellular Telephones, Telephone switches, Handset Multimedia Applications etc.
➢ Computer Peripherals : Printers, Scanners, Fax machines etc.
➢ Computer Networking Systems : Network Routers, Switches, Hubs, Firewalls etc.
➢ Health Care : Different Kinds of Scanners, EEG, ECG Machines etc.
➢ Measurement & Instrumentation : Digital multimeters, Digital CROs, Logic Analyzers,
PLC systems etc.
➢ Banking & Retail : Automatic Teller Machines (ATM) and Currency counters,
Point of Sales (POS).
➢ Card Readers : Barcode, Smart Card Readers, Handheld Devices etc.

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 Q&A

Thank you

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