BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING

EEE 304 – Digital Electronics Laboratory

Experiment 05
Design, Simulation, and Test of Finite State Machines
Using Verilog and Implementation in FPGA

Evaluation Form:
IMPORTANT! You must complete this experiment during your scheduled lab period.
All work for this experiment must be demonstrated to and verified by your lab
instructor before the end of your scheduled lab period.

STEP DESCRIPTION MAX SCORE

1 Implementation of Moore Machine using Verilog in FPGA 10
2 Implementation of Mealy Machine using Verilog in FPGA 10
3 Report tasks 10
TOTAL 30

Signature of Evaluator: ___________________________________________________

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IMPORTANT! Please carefully read and sign the Academic Honesty Statement, below. You
will not receive credit for this lab experiment unless this statement is signed in the presence of
your lab instructor.

“In signing this statement, I hereby certify that the work on this experiment is my own and that I have not copied
the work of any other student (past or present) while completing this experiment. I understand that if I fail to honor
this agreement, I will receive a score of ZERO for this experiment and be subject to possible disciplinary action.”

Name: Lab Group: Date:

E-mail: _____ @[Link] Signature: _____

Contents

Evaluation Form: ..................................................................................................................... 1

1 Introduction ...................................................................................................................... 1
1.1 Lab overview ........................................................................................................... 1
2 Pre-lab Study .................................................................................................................... 1
3 Introduction to State Machine .......................................................................................... 2
3.1 States ........................................................................................................................ 2
3.2 State Diagrams ......................................................................................................... 2
3.3 Mealy vs Moore Machines....................................................................................... 3
4 Design of State Machine: Step-by-Step Process .............................................................. 4
4.1 Implementation of State Machine for Pattern Detection: Moore Type ................... 4
4.2 Implementation of State Machine for Pattern Detection: Mealy Type .................... 8
5 Lab exercises .................................................................................................................. 10
6 Report Tasks .............................................................................................................. 10
7 Appendix ........................................................................................................................ 11
7.1 Appendix A: Necessary Codes .............................................................................. 11
7.2 Appendix B: Basic I/O for Nexys A7-100T: ......................................................... 18
7.3 Appendix C: Acknowledgement and References .................................................. 18
1 Introduction

1.1 Lab overview

At the end of this lab, you will be able to:

• Familiarize yourself with finite state machines

• Construct Mealy and Moore type state diagram
• Understand the difference between Mealy and Moore type machine
• Write Verilog codes for finite state machines and implement them in FPGA

2 Pre-lab Study

Before attempting this lab, please do the following:

1. Make sure you have studied theory of sequential circuit and Finite State Machine
(FSM).
2. Understand different types of Flip-Flops i.e. D type, T type Flip-Flops including their
synchronous and asynchronous reset operations.
3. Write the Verilog code of a D type Flip-flop with asynchronous reset and draw its
logic circuit.
4. Understand the difference between blocking and non-blocking statements.
5. Understand logic simplification using Karnaugh Maps (K-Maps).
6. Make sure you can use the built-in clock of the FPGA board where necessary

Reference text: Chapter 6 Stephen Brown, Zvonko Vranesic - Fundamentals of Digital Logic
with Verilog Design (3rd Edition)

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3 Introduction to State Machine

A state machine is a digital circuit that relies not only on the circuit's inputs, but also the
current state of the system to determine the proper output. For example, assume an elevator is
stopped on the eighth floor and someone from the fourth floor presses the elevator call
button. The elevator needs to decide whether to go up or down. As long as it remembers its
current state, i.e., that it is on the eighth floor, it will know that it needs to go down to access
the fourth floor. To remember the current state of a system, memory will have to be added to
our circuits. This memory will act as additional inputs to the circuitry used to create the
outputs.

3.1 States
A state defines the current condition of a system. The most basic traffic signal controls an
intersection with two directions, North-South and East-West for example. There are certain
combinations of lights (on or off) that describe the intersection's condition. These are the
system's states.

Figure 1: States of a Traffic Signal System

A state machine might also be as simple as a light bulb. The light bulb can have two states:
on and off. The light switch moves the condition of the bulb from one state to another.

Figure 2: States of a Light Bulb

3.2 State Diagrams

A state diagram models a state machine by using circles to represent each of the possible
states and arrows to represent all of the possible transitions between the states, also the cause
of state transitions. We need to include the boolean output associated with each of the states.
Figure 4 presents the completed state diagram for the light bulb problem shown in Figure 3.
The upper half of each circle indicates the name of the state. The lower half indicates the
binary output associated with that state. In the case of the light bulb state machine, a zero is

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output while we are in the OFF state and a one is output while we are in the ON state. The
arrows along with the input value say that when we are in state OFF and the switch input
goes to a 1, move to state ON. When we are in state ON and the switch input goes to a 0,
move to state OFF.

Figure 3: Complete State Diagram for Light Bulb State Machine

Before creating a state diagram, we must define the parameters of the system. We begin with
the inputs and outputs. The inputs are vital to the design of the state diagram as their values
will be used to dictate state changes. As for the outputs, their values will be determined for
each state as we create them.

3.3 Mealy vs Moore Machines

Before we dive into designing state machines, it's important to understand that there are two
fundamental types of finite state machines: Moore machines and Mealy machines. The key
difference between them lies in how they generate their outputs.

Moore Machine
In a Moore machine, the output depends only on the current state of the system, not on the
current input. As shown in the block diagram, the system consists of three main components:
the next state logic (combinational circuit that determines the next state based on current
state and inputs), the latches/flip-flops (storage elements that hold the current state), and the
output logic (combinational circuit that generates outputs) shown in Figure 4.

Figure 4: Block diagram of Moore machines

The system inputs feed into the next state logic along with the current state from the latches,
but the output logic receives only the current state from the latches, not the system inputs.

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The clock signal synchronizes state transitions by triggering the latches to update from the
next state to the current state. This means that the output can only change when the state
changes, which occurs on clock edges, making Moore machines less susceptible to input
glitches but potentially requiring more states.

Mealy Machine
In a Mealy machine, the output depends on both the current state and the current inputs.
The system has the same three components: logic determining the next state (computes next
state from external inputs and current state), latches outputting the current state (storage
elements synchronized by clock), and logic determining the output from current state
(generates system outputs) shown in Figure 5. However, as illustrated in the block diagram,
both the external inputs and the current state from the latches are fed into the output logic
block. This allows the output to respond immediately to changes in the input without waiting
for the next clock edge, potentially making Mealy machines faster and requiring fewer states.
The system inputs serve a dual purpose: they determine the next state and also directly
influence the current output.

Figure 5: Block diagram of Mealy machines

4 Design of State Machine: Step-by-Step Process

4.1 Implementation of State Machine for Pattern Detection: Moore Type

A common application for state machines is to watch for a specific binary pattern within a
serial data stream. The binary pattern may be used to indicate the start or end of a message or
to alert the receiving device that a control sequence is about to come. Let's design a state
machine that monitors an input bit stream w and produces an output z = 1 when the previous
two values of w were either 00 or 11; otherwise z = 0. This is a pattern detector that
recognizes when two consecutive identical bits occur.
If a clock can be produced that pulses once for each incoming bit, then we can develop a state
machine that detects this pattern. The state machine will initially output a zero indicating no

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Design, Simulation, and Test of Finite State Machines Using Verilog and Implementation in FPGA
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pattern match and will continue to output this zero until the full pattern is received. When the
full pattern is detected, the state machine will output a 1 for one clock cycle. When a clock
pulse is received, the next state is stored in the latches where it becomes the current state. The
list below identifies each of the states along with the states they would transition to based on
the input conditions.
• State A: Initial/reset state where no pattern has been detected yet or the previous
pattern has been broken. The system starts here and returns here when the input
sequence doesn't match either detection pattern. (Output z = 0)
• State B: The system has received a single 0 and is waiting to see if the next bit will
also be 0 to complete the "00" pattern. This is a transitional state where we're tracking
the first bit of a potential "00" sequence. (Output z = 0)
• State C: Pattern "00" has been successfully detected - the last two consecutive bits
received were both 0. The system will remain in this state as long as it continues to
receive 0 inputs, indicating an ongoing sequence of zeros. (Output z = 1)
• State D: The system has received a single 1 and is waiting to see if the next bit will
also be 1 to complete the "11" pattern. This is a transitional state where we're tracking
the first bit of a potential "11" sequence. (Output z = 0)
• State E: Pattern "11" has been successfully detected - the last two consecutive bits
received were both 1. The system will remain in this state as long as it continues to
receive 1 inputs, indicating an ongoing sequence of ones. (Output z = 1)
Apart from the clock signal, the other input to our system is w, the bit stream we are
monitoring. The value of w at each clock pulse determines which state we transition to next.
The desired FSM can be specified using the state diagram in Figure 6.

Figure 6: State Diagram for Moore type FSM

This is a Moore machine because the output depends only on the current state, not on the
current input. The corresponding state table is noted in Table 1.

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 Table 1: State Table for Pattern Detection

The next step is to assign binary values to each state. A straightforward state assignment can
be done as shown in Table 2.
Table 2: State assigned Table for Pattern Detection

Here, y₃y₂y₁ represents the current state of the system, stored in the three flip-flops, where y₃
is the most significant bit, y₂ is the middle bit, and y₁ is the least significant bit. These current
state values are inputs to the combinational logic that determines the next state and output.
Y₃Y₂Y₁ represents the next state of the system, which is the 3-bit value computed by the next
state combinational logic based on the current state (y₃y₂y₁) and the input (w). These values
will be loaded into the flip-flops on the next rising clock edge, at which point Y₃Y₂Y₁
becomes the new current state y₃y₂y₁. We can get the expression to determine Y₃Y₂Y₁ using
Karnaugh maps as follows:

This leads to a pretty complex set of expression. Now, observe that state A is reached only
when the machine is reset by means of the Reset input. So, it may be advantageous to assign
the four codes in which y3 = 1 to the states B, C, D, and E. The result is the new state-
assigned table 3.

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Design, Simulation, and Test of Finite State Machines Using Verilog and Implementation in FPGA
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 Table 3: Improved state assigned Table for Pattern Detection

Here the codes y₃y₂y₁ = 001, 010, 0 11 can be treated as don’t-care conditions. Then the
expressions for next-state and output is derived using Karnaugh maps:
𝑌1 = 𝑤𝑦2 + 𝑤
̅𝑦̅̅̅2
𝑌2 = 𝑤
𝑌3 = 1
𝑧 = 𝑦1
These expressions give us the final implementation of our state machine. By converting the
expressions to logic circuits, we get the circuit shown in Figure 7.

Figure 7: Finished Logic Circuit for Moore type FSM

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Design, Simulation, and Test of Finite State Machines Using Verilog and Implementation in FPGA
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4.2 Implementation of State Machine for Pattern Detection: Mealy Type

The same sequence detector can also be implemented as a Mealy machine, where the output
depends on both the current state AND the current input, not just the state alone. For the
Mealy version, we can use fewer states because the output can be determined immediately
when we see the input that completes the pattern. To this the state diagram needs to be
modified. The modified states are:

• State A: Initial/reset state where the system begins operation and has not yet
established any pattern history. From this state, the system branches based on whether
it receives a 0 (transitioning to State B) or a 1 (transitioning to State C), setting up the
foundation for pattern detection. This state serves as the neutral starting point before
any meaningful bit sequence has been observed.

• State B: The system has most recently received a 0 and is tracking sequences
involving zero. If another 0 arrives (input w=0), the output z=1 is immediately
produced because the pattern "00" is detected, and the system loops back to State B to
continue tracking zeros. If a 1 arrives (input w=1), no pattern is detected (z=0) and the
system transitions to State C to begin tracking ones instead.

• State C: The system has most recently received a 1 and is tracking sequences
involving one. If another 1 arrives (input w=1), the output z=1 is immediately
produced because the pattern "11" is detected, and the system loops back to State C to
continue tracking ones. If a 0 arrives (input w=0), no pattern is detected (z=0) and the
system transitions to State B to begin tracking zeros instead.

The modified state diagram according to the new states is shown in Figure 8.

Figure 8: Pattern Detector Logic Circuit for Mealy type FSM

Now we can get the state table in a similar manner to the previous section 4.1

EEE 304 – Digital Electronics Laboratory

Design, Simulation, and Test of Finite State Machines Using Verilog and Implementation in FPGA
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 Table 4: State Table for Pattern Detection in Mealy type

The next step is to assign binary values to each state which produces the state assigned table:
Table 5: State assigned Table for Pattern Detection in Mealy Type

Using Karnaugh map we get the following expressions

𝑌1 = 1
𝑌2 = 𝑤
𝑧=𝑤
̅𝑦1 ̅̅̅
𝑦2 + 𝑤𝑦2
These expressions ca be easily translated into a logic circuit in Figure 9.

Figure 9: Finished Logic Circuit for Mealy type FSM

EEE 304 – Digital Electronics Laboratory

Design, Simulation, and Test of Finite State Machines Using Verilog and Implementation in FPGA
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5 Lab exercises

Lab Problem 1: A code for pattern detector described in section 4.1 (for Moore type FSM) is
provided in the Appendix. Write a Verilog code and implement this design on the Nexys A7
FPGA and verify its operation. Demonstrate current state and next state using the 7-segment
display as shown in Figure 10.

Figure 10: Output configuration for Lab Problem 1 and 2

Lab Problem 2: Write the Verilog Code for the pattern detector described in section 4.2
using a Mealy type FSM. Demonstrate current state and next state using the 7-segment
display as shown in Figure 10. Observe the difference between Moore and Mealy type FSM.

6 Report Tasks

Report Task 1: Nth Fibonacci Number Calculator using Moore FSM

Design a Moore-type Finite State Machine in Verilog to calculate the nth term of the
Fibonacci sequence. The module accepts as input a number n of 4 bits and outputs the nth
Fibonacci number. The FSM must iteratively calculate Fibonacci numbers using the
recurrence relation: F(n) = F(n-1) + F(n-2), where F(0) = 0 and F(1) = 1. The first two
numbers in the sequence are 0 and 1.
Report Task 2: Vending Machine Controller using Mealy FSM
Design a Mealy-type Finite State Machine in Verilog for a vending machine that accepts
coins and dispenses a product when 15 taka is reached. The machine accepts 5 taka and 10
taka coins. When the total reaches exactly 15 taka, the machine outputs a vend signal. When

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Design, Simulation, and Test of Finite State Machines Using Verilog and Implementation in FPGA
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the total exceeds 15 taka, the machine must output both a vend signal and a change return
signal.
Report Task 3: Equivalent FSM

Identify if there is an equivalent state machine with fewer states by checking to see if any
states in the diagram above are equivalent. Two states are equivalent if
(1) they have identical outputs and
(2) for each possible combination of inputs they transition to equivalent states.
Draw the state transition diagram for the simplified FSM

7 Appendix

7.1 Appendix A: Necessary Codes

Code for Moore type FSM:
module sequence(clk, Resetn, w, z,CLK0, an, seg);
input clk, Resetn, w;
output z;
output wire CLK0;
output reg[6:0] seg;
output reg [7:0] an;
clock_div U1(.clk(clk),.slow_clk(CLK0));

reg [3:1] y, Y;
parameter [3:1] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
reg [19:0] refresh_counter;

always @(posedge clk) begin

refresh_counter <= refresh_counter + 1;
end

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 // Use one bit of the counter to toggle between the two digits
wire digit_select = refresh_counter[18];

// Define the next state combinational circuit

always @(w, y)
case (y)
A: if (w)
Y = D;
else
Y = B;
B: if (w)
Y = D;
else
Y = C;
C: if (w)
Y = D;
else
Y = C;
D: if (w)
Y = E;
else
Y = B;
E: if (w)
Y = E;
else
Y = B;
default: Y = 3'bxxx;
endcase

// Define the sequential block

always @(negedge Resetn, posedge CLK0)
if (Resetn == 0)

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 y <= A;
else
y <= Y;

// 7-SEG DECODER
function [6:0] state_to_seg;
input [2:0] state;
begin
case (state)
3'b000: state_to_seg = 7'b0001000; // A
3'b001: state_to_seg = 7'b1100000; // b
3'b010: state_to_seg = 7'b0110001; // C
3'b011: state_to_seg = 7'b1000010; // d
3'b100: state_to_seg = 7'b0110000; // E
default: state_to_seg = 7'b1111111;
endcase
end
endfunction

// 7-SEG MULTIPLEXING (FAST CLOCK)

always @(*) begin
if (!Resetn) begin
an <= 8'b11111111;
seg <= 7'b1111111;
end
else begin
if (!digit_select) begin
an <= 8'b11111110; // AN0 → current state
seg <= state_to_seg(y);
end
else begin
an <= 8'b11111101; // AN1 → next state
seg <= state_to_seg(Y);
end

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 end
end

// Define output
assign z = (y == C) | (y == E);
endmodule

Code for Mealy type FSM:

module sequence_mealy (clk, Resetn, w, z,CLK0, an, seg);
input clk, Resetn, w;
output reg z;
output wire CLK0;
output reg[6:0] seg;
output reg[7:0] an;

// Clock generators
clock_div U1 (.clk(clk), .slow_clk(CLK0));

// FSM states
reg [1:0] y, Y;
reg [19:0] refresh_counter;

always @(posedge clk) begin

refresh_counter <= refresh_counter + 1;
end

// Use one bit of the counter to toggle between the two digits
wire digit_select = refresh_counter[18];
// State encoding
parameter [1:0] A = 2'b00,
B = 2'b01,
C = 2'b11;

// Define the next state and output combinational circuit

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 always @(w, y)
case (y)
A: if (w) begin
z = 0;
Y = C;
end
else begin
z = 0;
Y = B;
end
B: if (w) begin
z = 0;
Y = C;
end
else begin
z = 1;
Y = B;
end
C: if (w)
begin
z = 1;
Y = C;
end
else begin
z = 0;
Y = B;
end
default:
begin
z = 0;
Y = 2'b00;
end
endcase

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Design, Simulation, and Test of Finite State Machines Using Verilog and Implementation in FPGA
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 // Define the sequential block
always @(posedge CLK0 or negedge Resetn)
if (Resetn == 0)
y <= A;
else
y <= Y;

// 7-SEG DECODER
function [6:0] state_to_seg;
input [1:0] state;
begin
case (state)
2'b00: state_to_seg = 7'b0001000; // A
2'b01: state_to_seg = 7'b0000000; // B
2'b11: state_to_seg = 7'b0110001; // C
default: state_to_seg = 7'b1111111;
endcase
end
endfunction

// 7-SEG MULTIPLEXING (FAST CLOCK)

always @(*) begin
if (!Resetn) begin
an <= 8'b11111111;
seg <= 7'b1111111;
end
else begin
if (!digit_select) begin
an <= 8'b11111110; // AN0 → current state
seg <= state_to_seg(y);
end
else begin
an <= 8'b11111101; // AN1 → next state
seg <= state_to_seg(Y);

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Design, Simulation, and Test of Finite State Machines Using Verilog and Implementation in FPGA
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 end
end
end
endmodule

Code for configuring clock:

module clock_div(clk,slow_clk);
input clk;
output reg slow_clk;
reg [26:0] ref_count;

always @(posedge clk)

begin
ref_count <= ref_count + 1;
if (ref_count == 27'b111111111111111111111111111)
begin
ref_count <= 0;
slow_clk<=~slow_clk;
end
end
endmodule

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Design, Simulation, and Test of Finite State Machines Using Verilog and Implementation in FPGA
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7.2 Appendix B: Basic I/O for Nexys A7-100T:

7.3 Appendix C: Acknowledgement and References

The labsheet is prepared by Nafis Sadik, Mrinmoy Kundu and Sadat Tahmeed Azad at the
Department of EEE, BUET, on 14/07/2023 under the supervision of Mr. Hamidur Rahman.
It has been updated by Tanvir Hossain and Archisman Sarkar at the Department of EEE, BUET
on 27/01/2026 under the supervision of Dr. Hamidur Rahman.

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