8255 PPI
The parallel input-output port chip 8255 is also called as parallel input-output port or
programmable peripheral input-output port.
The Intels 8255 are designed for use with Intels 8-bit, 16-bit and higher capability
microprocessors. It has 24 input/output lines which may be individually programmed in two
groups of twelve lines each, or three groups of eight lines.
ARCHITECTURE OF 8255
The two groups of I/O pins are named as Group A and Group B. Each of thesetwo groups
contains a subgroup of eight I/O lines called as 8-bit port and anothersubgroup of four lines
or a 4-bit port. Thus Group A contains an 8-bit port Aalong with a 4-bit port C upper.
The port A lines are identified by symbols PA0-PA7 while the port C lines are identified as
PC4-PC7 similarly. Group B contains an 8-bit port B, containing lines PB0- PB7 and a 4-bit
port C with lower bits PC0-PC3. The port C upper and port C lower can be used in
combination as an 8-bit port C. Both the port Cs is assigned the same address. Thus one may
have either three 8-bit I/O ports or two 8-bit and two 4-bit I/O ports from 8255. All of these
ports can function independently either as input or as output ports. This can be achieved by
programming the bits of an internal register of 8255 called as control word register (CWR).
The 8-bit data bus buffer is controlled by the read/write control logic. The read/write control
logic manages all of the internal and external transfer of both data and control words. RD,
WR, A1, A0 and RESET are the inputs, provided by the microprocessor to READ/WRITE
control logic of 8255. The 8-bit, 3-state bidirectional buffer is used to interface the 8255
internal data bus with the external system data bus. This buffer receives or transmits data
upon the execution of input or output instructions by the microprocessor. The control words
or status information is also transferred through the buffer.
PA7-PA0: These are eight port A lines that acts as either latched output or buffered input lines
depending upon the control word loaded into the control word register.
PC7-PC4: Upper nibble of port C lines. They may act as either output latches or input buffers
lines. This port also can be used for generation of handshake lines in mode1 or mode2.
PC3-PC0: These are the lower port C lines; other details are the same as PC7-PC4 lines.
PB0-PB7: These are the eight port B lines which are used as latched output lines or buffered
input lines in the same way as port A.
RD: This is the input line driven by the microprocessor and should be low to indicate read
operation to 8255.
WR: This is an input line driven by the microprocessor. A low on this line indicates write
operation.
CS: This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and
WR signals, otherwise RD and WR signal are neglected.
D0-D7: These are the data bus lines those carry data or control word to/from the
microprocessor.
RESET: Logic high on this line clears the control word register of 8255. All ports are set as
input ports by default after reset.
A1-A0: These are the address input lines and are driven by the microprocessor. These lines
A1-A0 with RD, WR and CS from the following operations for 8255. These address lines are
used for addressing any one of the four registers, i.e. three ports and a control word register as
given in table below.
MODES OF OPERATION OF 8255
Operating modes of 8255 are i)Bit Set-Reset mode (BSR) mode and ii) I/O mode
--In BSR mode only port C (PC0-PC7) can be used to set or reset its individual port bits.
--In I/O mode, the 8255 ports work as programmable I/O ports. Under the I/O mode of
operation, further there are three modes of operation of 8255, so as to support different types
of applications, mode 0, mode 1 and mode 2.
i)Bit Set-Reset mode (BSR) mode
In this mode any of the 8-bits of port C can be set or reset depending on D0 of the control
word. The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR as
given in table.
Fig. Control word for BSR mode
ii) I/O Modes
a) Mode 0 (Basic I/O mode)
The features of Mode 0:
1. Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper and lower) are
available. The two 4-bit ports can be combined used as a third 8-bit port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
4. A maximum of four ports are available so that overall 16 I/O configurations
are possible.
b) Mode 1 (Strobed input/output mode)
The salient features of mode 1 :
1. Two groups – group A and group B are available for strobed data transfer.
2. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
3. The 8-bit data port can be either used as input and output port. The inputs and
outputs both are latched.
4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B and
PC3-PC5 are used to generate control signals for port A. the lines PC6, PC7 may
be used as independent data lines.
c) Mode 2 (Strobed bidirectional I/O):
The Salient features of Mode 2 :
1. The single 8-bit port in group A is available.
2. The 8-bit port is bidirectional and additionally a 5-bit control port is available.
3. Three I/O lines are available at port C.( PC2 – PC0 )
4. Inputs and outputs are both latched.
5. The 5-bit control port C (PC3-PC7) is used for generating / accepting
handshake signals for the 8-bit data transfer on port A.