Department of Electronics & Communication Engineering

Basic Electronics Notes (ECE111)

NitteDU - 2025-26
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January - 2026
Contents

1 Diodes and their Applications 3

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 PN DIODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 Unbiased PN Junction Diode . . . . . . . . . . . . . . . . . . . . 5
1.2.2 Biasing of the Diode . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 VI characteristics of the Si and Ge diode: . . . . . . . . . . . . . . . . . . 8
1.4 Diode Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Numerical on Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.6 Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6.1 Half Wave Rectifier (HWR) . . . . . . . . . . . . . . . . . . . . . 14
1.6.2 Full Wave Bridge Rectifier (FWBR) . . . . . . . . . . . . . . . . . 19
1.7 Filter Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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1.7.1 Bridge Rectifier with Capacitor Filter . . . . . . . . . . . . . . . . 25
1.8 Numerical on Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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1.9 Zener Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.9.1 VI Characterstics of Zener Diode . . . . . . . . . . . . . . . . . . 31
1.9.2 Zener diode as a Voltage Regulator . . . . . . . . . . . . . . . . . 34
1.10 Numerical on Zener Diode . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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2 Transistors and their Applications 41

2.1 Introduction of Bipolar junction transistors (BJT) . . . . . . . . . . . . . 41
2.1.1 NPN Transistor Operation . . . . . . . . . . . . . . . . . . . . . . 42
2.1.2 BJT Voltages and Currents (NPN) . . . . . . . . . . . . . . . . . 44
2.1.3 Relation between α and β: . . . . . . . . . . . . . . . . . . . . . . 45
2.2 Numerical on Transistor Currents and Current Gain . . . . . . . . . . . . 46
2.3 Transistor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.3.1 Common Emitter Configuration (NPN) . . . . . . . . . . . . . . . 47
2.4 CE-RC Coupled Amplifier (Single Stage) . . . . . . . . . . . . . . . . . . 50
2.5 Transistor as a Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.6 Field Effect Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.6.1 N channel Enhancement Type Metal Oxide Semiconductor (N-
EMOSFET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.7 CMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3 Op-Amp & Linear IC Applications 59

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.2 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3 Op-Amp Parameters: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.4 Ideal Op-Amp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 64

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3.5 Practical values: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.6 Numerical on Op-Amp Characteristics . . . . . . . . . . . . . . . . . . . 66
3.7 Virtual Ground Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.8 Saturable Property of an Op-Amp: . . . . . . . . . . . . . . . . . . . . . 68
3.9 Op-Amp Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.9.1 Inverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.9.2 Noninverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 71
3.9.3 Inverting Summer (Adder) . . . . . . . . . . . . . . . . . . . . . . 73
3.9.4 Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.9.5 Differentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.9.6 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.10 IC Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.11 Numerical on Op-Amp Applications . . . . . . . . . . . . . . . . . . . . . 82

4 Feedback and Oscillator Circuits 90

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.2 Negative Feedback Concepts . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.3 Voltage series negative feedback amplifier . . . . . . . . . . . . . . . . . . 91
4.4 Numerical on Voltage series feedback amplifier . . . . . . . . . . . . . . . 92
4.5 Oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.5.1 Barkhausen criterion . . . . . . . . . . . . . . . . . . . . . . . . . 94
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4.6 Types of Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.6.1 RC Phase Shift Oscillator . . . . . . . . . . . . . . . . . . . . . . 96
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4.6.2 Hartley Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.6.3 Colpitts Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.7 Numerical on Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5 Fundamentals of Communication and Embed-

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ded Systems 107

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.2 Basic Blocks of Communication Systems . . . . . . . . . . . . . . . . . . 107
5.3 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.1 Need for modulation . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.4 Telecommunication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.5 Cellular Communication System . . . . . . . . . . . . . . . . . . . . . . . 111
5.5.1 Different events between the mobile unit and a cellular system while
a phone number is entered . . . . . . . . . . . . . . . . . . . . . . 112
5.5.2 Frequency reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.5.3 Why a cell is hexagon in shape? . . . . . . . . . . . . . . . . . . . 113
5.6 Embedded Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.6.1 Elements of Embedded Systems . . . . . . . . . . . . . . . . . . . 114
5.6.2 Difference between Microprocessor and Microcontroller . . . . . . 116
5.6.3 Sensors and Actuators . . . . . . . . . . . . . . . . . . . . . . . . 116

REFERENCES 117

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Chapter 1

Diodes and their Applications

1.1 Background
Materials can be classified into three types as mentioned below. The Figure 1.21 shows
the energy band gap of different materials.

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Figure 1.1: Energy Band Gap of different Materials: (a) Insulators, (b) Conductors, (c)
Semiconductors

⋆ Conductors: Are very good carriers of electricity. They have a large number of
free electrons since there is no energy gap between conduction band and valence
band. E.g., Copper, Aluminium.

⋆ Insulators: Do not conduct electricity. There is a large energy gap between con-
duction band and valence band. Eg: Wood, glass.

⋆ Semi-Conductors: Are neither insulators, nor conductors. The band Gap be-
tween conduction band and valence band is very narrow. Eg: Germanium (Ge),
Silicon (Si) conductivity lies between conductors and insulators. There are 2 types
of semiconductors.

– Intrinsic semiconductors: Semiconductor in its purest form is intrinsic

semiconductor. It behaves as an insulator at zero temperature. At room
temperature, electron hole pairs are created, due to the drift of electrons to
the conduction bond. This creates a vacancy called as a ‘hole’. Holes are
positively charged while electrons are negatively charged.

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Thus, the movement of electrons in conduction band yields electron and the
movement of holes in valence band gives rises to a hole current.
– Extrinsic semiconductors: Are created by adding impurities (or other ma-
terials) to intrinsic semiconductors to improve conductivity or conduction na-
ture of the materials used in diodes, transistors etc. Depending upon the
type of impurities added, we have 2 types: P-type semiconductors and N-type
semiconductors.
* P-type semiconductors: Are produced by doping intrinsic semiconduc-
tors with trivalent impurities also known as acceptor impurities (ions). In
this hole are majority charge carriers and electrons are the minority charge
carriers. Eg: trivalent impurities are Boron, Aluminium.
* N-type semiconductors: are generated by doping intrinsic semicon-
ductors with pentavalent impurities. Eg: Arsenic, phosphorous. These
impurities are known as donor ions. In n-type semiconductors, electrons
are the majority charge carriers and holes are minority charge carriers.

NOTE:

– Active components: Transforms one form of signals to another form. Eg:

Transistors, MOSFETS, OP-Amp, Gates.
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– Passive Components: Diodes, Resistor (R), Inductor (L) and Capacitor (C)
utilizes Power (P) or Voltage (V) from other sources.
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1.2 PN DIODE
ˆ N- type and P-type semiconductor materials are chemically combined with a special
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fabrication technique to form P-N junction. Such P-N junction forms a popular
electronic device called P-N Junction diode.

Figure 1.2: Diode Symbol

ˆ A diode is a basic element for the number of electronic circuits.

ˆ Diode is connected in two modes. That is Forward Bias and Reverse Bias
ˆ P-N junction diode allows current flow when forward biased and blocks the current
flow when reverse biased.

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ˆ It is a Uni-directional (one-way) device offering low-resistance when forward biased

and behaving almost as open switch when reverse biased.

ˆ Arrow head indicates the conventional direction of current flow when the diode is
forward biased.

ˆ Manufacturers provide datasets that specify the maximum forward current and
reverse voltages for various types of diodes.

ˆ Some diodes are low current diodes that are used in switching circuits. High current
diodes are often used as rectifiers for ac to dc conversion.

ˆ P-N junction diode can be get damaged if

– A high forward current overheats the device
– A large reverse voltage causes the junction breakdown.

1.2.1 Unbiased PN Junction Diode

ˆ Unbiased P-N junction is the one where no external source is connected across the
terminals of the device. Consider a zero bias P-N junction as shown in figure 1.3.
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Figure 1.3: Unbaised Diode

ˆ At N-type semiconductor, large number of free electrons are present while at P-type,
small number of free electrons are present.

ˆ Due to this high concentration of electrons at N-side, they get repelled from each
other and hence try to move towards lower concentration region. Hence, the free
electrons from N-side are attracted towards the holes at P-side. Thus, the free
electrons move from N-side (high concentration region) to P-side (low concentration
region) (called Diffusion)

ˆ At P-type semiconductor, large number of holes are present while at N-type, semi-
conductor, small number of holes are present.

ˆ Due to this high concentration of holes at P-side they get repelled and move towards
lower concentration N-side. Hence, the holes from P-side are attracted towards the
free electrons at N-side. Thus, the holes move from P-side (high concentration) to
N-side (low concentration)

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ˆ As holes enter the N region, they recombine with the donor atoms. As donor
atoms accept additional holes, they become positively charged immobile ions. Hence
number of positively charged immobile ions get formed near the junction on N-side.
ˆ Similarly the electrons diffusing from N side to P side recombine with the acceptor
atoms on P side. As acceptor atoms accept additional electrons, they become neg-
atively charged immobile ions. Such large number of negatively charged immobile
ions get formed near the junction on p-side. The formation of immobile ions near
the junction is shown in the Figure 1.3.
ˆ In the region near the junction, there exists a wall of negative immobile charges
on P side and a wall of positive immobile charges on N side. In this region, there
are no mobile charge carriers. Such a region is depleted of the free mobile charge
carriers and hence called depletion region or depletion layer.
ˆ In equilibrium condition, the depletion region gets widened upto a point where no
further electrons or holes can cross the junction. Thus depletion region acts as the
barrier.
ˆ Thus, a barrier is built up near the junction which prevents the further movement
of electrons and holes. The total charge formed at the P-N junction is called barrier
voltage, barrier potential or junction potential.
ˆ The size of the barrier voltage at the P-N junction depends on the amount of doping,
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junction temperature and type of material used. The barrier potential for Si diode
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is 0.7V and for Ge is 0.3V.

1.2.2 Biasing of the Diode

ˆ Applying an external voltage across the terminals of the P-N junction diode is
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known as biasing.
ˆ There are two types:
– Forward biasing
– Reverse biasing

Forward Biased P-N Junction

ˆ A diode is said to be forward biased when its anode is connected to the
positive terminal of the battery and cathode is connected to the negative
terminal.

Figure 1.4: Forward Biasing of the Diode

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ˆ When the diode is forward biased, as long as the applied voltage V is less than the
barrier potential, there is no conduction.
ˆ When the applied voltage V exceeds the barrier potential, the diode becomes for-
ward biased.
– Holes on the P-side are repelled by the positive terminal of the battery and
are driven towards the junction.
– Electrons on the N-side are repelled by the negative terminal of the battery
and move towards the junction.
ˆ As a result, the width of the depletion region decreases.
ˆ As the forward bias voltage V increases further:
– The depletion layer reduces further.
– Eventually, it disappears almost completely.
– A large number of charge carriers flow across the junction.
– This causes an exponential rise in current.

Reverse Biased P-N Junction

ˆ A diode is said to be reverse biased when the anode (P-region) is connected to
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the negative terminal of the battery and the cathode (N-region) is connected
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to the positive terminal.
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Figure 1.5: Reverse Biasing of the Diode

ˆ Electrons from the N-region are attracted towards the positive terminal of the
battery, and holes from the P-region are attracted towards the negative terminal.
ˆ No charge carrier is able to cross the junction. As electrons and holes both move
away from the junction, the depletion region widens. This creates more positive
ions and hence more negative ions in the N region.
ˆ This causes the depletion region to widen and the barrier potential to in-
crease, reducing the flow of majority charge carriers across the junction to nearly
zero.
ˆ Due to increased barrier potential, the electrons from P-region towards the positive
of battery. Similarly negative side of barrier potential drags the holes from N-region
towards the negative of battery. The electrons on P-side and holes on N-side are
minority charge carriers, which constitute the current in reverse biased condition.
This is called the reverse saturation current (IS ).

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ˆ As a result, a reverse biased diode allows only a very small reverse current, and
hence can be considered to have a high reverse resistance.

– Typically in the nanoampere (nA) range for silicon diodes and microampere
µ
( A) or milliampere (mA) for germanium diodes.

ˆ If reverse voltage is increased, at a particular value, velocity of minority carriers

increases. Due to the kinetic energy associated with the minority carriers, more
minority carriers are generated when there is collision of minority carriers with
the atoms. The collision make the electrons to break the co-valent bonds. These
electrons are available as minority carriers and get accelerated due to high reverse
voltage. They again collide with another atoms to generate more minority carriers.

ˆ Finally large number of minority carriers move across the junction, breaking the PN
junction. These large number of minority carriers give rise to a very high reverse
current. This effect is called avalanche effect and the mechanism of destroying
the junction is called reverse breakdown of a p-n junction.

ˆ So, when the reverse voltage V R is sufficiently increased, the diode enters break-
down.

ˆ Caution: Reverse breakdown can permanently damage the diode unless the reverse
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current is limited by a suitable series resistor.
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1.3 VI characteristics of the Si and Ge diode:

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Figure 1.6: VI characteristics of the Si and Ge diode

ˆ V-I characteristics of PN junction diode is the graph of voltage applied across the
diode and the current flowing through the diode.

ˆ The voltage across the diode is V F and the current flowing in the circuit is the
forward current IF . The graph of forward current IF against the forward voltage
VF across the diode is called forward characteristics of a diode.

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ˆ As long as V is less than knee voltage, the current flowing is very small. Practically
F
this current is assumed to be zero.

ˆ As V increases towards knee voltage, the width of depletion region goes on reduc-
F
ing. When VF exceeds knee voltage, the depletion region becomes very thin and
current increases suddenly. This increase in the current is exponential as shown in
the Fig. 1.6.

ˆ At one point, the forward current starts increasing exponentially is called knee of
the curve.

ˆ The reverse voltage across the diode is V

R while the current flowing is reverse current
IR flowing due to minority charge carriers. The graph of IR against VR is called
reverse characteristics of a diode.

ˆ As reverse voltage is increased, reverse current increases initially but after a certain
voltage, the current remains constant equal to reverse saturation current Is though
reverse voltage is increased. At one point, where breakdown occurs and reverse
current increases rapidly is called knee of the reverse [Link] is shown
in the reverse VI characteristics of the diode in Figure 1.6.

Diode Parameters
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ˆ Forward Voltage Drop (V F or VK ):
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The voltage drop across the diode in forward bias condition is known as forward
voltage drop. It is represented as VF and is generally equal to the knee voltage
VK .
Typical values:
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– Silicon (Si): 0.7 V

– Germanium (Ge): 0.3 V

ˆ Maximum Forward Current (I F max ):

It is the maximum current a diode can conduct under forward bias without causing
permanent damage to the P-N junction due to overheating.

ˆ Reverse Breakdown Voltage (V BR ):

It is the reverse bias voltage at which the P-N junction breaks down and a large
current flows, potentially damaging the diode.

– For silicon diodes, breakdown occurs around 75 V.

– For germanium diodes, breakdown occurs around 50 V.

ˆ Reverse Saturation Current (I ): S

It is the very small current that flows through the diode in reverse bias due to
minority carriers.
Typical values:

– Germanium (Ge): in µA
– Silicon (Si): in nA

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ˆ Dynamic Resistance (r ): d
It is the resistance offered by the diode to changing voltages in forward bias. Also
called incremental or AC resistance.
It is given by:
∆VF
rd =
∆IF
From the V -I graph of the diode:
∆IF 1
Slope = ⇒ rd =
∆VF Slope

ˆ Forward Resistance (R F ):
It is the ratio of forward voltage to forward current. Also known as static forward
resistance:
VF
RF =
IF
ˆ Reverse Resistance (R ): R
It is the ratio of reverse voltage to reverse current. Also called static reverse
resistance:
VR
RR =
IR
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1.4 Diode Models
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An equivalent circuit for a device is a circuit that models or simulates its electrical
behavior. It is made up of basic components such as resistors and voltage sources.
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Figure 1.7: Diode Models

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1. Ideal Diode Model

ˆ In an ideal diode:
– Forward Voltage Drop (VF ) = 0
– Forward Resistance (RF ) = 0
– Reverse Resistance (RR ) = ∞
– Reverse Current (IR ) = 0
ˆ This implies perfect conduction in forward bias and perfect insulation in reverse
bias.

2. Approximate Diode Model

ˆ The approximate model includes:
– An ideal diode switch
– A voltage source VF = 0.7 in series to represent the threshold voltage
(barrier potential)
ˆ It neglects the dynamic resistance (r ) and models only the threshold behavior.
E d

3. Piecewise Linear Model

ˆ This model consists of:
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– An ideal diode
– A voltage cell (threshold voltage VF =0.7)
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– A dynamic resistance rd in series

ˆ This model provides a more accurate approximation of a real diode’s forward char-
acteristic.
ˆ Note: When the actual forward characteristics of a diode are not available, this
model provides a straight-line approximation and is called the piecewise linear
model.

1.5 Numerical on Diodes

1. Find the value of current I in the following circuit.

Figure 1.8: Problem 1

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Answer: A Si diode is reverse [Link] it does not conduct.

2. For the circuit shown, calculate ID .

Figure 1.9: Problem 2

Solution: Applying KVL, we get:

15 V − 0.7 V − ID × 3 kΩ = 0

15 − 0.7 14.3
ID = = = 4.76 mA
3kΩ 3kΩ
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3. For the circuit shown, calculate ID and Vo .
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Figure 1.10: Problem 3

Solution:
Applying KVL, we get:

8 V − ID × 1.2 kΩ − ID × 4.7 kΩ − 0.7 V = 0

8 − 0.7 7.3
ID = = = 1.237 mA
(4.7 + 1.2) kΩ 5.9 kΩ

Vo = ID × 4.7 × 103 + 0.7

= 1.237 × 10−3 × 4.7 × 103 + 0.7 = 5.8119 + 0.7 = 6.51 V

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Figure 1.11: Problem 4

4. For the circuit shown, calculate ID and Vo .

Solution
Applying KVL, we have:

−5 V + 2.2 kΩ × ID + 0.7 V = 0

5 − 0.7
∴ ID = = 1.95 mA
E 2.2 kΩ

Vo = 1.95 mA × 2.2 kΩ = 4.3 V

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5. For the circuit shown, calculate the current in the circuit.
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Figure 1.12: Problem 5

Solution: Applying KVL, we get:

12 V − 0.7 V − 0.7 V − ID × 5.6 kΩ = 0

12 − 1.4 10.6
ID = = = 1.893 mA
5.6kΩ 5.6kΩ

1.6 Rectifiers
ˆ One of the most important applications of a junction diode is rectification.
ˆ Rectification is the process of converting alternating current (AC) into direct
current (DC).

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ˆ Rectification can be performed using:

– Half-wave rectifier (uses one diode)
– Full-wave rectifier (uses two or four diodes)

ˆ Depending on the type of AC supply and the configuration of the rectifier circuit,
the output voltage may contain both DC and AC components. This output is called
pulsating DC and includes AC ripples.

ˆ Many applications, such as power supplies for radios, televisions, and computers,
require a steady and constant DC voltage.

ˆ In such applications, the output of the rectifier is passed through a filter circuit
to reduce the ripple content and provide a smooth DC voltage.

ˆ Filter circuits typically consist of:

– Capacitors
– Inductors (chokes)
– Resistors (optional)
– Or a combination (e.g., RC filters, LC filters)

ˆ The filtering process generally involves the use of a large capacitor, which charges
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to the peak of the input voltage and discharges slowly, thus providing a relatively
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constant DC output voltage.

ˆ Filter types:
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– RC Filter: Uses resistor and capacitor

– LC Filter: Uses inductor and capacitor

1.6.1 Half Wave Rectifier (HWR)

ˆ A Half Wave Rectifier requires only one diode for its construction.

Figure 1.13: Half Wave Rectifier

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ˆ In HWR, the diode conducts only during the positive half cycle of the input AC
signal.

ˆ The negative half cycle is blocked, resulting in a unidirectional (pulsating DC)

output.

ˆ The input is a sinusoidal AC voltage. The instantaneous secondary voltage is:

Vs = Vm sin ωt for 0 ≤ ωt ≤ 2π

where, ω = 2πf, and Vm is the peak value of voltage.

Working
ˆ During the positive half cycle of the input AC signal, i.e., 0 ≤ ωt ≤ π:
– The secondary winding of the transformer has node A more positive than node
B.
– The diode D becomes forward biased and acts as a closed switch.
– Current flows through the load resistor RL , producing a voltage across it.
– Since the load is resistive, the current waveform follows the voltage waveform.
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ˆ The load current is given by:
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IL = Im sin ωt for 0 ≤ ωt ≤ π

ˆ Where: Vm
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Im =
Rs + Rf + RL
is the peak value of the current.

ˆ The output voltage is a pulsating DC, and is discontinuous.

ˆ The average or DC value of the output voltage or current is obtained by inte-
grating over one full cycle.

ˆ During the negative half cycle, i.e., π ≤ ωt ≤ 2π:

– Node A becomes negative and node B becomes positive.
– The diode D is reverse biased and acts as an open switch.
– No current flows through the load resistor RL .
– Therefore,
IL = 0 for π ≤ ωt ≤ 2π
– The load voltage is:

VL = Vm sin ωt for 0 ≤ ωt ≤ π

VL = 0 for π ≤ ωt ≤ 2π

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Waveform

Figure 1.14: HWR Waveforms

Parameters
1. Average DC Load Current (IDC ): The average value of an alternating current
is calculated as the area under the one cycle of load current IL from 0 to 2π, divided
by the period of IL , i.e., 2π:
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Area under the one cycle of load current IL
IDC =
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period of IL
Z 2π
1
IDC = IL d(ωt)
2π 0
NI

Given, IL = Im sin(ωt), we have:

Z 2π
1
IDC = Im sin(ωt) d(ωt)
2π 0

Since the current is zero from π ≤ ωt ≤ 2π, the integral becomes:

Z π
Im
IDC = sin(ωt) d(ωt)
2π 0

Im
IDC = [− cos(ωt)]π0
2π

Im
IDC = − [cos(π) − cos(0)]
2π

cos(π) = −1, cos(0) = 1

Im
IDC = − (−2)
2π

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Im
IDC =
π
2. Average DC Load Voltage (VDC ):
The average DC voltage can also be expressed as the product of DC load current
IDC and the load resistance RL :

Im
VDC = IDC × RL = RL
π
Also, since:
Vm
IDC =
π(RL + RS + Rf )
Then:
Vm
VDC = IDC · RL = · RL
π(RL + RS + Rf )

Vm
VDC =  
RS +Rf
π 1+ RL

Since RS + Rf ≪ RL , we approximate:
E
RS + Rf
TT
≪1
RL
Therefore:
NI

Vm
VDC =
π
3. RMS Value of Load Current (IRM S ):
The RMS value of the load current is defined as:
s
(Area under the one cycle of load current IL )2
IRM S =
period of IL
s
Z 2π
1
IRM S = IL2 d(ωt)
2π 0

Since the current is zero for π ≤ ωt ≤ 2π:

s Z π
1
IRM S = IL2 d(ωt)
2π 0

Given IL = Im sin(ωt):
s Z π
1 2 sin2 (ωt) d(ωt)
IRM S = Im
2π 0

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1−cos(2ωt)
Using identity sin2 (ωt) = 2
:
s
2 π
1 − cos(2ωt)
Z
Im
IRM S = d(ωt)
2π 0 2
s  π
2
Im sin(2ωt)
IRM S = ωt −
4π 2 0
r
2
Im Im
sin(2π) = 0, sin(0) = 0 ⇒ IRM S = ·π =
4π 2

Im
IRM S =
2
4. RMS Value of Load Voltage (VRM S )
Similarly,
Im Vm
VRM S = IRM S · RL = RL and Im =
2 RS + R L + R f
So,
E
Vm
VRM S = · RL
2(RL + RS + Rf )
TT

Vm
VRM S =  
RS +Rf
2 1+ RL
NI

Since RS + Rf ≪ RL , we approximate:

RS + Rf
≪1
RL
Therefore:

Vm
VRM S =
2
5. Ripple Factor (γ):
Ripple factor is defined as the ratio of RMS value of AC component to DC com-
ponent of the output. Ripple factor is defined as the ratio of the RMS value of the
AC component to the DC component of the output:

IAC RMS value of AC component of output

γ= =
IDC DC component of output
Here, IRMS is the total RMS current of the rectifier output. It includes both AC
and DC components:

2 2 2
IRMS = IAC + IDC

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2
Solving for IAC :

2 2 2
IAC = IRMS − IDC

Therefore, the ripple factor becomes:

s
2
IAC IRMS
γ= = 2
−1
IDC IDC

Given:

s s r
Im Im (Im /2)2 1/4 π2
IDC = , IRM S = ⇒γ= −1= −1= − 1 ≈ 1.21
π 2 (Im /π)2 1/π 2 4

Hence, ripple content in output = 121% of DC component, indicating poor rectifi-

cation.

6. Efficiency (η):
Efficiency is the ratio of output DC power to input AC power:
E
PDC output DC power I 2 RL
TT
η= = = 2 DC
PAC input AC power IRM S (Rf + RL )

Im 2


2
RL Im /π 2 RL
η=
π = ·
NI

Im 2 2
Im /4 Rf + RL
2
(Rf + RL )

4 RL
= 2
·
π Rf + RL

If Rf ≪ RL , then:

4
η≈ = 0.406 ⇒ η ≈ 40.6%
π2

In Half Wave Rectifiers, the ripple content is high and efficiency is low. Therefore,
output is not very close to pure DC.

1.6.2 Full Wave Bridge Rectifier (FWBR)

ˆ It is a Full Wave Rectifier (FWR) circuit with four diodes.
ˆ An AC voltage is applied to one diagonal of the bridge through a transformer, and
the rectified DC output voltage is taken from the other diagonal of the bridge.

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Figure 1.15: Full Wave Rectifier

Working
ˆ During the positive half cycle of the AC input signal, node A at the secondary of
the transformer is positive while node B is negative. Hence, diodes D1 and D2 are
forward biased and conduct current, while diodes D3 and D4 are reverse biased and
do not conduct.

ˆ The diodes D 1and D2 are connected in series with the load resistance RL , allowing
current to flow through the load.

ˆ During the negative half cycle of the AC input signal, node A becomes negative
E
while node B becomes positive. In this case, diodes D3 and D4 are forward biased
and conduct current, whereas diodes D1 and D2 are reverse biased and remain off.
TT

ˆ Now, diodes D 3 and D4 conduct current through the load resistance RL .

In a Full Wave Rectifier (FWR), load current flows during both the half cycles of the
AC input signal, and in the same direction through the load resistance. As a result, the
NI

negative half cycle of the input signal is also rectified and appears above the axis in the
output waveform.
The load current is given by:

IL = Im sin ωt for 0 ≤ ωt ≤ π
Where:
Vm
Im =
Rs + 2Rf + RL
is the peak value of the current. The load voltage is:

VL = Vm sin ωt for 0 ≤ ωt ≤ π

where, Vm is the peak value of voltage.

Waveform
The input and output waveform of the Bridge rectifiers is shown in the Figure 1.16.

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Figure 1.16: FWR Waveforms

E
Parameters
TT

1. Average Value of Load Current (IDC ): The average value of current is given
by the area under the curve of load current IL over one full cycle:
NI

Area under the one cycle of load current IL

IDC =
period of IL
Z π
1
IDC = IL d(ωt)
π 0
Given: IL = Im sin ωt
1 π
Z
⇒ IDC = Im sin ωt d(ωt)
π 0
1 π
Z
= Im sin ωt d(ωt)
π 0
Im π
Z
= sin ωt d(ωt)
π 0
Im
= [− cos ωt]π0
π
Im
= [− cos π + cos 0]
π
Since cos π = −1 and cos 0 = 1,
Im Im
IDC = [−(−1) + 1] = ·2
π π
2Im
⇒ IDC =
π

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2. Average DC Load Voltage (VDC ):

2Im
VDC = IDC × RL = RL
π

Also, since:
Vm
IDC =
π(RL + RS + 2Rf )

Then:
Vm
VDC = IDC · RL = · RL
π(RL + RS + 2Rf )

Vm
VDC =  
RS +2Rf
π 1+ RL

Since RS + 2Rf ≪ RL , we approximate:

RS + 2Rf
≪1
RL
Therefore:
E
2Vm
TT
VDC =
π
3. RMS Value of Load Current (IRM S ):
NI

s
(Area under the one cycle of load current IL )2
IRM S =
period of IL
s Z
1 π 2
IRM S = I d(ωt)
π 0 L
IL = Im sin ωt
s Z
1 π 2
⇒ IRM S = I sin2 ωt d(ωt)
π 0 m
s Z
2 π
Im 1 − cos 2ωt
= d(ωt)
π 0 2
s  π
Im2 sin 2ωt
= ωt −
2π 2 0

Since sin 0 = sin 2π = 0,

r r
2
Im 2π
Im
IRM S = (π − 0) =
2π 2π
Im
=√
2

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4. RMS Value of Load Voltage (VRM S ):

Im Vm
VRM S = IRM S · RL = √ RL and Im =
2 RS + RL + 2Rf
So,
Vm
VRM S = √ · RL
2(RL + RS + 2Rf )

Vm
VRM S = √  
R +2R
2 1 + SRL f

Since RS + 2Rf ≪ RL , we approximate:

RS + 2Rf
≪1
RL
Therefore:

Vm
VRM S = √
2
E
5. Ripple Factor (γ):
TT
The ripple factor is defined as the ratio of the RMS value of the AC component to
the DC component of the output:

s
NI

2
IAC IAC
γ= = 2
IDC IDC
2 2 2
Since IAC = IRM S − IDC ,
s s
2 2 2
IRM S − I DC IRM S
⇒γ= 2
= 2
−1
IDC IDC
Im 2Im
Substituting: IRM S = √ , IDC =
2 π
v 
u Im2
u
u 2
⇒ γ = t 2  − 1
4Im
π2
r
π2
= −1
8 √
√
= 1.2337 − 1 = 0.2337 ≈ 0.483
⇒ %γ = 48.3%

Conclusion: The ripple content in the output is 48.3% of the DC component, i.e.,
IA C < IDC , hence it offers good rectification.

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6. Efficiency (η):
Efficiency is defined as the ratio of DC output power to AC input power:
Output DC Power PDC
η= =
Input AC Power PAC
2
IDC RL
= 2
IRM S (RS + 2Rf + RL )
2Im Im
Substitute: IDC = , IRM S = √
π 2
2Im 2


π
RL
⇒η=  2
Im
√
2
(RS + 2Rf + RL )
 2
4Im
π2
RL
= 2

Im
2
(RS + 2Rf + RL )
8 RL
= ·
π 2 RS + 2Rf + RL
RS + 2Rf RL
If ≪ 1, ⇒ ≈1
RL RS + 2Rf + RL
E
8
⇒η≈ ≈ 0.812
π2
TT
⇒ %η ≈ 81.2%

Conclusion: In a Full Wave Rectifier, ripple contents are lower, and hence, the
efficiency is higher.
NI

Advantages of Full Wave Rectifier (FWR)

ˆ DC load voltage and current are more than Half Wave Rectifier (HWR)
ˆ Efficiency is high
ˆ Provides large DC power output
ˆ Ripple factor is less
ˆ Widely used in regulated power supplies
1.7 Filter Circuits
The output from a half-wave or full-wave rectifier circuit isn’t a pure direct current (DC);
it contains unwanted fluctuations known as ripple. To reduce these ripples, filter circuits
are introduced. These filters are placed between the rectifier and the load to help smooth
the output is shown in Figure 1.17. Filter circuits are used at the output of rectifiers
to obtain ripple-free DC voltage. They minimize the ripples in the output as much as
possible. Two components used by the filter circuits are

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Figure 1.17: Filter Circuit

ˆ Inductor Filter: Blocks AC and allows DC to pass through. Hence, it is connected

in series with the load.

ˆ Capacitor Filter: Blocks DC and allows AC components to pass through. Hence,

it is connected in parallel with the load.

The inductor filter is not in use now a days as inductors are bulky, costly, and consume
more power, so they’re not commonly used anymore.

1.7.1 Bridge Rectifier with Capacitor Filter

E
TT
NI

Figure 1.18: Capacitor Filter

ˆ The capacitor charges to the peak value V during the diode conduction period and
m
delivers this energy during the non-conduction period to the load RL .

ˆ Charging time of the capacitor must be small so that it quickly reaches the peak
value. The discharging time must be large so that it slowly discharges until the
next peak.

ˆ During the positive half cycle of the AC supply, diodes D and D2 conduct and
1
charge the capacitor to the peak value Vm . They stop conducting when the trans-
former secondary voltage drops below Vm . This is because the capacitor voltage,
which is the cathode voltage of diode becomes more positive than anode.

ˆ So the capacitor then starts discharging through R , and the voltage across the
L
capacitor falls gradually.

ˆ The discharging of capacitor is decided by R C time constant which is very large

L
and hence capacitor discharges very little from Vm

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Figure 1.19: Capacitor Filter in Bridge Rectifier

ˆ In the next positive half cycle, when the transformer secondary voltage, becomes
more than the capacitor voltage, the diodes D3 and D4 becomes forward biased and
charges the capacitor C back to Vm

ˆ Due to short charging time and long discharging time, the ripples in the output
voltage are considerably reduced.
E
TT
NI

Figure 1.20: Bridge Rectifier with filter waveform

Time Constants

Charging time: T1 = 2Rf C

Discharging time: T2 = RL C

Output Voltage Variation

ˆ Without filter: 0 to V m

ˆ With filter: (V - V ) to V
m r m

This indicates that the parallel combination of RL and C significantly reduces the
ripple content in the output voltage.

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Ripple Factor with Capacitor Filter

ˆ For FWR: 1
γ= √
4 3f CRL
By selecting a large value of C, the output can be made smoother, thereby reducing
the ripple content.

1.8 Numerical on Rectifiers

1. A sinusoidal voltage of peak value 40V and frequency 50 Hz is applied to a HWR
without filter. It has a load RL = 800 Ω
Calculate:
a) Peak, DC and RMS value of Load current
b) DC output power
c) AC input power
d) Rectifier efficiency
Solution:
Given: Vm = 40 V, f = 50 Hz, RL = 800 Ω, Rf = 8 Ω
E
a) Peak value of the load current Im :
TT

Vm 40
Im = = = 49.5 mA
RL + Rf 800 + 8
NI

Im 49.5
IDC = = = 15.757 mA
π π

Im 49.5
Irms = = = 24.75 mA
2 2
b) DC power to load, PDC :
2
PDC = IDC · RL = (15.75 × 10−3 )2 × 800 = 198.45 mW

c) AC input power PAC :

2
PAC = Irms · (RL + Rf ) = (24.75 × 10−3 )2 · 808 = 494.95 mW

d) Efficiency η:
PDC 198.45
η= = = 0.4009
PAC 494.95

%η = 40.09%

2. An input to a HWR is v = 23 sin 314t. If Rf = 50 Ω and RL = 500 Ω, determine:

ˆ DC load voltage
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ˆ RMS load voltage

ˆ DC power delivered to the load
ˆ Rectification efficiency
Solution:
Given:
v = Vm sin ωt = 23 sin 314t, Rf = 50 Ω, RL = 500 Ω

DC Load Voltage:

Im Vm 23
IDC = , Im = = = 41.81 mA
π RL + Rf 50 + 500

41.81 mA
IDC = = 13.31 mA
π

VDC = IDC × RL = 13.31 mA × 500 = 6.65 V

RMS Load Voltage:

E
Im 41.81 mA
TT
Irms = = = 20.90 mA
2 2

Vrms = Irms × RL = 20.90 mA × 500 = 10.45 V

NI

DC Power Delivered to Load:

2
PDC = IDC × RL = (13.31 × 10−3 )2 × 500 = 88.57 mW

Rectification Efficiency:
2
PAC = Irms · (RL + Rf )

PAC = (20.90 × 10−3 )2 · (500 + 50)

PAC = 239.3mW

PDC 88.57
η= = = 0.37
PAC 239.3

%η = 37%

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3. In a full wave bridge rectifier, the transformer secondary voltage is

VS = 100 sin ωt

The forward resistance of each diode is Rf = 25 Ω and load resistance is RL = 950 Ω.

Calculate:

ˆ DC Output Voltage
ˆ Ripple Factor
ˆ Efficiency
Solution:
Given:
VS = Vm sin ωt, Vm = 100 V, Rf = 25 Ω, RL = 950 Ω

1. DC Output Voltage:

Vm 100 100
Im = = = = 100 mA
2Rf + RL
E 2 × 25 + 950 1000

2Im 2 × 100 mA
IDC = = = 63.66 mA
π π
TT

VDC = IDC × RL = 63.66 mA × 950 = 60.478 V

NI

2. Ripple Factor:

Im 100 mA
Irms = √ = √ = 70.71 mA
2 2

s 2 s 2
Irms 70.71 √ √
γ= −1= −1= 1.233 − 1 = 0.2337 = 0.4834
IDC 63.66

%γ = 48.34%

3. Efficiency:

PDC I 2 × RL
η= = 2 DC
PAC Irms × (2Rf + RL )

(63.66 × 10−3 )2 × 950 3.85

η= −3 2
= = 0.77
(70.71 × 10 ) × 1000 5

η = 77%

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4. A bridge rectifier uses 4 diodes with an RMS input voltage of 110 V. The forward
resistance of each diode is 25 Ω, and the load resistance is RL = 1 kΩ. Find:

ˆ Maximum value of current

ˆ DC value of current through the load
ˆ DC load voltage
Solution:
Given:
Vrms = 110 V, Rf = 25 Ω, RL = 1000 Ω

1. Find Vm :
Vm √ √
Vrms = √ ⇒ Vm = Vrms × 2 = 110 × 2 = 155.56 V
2

2. Maximum value of current Im :

Vm 155.56 155.56
Im = = = = 148.15 mA
2Rf + RL 2 × 25 + 1000 1050

3. DC value of current:
E
2Im 2 × 148.15 mA
TT
IDC = = = 94.36 mA
π π

4. DC load voltage:
NI

VDC = IDC × RL = 94.36 mA × 1000 = 94.36 V

5. Determine the ripple factor of a bridge rectifier using a capacitor [Link] load
used is 2 kΩ and DC output voltage is 12 V. Assume supply frequency of 50 Hz and
ideal diodes. A capacitor of 100 µF is used in the filter circuit.
Solution:
Given:
RL = 2 kΩ, VDC = 12 V, f = 50 Hz, C = 100 µF

Ripple factor for bridge rectifier with capacitor filter:

1
γ= √
4 3f CRL

Substituting the values:

1 1
γ= √ =
4 3 × 50 × 2 × 103 × 100 × 10−6 69.28

γ = 0.0144 ⇒ %γ = 1.44%

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6. Calculate the value of capacitor C that has to be used for the filter of a bridge
rectifier to get a ripple factor of 0.01. The rectifier supplies current to a load of
2 kΩ and the supply frequency is 50 Hz.
Solution:
Given:
γ = 0.01, RL = 2 kΩ, f = 50 Hz

1 1
γ= √ ⇒C= √
4 3f CRL 4 3f RL γ
Substituting the values:
1 1
C= √ = = 1.443 × 10−4 F
3
4 3 × 50 × 2 × 10 × 0.01 6928.203

C = 144.3 µF

1.9 Zener Diode E

TT
NI

Figure 1.21: Zener Diode Symbol

ˆ Zener diode is a special purpose diode; it is heavily doped compared to a junction

diode.

ˆ Zener diodes are designed for operation in the reverse breakdown region.
ˆ The zener diodes have breakdown voltage range from 3 V to 200 V.
1.9.1 VI Characterstics of Zener Diode
The forward and reverse baising of the zener diode is shown in the Figure 1.22. The VI
characterstics of the Zener is shown in Figure 1.23.

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Figure 1.22: Forward and Reverse baising of the Zener diode

E
TT
NI

Figure 1.23: VI Characteristics of the Zener diode

ˆ In the forward biased condition, As long as forward voltage is less than barrier
voltage, the current flowing is very small. As it increases beyond this voltage the
depletion region becomes very thin and current increases suddenly. This increase
in the current is exponential as shown in the Fig. 1.23.
ˆ When a narrow junction with a narrow depletion region is applied with a high
reverse voltage, due to the high electric field, electrons break away from the atoms.
Hence, electron hole pairs are generated in large numbers and a sudden increase of
current is ibserved. This ionization by electric field is known as Zener breakdown.
ˆ When a junction diode is reverse biased, there is normally a small amount of reverse
saturation current due to the minority charge carriers till the reverse voltage applied
is less than the reverse breakdown voltage.

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ˆ When the reverse voltage is sufficiently increased, the junction breaks down and a
large reverse current flows but the voltage across it remains almost constant.

ˆ Under this condition, the diode may be continuously operated in reverse breakdown.
ˆ Every zener diode has a capacity to carry current. As current increases, the power
dissipation PZ increases. If this dissipation increases beyond a certain value, the
diode may get damaged.

ˆ If the reverse current is limited by means of a suitably connected series resistor,

the power dissipation in the diode can be kept to a level that will not destroy the
device.

ˆ This property of breakdown may be useful in applications such as a voltage reference

source or voltage regulator.

Zener Parameters
ˆ Zener Breakdown Voltage (V ): Z
It is the voltage beyond which there is a sharp increase in current for a small change
in reverse voltage. It is the voltage across the Zener diode in the breakdown region.

ˆ Reverse Knee Current (I ZK ):

E
It is the Zener current corresponding to the knee region of the V-I characteristics.

ˆ Maximum Zener Current (I

TT

ZM ):
It is the maximum Zener current that can pass through the diode without damaging
the device.

ˆ Zener Test Current (I

NI

ZT ):
It is the standard test current used for checking the working condition of a Zener
diode.

ˆ Dynamic Resistance (r ): Z
It is the ratio of the change in reverse voltage to the corresponding change in reverse
current beyond the knee region.
∆VZ
rZ =
∆IZ

ˆ Maximum Power Dissipation (P D ):

It is given by the product of the Zener breakdown voltage and the maximum Zener
current:
PD = VZ × IZ max

Note: Many low power Zener diodes have a test current specified as IZT = 20 mA.

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1.9.2 Zener diode as a Voltage Regulator

ˆ Voltage regulators are devices used to maintain constant voltage across a load irre-
spective of fluctuations in the input voltage and load currents.

ˆ After rectification, the voltage is pulsating DC with ripples those are unwanted
fluctuations.

ˆ A filter circuit helps smoothen this, reducing ripple. But it doesn’t completely
eliminate it, so the result is unregulated DC.

ˆ To achieve smooth and stable output, a regulator circuit is added after the filter.
It:

– Minimizes remaining ripple,

– Keeps the output voltage constant even if input voltage or load conditions
change.

ˆ The output of the regulator is called DC supply.

ˆ Zener diodes are widely used as voltage regulators to regulate the voltage across
small loads.

ˆ Zener diodes have a sharp reverse breakdown voltage, which remains nearly constant
E
over a wide range of currents.
TT

ˆ They can produce a stabilized output voltage with low ripple under varying load
current conditions.

Working of Zener diode voltage Regulator:

NI

Figure 1.24: Zener Volatge Regulator

ˆ The Zener diode is connected with its cathode terminal to the positive terminal of
the DC supply, hence it is reverse biased and operates in breakdown region. The
large current flows through the zener diode. Under this condition the voltage across
the zener is constant and is equal to Vz .

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ˆ A resistor R is connected in series with the Zener diode to limit the maximum
s
current in the circuit.

ˆ As the voltage across the zener diode remains constant, equal to V , it is connected
Z
across the load, and hence the load voltage Vo is equal to the zener voltage VZ .

ˆ Zener current must remain above I for voltage stabilization.

Z(min)

ˆ I depends on the Zener’s power rating.

Z(max)

Case 1: No Load Condition (IL = 0)

ˆ The load current is zero, so the entire current flows through the Zener diode (I = I ) Z

Vin − VZ
I= = Iz
RS

ˆ The diode dissipates maximum power.

ˆ R must be chosen to keep power dissipation within safe limits.
s

Case 2: With Load Condition (IL ̸= 0)

E
1. Regulation with Varying line voltage:

ˆ Load R is connected in parallel with the Zener diode.

TT
L

ˆ The voltage across R is equal to Zener voltage.

L

Vo = VZ is constant.
NI

Vo VZ
∴ IL = = = constant
RL RL
And
Vin − VZ
I= = IZ + IL
RS
ˆ Now if V increases, then the total current I increases. But IL is constant
in
as VZ is constant. Hence, the current IZ increases to keep IL constant.

ˆ But as long as I is between IZmin and IZmax , the VZ , i.e., output voltage Vo , is
Z
constant. Thus, the changes in input voltage get compensated and the output
is maintained constant.

ˆ Similarly, if Vdecreases, then current I decreases. But to keep IL constant,

in
IZ decreases. As long as IZ is between IZmax and IZmin , the output voltage
remains constant.

Key Note:

2. Regulation with Varying Load:

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ˆ The input voltage V in is constant, and the output voltage Vo across the load is
also constant due to the Zener diode maintaining a fixed voltage VZ . Assuming
the series resistance Rs is constant, the total current I through Rs remains
constant.
Vin − VZ
I= (constant) = IL + IZ
RS
Where:
– I is the total current through the resistor Rs
– IL is the load current through RL
– IZ is the current through the Zener diode
ˆ As the load resistance R decreases, the load current I increases. The
L L
voltage V is constant. Hence, the current I decreases to keep I constant.
Z Z

ˆ But as long as I is between I and I , the V , i.e., output voltage V , is

E
Z Zmin Zmax Z o
constant. Thus, the changes in input voltage get compensated and the output
TT

is maintained constant.
ˆ Similarly, if the load resistance R increases, the load current IL decreases.
L
The voltage VZ is constant. Hence, the current IZ increases to keep I constant.
NI

As long as IZ is between IZmax and IZmin , the output voltage remains constant.

Key Note:

1.10 Numerical on Zener Diode

1. A 24 V, 600 mW zener diode is used for providing a 24 V stabilized supply to a
variable load from a 32 V supply. Calculate:

(a) Value of series resistance required

(b) Zener current when the load is 1200 Ω

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Figure 1.25: Problem 1

Given:

VZ = 24 V
PZ = 600 mW = 0.6 W
VS = 32 V

(i) Value of Series Resistance RS

E
When the load is disconnected (RL = ∞), i.e., IL = 0, then:
TT
Is = IZ + IL = IZ + 0 = IZmax

PZ 600 × 10−3
IZmax = = = 25 mA
VZ 24
NI

Applying KVL:
VS − IS RS − VZ = 0

Substituting values:
32 − 24 8
32 − (25 × 10−3 )RS − 24 = 0 ⇒ RS = −3
= = 320 Ω
25 × 10 0.025

Therefore, the value of series resistance is RS = 320 Ω .

(ii) Zener Current when Load is RL = 1200 Ω

We know:
VZ 24
VZ = VO = VL = IL · RL ⇒ IL = = = 0.02 A = 20 mA
RL 1200

Load current is IL = 20 mA.

Now,
IZ = IS − IL = 25 mA − 20 mA = 5 mA

Therefore, the zener current when the load is 1200 Ω is IZ = 5 mA .

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Figure 1.26: Problem 2

2. For the circuit shown, calculate the zener diode current and the power dissipation.
Given:

Vin = 15 V
VZ = 5.2 V
R1 = 670 Ω

Solution: Applying KVL,

E −IZ R1 − VZ + Vin = 0

Vin − VZ 15 − 5.2
⇒ IZ = = = 14.6268 mA
TT
R1 670
Power Dissipation:

PD = VZ · IZ = 5.2 × 14.6268 × 10−3 = 76.059 mW

NI

Answer:
Zener current IZ = 14.6268 mA
Power dissipation PD = 76.059 mW

3. A circuit has a zener diode connected across the load with the following details.
Find the source current I, the load current IL , and the zener power dissipation PZ .

Figure 1.27: Problem 3

Given:

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ˆ Source voltage, V = 20 V
in

ˆ Series resistance, R = 300 Ω

ˆ Zener voltage, V = 10 V
Z

ˆ Load resistance, R = 1 kΩ = 1000 Ω

L

To find: I, IL , and zener power dissipation PZ

Solution
Applying KVL to the input loop:

Vin − IRS − VZ = 0
20 − 10 10
20 − I · 300 − 10 = 0 ⇒ I = = = 0.033 A = 33 mA
300 300
Load current:
VZ 10
VL = VO = IL RL = VZ ⇒ IL = = = 0.01 A = 10 mA
E RL 1000

Power dissipation across Zener:

PZ = VZ · IZ = 10 · 22 × 10−3 = 220 mW
TT

4. In the circuit shown in Figure 1.28 determine,

a) the load current
NI

b) the zener current

c) power dissipated in zener diode

Figure 1.28: Problem 4

Solution
Given: Vi = 18 V, RS = 270 Ω
Vz = 10 V, RL = 1 kΩ

Source Current:
Vi − Vz 18 − 10
IS = = = 29.62 mA
RS 270

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(a) Load current

Vz 10
IL = = = 10 mA
RL 1 × 103
(b) Zener current
IS = IZ + IL ⇒ IZ = IS − IL
IZ = 29.62 × 10−3 − 10 × 10−3 = 19.62 mA
(c) Power dissipated in zener diode

PZ = VZ · IZ = 10 × 19.62 × 10−3 = 196.2 mW

E
TT
NI

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Chapter 2

Transistors and their Applications

2.1 Introduction of Bipolar junction transistors (BJT)

ˆ BJT is a three-terminal device constructed using doped semiconductor materials.
ˆ It is mainly used in amplifying and switching applications.
ˆ It is called bipolar because both holes and electrons take part in the conduction
of current.

ˆ The three terminals of a BJT are:

E
TT
– E: Emitter
– B: Base
– C: Collector

ˆ Two junctions present in a BJT are:

NI

– B–E junction (Base–Emitter)

– C–B junction (Collector–Base)

Types of Transistors
1. NPN transistor: A P-type semiconductor material is sandwiched between two
N-type materials.

2. PNP transistor: An N-type semiconductor material is sandwiched between two

P-type materials.

Junction representations of NPN and PNP transistors with terminals can be illus-
trated in Figure 2.1 using circuit diagrams or symbolic representations.

ˆ Emitter: It is highly doped and is the supplier of electrons (in NPN transistor).
ˆ Base: It is thin and lightly doped.
ˆ Collector: It is moderately doped and large in size. It collects the electrons emitted
by the emitter (in NPN transistor).

41
 Basic Electronics

Figure 2.1: Types of Transistor

Transistor symbols:

Figure 2.2: Transistor Symbols

ˆ The arrow indicates the emitter terminal of the transistor.

E
It also indicates the
conventional direction for the current flow (P to N).
TT

ˆ In NPN transistor the arrowhead points outwards from base to emitter.

ˆ In PNP transistor the arrowhead points inwards for emitter towards the base.
NI

2.1.1 NPN Transistor Operation

Unbiased Transistor
An unbiased transistor means a transistor with no external voltage (biasing) is applied.
There will be no current flowing from any of the transistor leads. Since a transistor is
like two pn junction diodes connected back to back, there are depletion regions at both
the junctions, emitter junction and collector junction, as shown in the Figure 2.3.

Figure 2.3: Unbiased Transistor

During diffusion process, depletion region penetrates more deeply into the lightly
doped side in order to include an equal number of impurity atoms in each side of the

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junction. As shown in the Figure 2.3, depletion region at emitter junction penetrates less
in the heavily doped emitter and extends more in the base region. Similarly, depletion
region at collector junction penetrates less in the heavily doped collector and extends more
in the base region. As collector is slightly less doped than the emitter, the depletion layer
width at the collector junction is more than the depletion layer width at the emitter
junction.

Operation of NPN Transistor with Biasing

E
Figure 2.4: Baised Transistor
TT

ˆ Emitter and collector are heavily doped, whereas the base is lightly doped.
ˆ The figure shows an NPN transistor with external bias voltages applied.
ˆ The emitter-base (E–B) junction is forward biased by an external DC source. This
NI

reduces the barrier voltage and causes electrons in the N-type emitter to flow toward
the P-type base. As a result, the depletion region at the E–B junction becomes
narrow.
(Electrons are emitted into the base region, hence the name emitter, and the
resulting current is called emitter current IE .)

ˆ The collector-base (C–B) junction is reverse biased by the external DC source. This
increases the barrier voltage and widens the C–B depletion region.

ˆ Electrons flow from the emitter through the P-type base and combine with holes
in the base. Since the base region is thin and lightly doped, only a few electrons
recombine with holes to form the base current IB .

ˆ The remaining electrons reach the C–B depletion region and are drawn across the
junction by the external DC bias supply. These electrons are collected in the col-
lector region, giving rise to the collector current IC .

ˆ Thus, electron current is dominant in an NPN transistor.

ˆ Since approximately 98% of the electrons from the emitter flow into the collector
circuit and only a few recombine in the base, the base current is small and the
collector current is large.

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2.1.2 BJT Voltages and Currents (NPN)

Terminal Voltages

Figure 2.5: Transistor Currents and Voltages

ˆ The direction of the arrowhead indicates the conventional current direction.

ˆ For an NPN transistor, the base is biased with a positive voltage with respect to
the emitter.

ˆ The collector is biased with a higher positive voltage than the base.
E
ˆ In the figure, V is the base bias voltage connected through R , and the collector
TT
BB B
supply VCC is connected through RC .

ˆ The negative terminals of both sources are connected to the emitter terminal.
ˆ To ensure the collector-base junction is reverse biased, V > V (i.e., positive on
NI

CC BB
collector and negative on base).

Note:

ˆ Typical base-emitter voltages: 0.3 V for germanium, 0.7 V for silicon.

ˆ Typical collector voltages: 3 V to 20 V.
Transistor Currents (NPN)
ˆ For an NPN transistor, I B and IC flow into the device (conventional current), and
IE flows out.

ˆ The current relationship is:

IE = IB + IC

ˆ Electrons are the majority carriers and move opposite to the conventional current
direction.

ˆ Low-power transistors: I C = 1 mA to 20 mA.

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ˆ High-power transistors: I C = 100 mA to several amperes.

Nearly 96% to 99% of IE flows across the collector-base junction to become collector
current IC .

ˆ Common-base current gain:

IC = αIE

Where, α is the emitter to collector current gain. It is also referred to as

common base current gain. It is the ratio of collector current to emitter current,
IC
α= , typically α ∈ [0.96 to 0.99]
IE
Hence, the collector current is almost equal to emitter current. In many circuits, it
is assumed that IC ≈ IE .
Leakage current: Since CB junction is reverse biased, very small reverse sat-
uration current ICBO flows across the junction. It is known as collector to base
leakage current.

ˆ Common-emitter current gain:

E
IC = βIB
TT
IC
β= , typically β ∈ [25 to 300]
IB
Where, β is the base to collector current gain. t is also referred to as common
emitter current gain. It is the ratio of collector to base current.
NI

2.1.3 Relation between α and β:

IE = IC + IB (1)

and
IC IC
α= , β=
IE IB

IC = αIE (2)
Substituting 1 in 2,
IC = α(IC + IB )

IC − αIC = αIB
IC (1 − α) = αIB
IC α
=
IB 1−α
α
∴ β=
1−α

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Also,
α
β=
1−α
or β(1 − α) = α
β − βα = α
β = α + βα
= (1 + β)α
β
∴ α=
1+β

2.2 Numerical on Transistor Currents and Current

Gain
1. Calculate IC and IE for a transistor that has α = 0.98 and IB = 100 µA. Determine
the value of β for the transistor.
Solution:
α 0.98 0.98
β=
E = = = 49
1−α 1 − 0.98 0.02
IC = β · IB = 49 × 100 × 10−6 = 4.9 mA
TT

IE = IC + IB = 4.9 mA + 0.1 mA = 5 mA

2. Calculate α and β for IC = 1 mA and IB = 25 µA. Determine new IB for IC = 5 mA.

Solution:
NI

IC 1 mA
β= = = 40
IB 25 µA
IE = IC + IB = 1.025 mA
IC 1
α= = ≈ 0.976
IE 1.025
IC 5 mA
IBnew = = = 125 µA
β 40
3. Determine β and IE for IB = 50 µA and IC = 3.65 mA.
Solution:
IE = IC + IB = 3.65 mA + 0.05 mA = 3.70 mA
IC 3.65
β= = = 73
IB 0.05
4. Given IC = 3 mA and IE = 3.03 mA, find β. Determine new IC if β = 70.
Solution:
IB = IE − IC = 3.03 mA − 3 mA = 0.03 mA = 30 µA
IC 3
β= = = 100
IB 0.03
ICnew = β · IB = 70 × 30 × 10−6 = 2.1 mA

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5. Find IC and IE for α = 0.99 and IB = 20 µA.

Solution:
α 0.99
β= = = 99
1−α 0.01
IC = β · IB = 99 × 20 × 10−6 = 1.98 mA
IE = IC + IB = 1.98 mA + 0.02 mA = 2 mA

2.3 Transistor Characteristics

The graphs showing the relationship between different currents and voltages of a transistor
are known as the characteristics of the transistor.

Types of Characteristics
ˆ Input Characteristics
ˆ Output Characteristics
Any transistor circuit can be designed using three types of configurations, based on
the connection of transistor terminals:
E
ˆ Common Emitter Configuration (CE)
TT

ˆ Common Base Configuration (CB)

ˆ Common Collector Configuration (CC)
NI

Each configuration has its own characteristic curves.

2.3.1 Common Emitter Configuration (NPN)

In this configuration, the emitter terminal is common to both input and output terminals
as shown in Figure 2.6.

Figure 2.6: CE Configuration of NPN transistr

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ˆ Input is applied between the base-emitter (B–E) terminals, and output is taken
between collector-emitter (C–E) terminals.

ˆ This configuration is widely used as an inverting amplifier.

ˆ It introduces a phase shift of 180 at the output.
◦

ˆ The B–E junction is forward biased and the C–B junction is reverse biased using
supplies VBB and VCC .

ˆ The negative terminal of V repels electrons in the emitter, causing current to

BB
flow from emitter to base and then to collector.

ˆ Input current: IB, Output current: IC , and IE = IB + IC

Input Characteristics
Input characteristics are obtained by plotting input current IB versus input voltage VBE
at constant output voltage VCE .

E
TT
NI

Figure 2.7: Input Characteristics of CE Configuration

ˆ When V CE is constant, after the cut in voltage, the base current (IB ) increases
rapidly with a small increase in the VBE . This means that dynamic input resistance
is small in the CE configuration.

ˆ Dynamic input resistance is defined as the ratio of change in base-emitter voltage

to change in base current at constant VCE :
∆VBE
ri = (with VCE constant)
∆IB

ˆ For a fixed value V BE ,

IB decreases as VCE is increased. Alarger value of VCE
results in a large reverse bias at collector-base PN junction. This increases the

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depletion region and reduces the effective width of the base. Hence, there are fewer
recombinations in the base region, reducing the base current IB .

ˆ This shifts the input characteristic curves to the right.

Output Characteristics
Output characteristics are obtained by plotting output current IC versus output voltage
VCE at constant input current IB .

E
TT
Figure 2.8: Output Characteristics of CE Configuration

ˆ Even with constant I , I increases slightly with V , making the slope.

B C CE

ˆ If V exceeds a certain limit, the C–B junction breaks down, causing I

NI

CE C to rise
rapidly—this is the breakdown region.

ˆ For the fixed value of V CE , the ratio of small change in Ic , ∆IC to small change in
IB , ∆IB , then β is:
∆IC
β=
∆IB
ˆ From the output characteristics, the change in collector emitter voltage( ∆V CE )
causes little change in the collector current(∆IC ) for constant base current IB .
Thus, the output dynamic resistance is high in CE configuration,
∆VCE
ro = (with IB constant)
∆IC

ˆ The output characterstics of common emitter configuration consists of three regions:

– Active Region: As VCE is increased, reverse bias increases. This causes the
depletion region to spread more in the base region than in the collector, re-
ducing the chances of recombination in the base. This causes collector current
IC to rise more sharply with increasing VCE . B–E junction is forward biased,
C–B junction is reverse biased. A transistor acts as an amplifier.

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– Saturation Region: If the VCE is reduced, the CB junction becomes forward

biased, since the EB junction is already forward biased, IC also decreases
rapidly. Here both the junctions are forward biased. A transistor acts as a
closed switch.
– Cut-off Region: When the input base current is made equal to zero, the IC
is the small leakage current. Here, both junctions are reverse-biased biased
and hence no current flows through the transistor. A transistor acts as an
open switch.

ˆ In the active region, the CB junction is reverse biased. If the VCE is excedes the
maximum limit, width of the depletion region at the CB junction increses such that
it penatrates into the base until it makes contact with EB depletion region. This
condition is called punch through effect. When this situation occurs, breakdown
of transitor occurs. That is large IC flows and which distroys the transistor.

2.4 CE-RC Coupled Amplifier (Single Stage)

Single-stage Common Emitter (CE) RC coupled amplifiers are designed to improve the
strength of weak signals for further amplification.
E
TT
NI

Figure 2.9: Single Stage Common Emitter RC Coupled Amplifier

Significance of the each Components

ˆ Input Coupling Capacitor C : C 1 1 Couples the small signal AC, Vs to the base
of the transistor. Blocks DC and allows only AC to pass, preventing external DC
from affecting the transistor’s biasing. If the C1 is not connected, then the Rs is in
parallel with R2 . This will reduce the bias voltage at the transistor base and alter
the collector current. To avoid this and maintain the stability of bias condition
coupling capacitors are connected.

ˆ Biasing Circuit (R , R 1 2 and RE ): The R1 and R2 provides necessary base bias

using a voltage divider network to operate the transistor in the active region. It sets
the proper operating point for the CE amplifier. The RE provides bias stabilization.

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ˆ Emitter Bypass Capacitor C E:

Connected in parallel to RE , it offers a low-
resistance path to the amplified AC signal, thereby increasing the gain.
Note: Without CE , the amplified signal passes through RE , causing a large voltage
drop and reducing output voltage and gain.

ˆ Output Coupling Capacitor C : Connected at the collector to block DC and

2
pass AC to the load or next stage. If the RL is connected directly to the output
without connecting the C2 , the DC levels of VCE and Vc will change. To avoid this
Coupling capacitors are used at the output.

Phase Reversal Concept

ˆ During the positive half cycle of the input signal V , the AC and DC voltages
s
add together, increasing the forward bias across the base-emitter (B-E) junction.
This leads to an increase in base current IB . Consequently, the collector current
increases as:
IC = βIB
The increase in IC causes an increase in the voltage drop across RC .

ˆ Since the collector voltage is given by:

E
VC = VCC − IC RC
TT
An increase in IC increases IC RC , causing VC to decrease (i.e., move in the negative
direction).

ˆ During the negative half cycle of the AC input signal V , the AC and DC voltages
s
NI

oppose each other, reducing the forward bias across the B-E junction. As a result,
the base current IB decreases, which also reduces the collector current IC .

ˆ The reduction in I C decreases the voltage drop IC RC across RC . Since:

VC = VCC − IC RC

For a fixed VCC , when IC RC reduces, the collector voltage VC increases (moves in
the positive direction).

Thus, as Vs increases in the positive direction, the collector voltage VC moves in the
negative direction. Hence, we obtain a negative half cycle of the output voltage for a
positive half cycle at the input.
Similarly, a positive half cycle is observed at the output for a negative half cycle
at the input. Therefore, we conclude that there exists a 180◦ phase shift between the
input and output voltages in a CE amplifier, making it an inverting amplifier.

2.5 Transistor as a Switch

A transistor can be made to operate as an ON/OFF switch.

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Figure 2.10: Transistor as Switch

Case 1: Cut-off State (Open Switch)

When base voltage VBB = 0V , both the EB and CB junctions are reverse biased. No base
current IB flows. Hence, IC = 0. Therefore, the collector (C) and emitter (E) terminals
are open-circuited.
Output collector voltage: VO = VCC

Therefore, the transistor is in the cut-off state.

E
TT

Case 2: Saturation State (Closed Switch)

When a higher level of base voltage VBB is applied, both EB and CB junctions are forward
biased. A large base current IB flows due to +VBB which makes the collector current
NI

reach saturation level. Hence, collector (C) and emitter (E) terminals are short-circuited.
Output collector voltage: VO = 0V
Saturation current:
VCC − VCE
IC(sat) =
RC

Therefore, the transistor is in the saturation state.

2.6 Field Effect Transistor

ˆ Field Effect Transistor known as FET is a 3-terminal semiconductor device in which
current flow is only due to one of the two kinds of charge carriers namely electrons
or holes. Hence, it is a unipolar device.

ˆ BJT is a current controlled device (I Bcontrols IC in CE configuration) while FET

is a voltage controlled device (input voltage controls output current).

ˆ FET construction is simple compared to BJT and uses less area in an integrated
circuit (IC). It is less noisier than BJT.

ˆ Low power consumption and are used in MOS circuits.

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 Basic Electronics

ˆ Input resistance is high compared to BJT.

Two Types of FETs are:
1. Junction Field Effect Transistor (JFET)
2. Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

1. JFET
ˆ n-channel JFET
ˆ p-channel JFET
2. MOSFET
ˆ Depletion type
– n-channel
– p-channel
ˆ Enhancement type E
– n-channel
– p-channel
TT

2.6.1 N channel Enhancement Type Metal Oxide Semiconduc-

tor (N-EMOSFET)
NI

(a) Structure (b) Symbol

Figure 2.11: N-EMOSFET

Basic Construction
ˆ A slab of p-type material is formed from a silicon base and is referred to as substrate.
The substrate is internally connected to the source terminal.

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ˆ The source and drain terminals are connected through metallic contacts to the
n-doped regions. There is an absence of channel between the two n-doped regions.

ˆ SiO layer is present to isolate the gate metallic platform from drain and source
2
terminals.

Drain and Trnasfer Characteristics of n-channel MOSFET

ˆ If V is set to 0V and a positive voltage is applied between drain and source
GS
terminals, the absence of an n-channel will result in a current of zero mA.

ˆ Both V GS and VDS are set at some positive voltage greater than zero volts.
This establishes a positive potential between the drain and gate with respect to the
source.

ˆ The positive potential at the gate will pressure the holes in the p-substrate along
the edge of SiO2 layer to leave the area and enter deeper regions of the p-substrate,
as in Figure 2.12.

E
TT
NI

Figure 2.12: Channel formation in the NEMOSFET

ˆ The electrons (minority carriers) in the p-substrate will be attracted to the positive
gate and accumulate in the region near the surface of the SiO2 layer.

ˆ The SiO layer and its insulating qualities will prevent the electrons from being
2
absorbed by the gate.

ˆ As V increases in magnitude, the concentration of electrons near the SiO2 surface

GS
increases until it can control the flow of current between drain and source.

ˆ The level of V
GS that results in significant increase in drain current is called as
threshold voltage VT .

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ˆ Since the channel is non-existent with VGS = 0V and is enhanced by the application
of positive gate-to-source voltage, this type of MOSFET is called an enhancement
type MOSFET.

ˆ The Figure 2.13 shows the drain characteristics of an N channel enhancement type
MOSFET. Here, as VGS is increased beyond the threshold level VT , VGS > VT , the
density of free carriers in the induced channel will increase, resulting in increased
drain current ID .

E
TT
NI

Figure 2.13: Drain Characteristics of the N-EMOSFET

ˆ If V GS is held constant, and VDS is increased, the drain current ID increases in the
initial portion of the curve, and this region is called Ohmic region. As the VDS
is further increased ID reaches a Saturation level. At this condition, pinching off
occurs.

ˆ When saturation occurs, the channel becomes narrow toward the drain, as shown
in Figure 2.14.

ˆ With V GS held constant and VDS increased, the gate-to-drain voltage VGD will drop.
So, the gate will be less and less positive with respect to the drain.

ˆ This reduction in gate-to-drain voltage causes a reduction in channel width. Hence,

the channel will be reduced to a point of pinch-off and a saturation condition will
be established.
Saturation Condition:
VDS(sat) = VGS − VT

ˆ When V DS is less than VT , the drain current drops to zero and hence the device
shifts to Cut off region.

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Figure 2.14: Change in channel and depletion in MOSFET

E
TT
NI

Figure 2.15: Transfer Characteristics of the NEMOSFET

The Figure 2.15 shows the Transfer characteristics of the MOSFET.

ˆ For V GS < VT , ID = 0 mA

ˆ For V GS > VT , ID depends on VGS and is applied by a nonlinear relation:

ID = K(VGS − VT )2
Where,
K is a constant = 0.278 × 10−3 A/V2

ID(ON)
K=
(VGS − VT )2

2.7 CMOS Inverter

ˆ CMOS → Complementary MOS. It uses two E-MOSFETs for its construction.
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ˆ A P-channel and N-channel E-MOSFET when placed on the same substrate is

known as Complementary MOS.

ˆ It has low input impedance, fast switching speeds and low power consumption.
ˆ It is used in computer logic design.
ˆ One N-type MOS (NMOS) and one P-type MOS (PMOS) are connected in pairs
to form CMOS.

ˆ Gates of the two devices are connected to form the input terminal, and the two
drain terminals are connected together to form the output terminal, as shown in
Figure 2.16.

E
TT
NI

Figure 2.16: CMOS Inverter

Case 1: When Vin = 5V (State 1)

VGS2 = Vin − VDD = 5 − 5 = 0V

Hence, PMOS is non-conducting or OFF (open circuited). It offers high resistance.

VGS1 = Vin − VG = 5 − 0 = 5V
Therefore, for VGS1 = 5V, NMOS is conducting or ON (short circuited to ground).
It offers low resistance.
NMOS is ON with low resistance. Hence,

Vout = 0V (State 0)

Case 2: When Vin = 0V (State 0)

VGS2 = 0 − 5 = −5V
For negative gate voltage, PMOS is ON and acts as a closed switch. It conducts and
offers low resistance.

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VGS1 = 0 − 0 = 0V
NMOS is non-conducting for VGS1 = 0V.
Hence, it is OFF and open circuited. It offers high resistance.

∴ PMOS is ON with Vout = 5V (State 1)

E
TT
NI

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Chapter 3

Op-Amp & Linear IC Applications

3.1 Introduction
ˆ Operational amplifiers, also known as op-amps, are voltage amplifying device de-
signed to be used with components like capacitors and resistors between input and
output terminals.

ˆ They are high gain amplifiers consisting of one or more differential amplifiers.
ˆ They are often used in signal conditioning, filtering and operations (mathematical)
E
such as addition, subtraction, multiplication, integration and differentiation.

ˆ OP-Amps are the most useful device in analog electronic circuitry. With only a few
TT

external components it can be made to perform a variety of analog signal processing

tasks. It can amplify both AC and DC input signals.
NI

3.2 History
ˆ In 1963, the first monolithic integrated circuit (IC) or Op-Amp IC was introduced.
It was µA702 from Fairchild semiconductors – designed by an engineer Bob Widlar.

ˆ In 1968, some of the instability issues in µA709 were resolved and the IC was re-
introduced by the name as µA741. It is a widely used IC for many applications.
Here µA  (micro amperes).

ˆ Op-Amp is a very high gain negative feedback amplifier that can amplify signals
having wide range of frequencies.

ˆ With the addition of suitable external feedback components, Op-Amps can also
be used for variety of applications such as signal amplification, filter, oscillators,
regulators, comparators etc.

59
 Basic Electronics

IC Diagram:

Figure 3.1: 8 pin IC package of µA741 Op-Amp

Schematic symbol of Op-Amp:

E
TT
NI

Figure 3.2: Schematic symbol

ˆ Figure 3.2 shows the schematic symbol of Op-Amp. It has two inputs and one
output terminal. The input with positive sign is called as non-inverting terminal
and that with negative sign is called as inverting terminal.
ˆ +V and −V are DC power supply terminals.
CC EE

ˆ The output voltage V is in phase with input if the signal is connected to the non
o
inverting terminal is shown in Figure 3.3. The output voltage Vo is out of phase
with the input if the signal is connected to the inverting terminal is shown in Figure
3.4.

Figure 3.3: Inverting amplifier

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Figure 3.4: Non-Inverting amplifier

Equivalent circuit of an Op-Amp:

E
TT

Figure 3.5: Equivalent Circuit of Op Amp

In the above equivalent circuit, the output voltage Vo is given by

NI

Vo = Ad (V1 − V2 ) (1)
Vo = Ad Vd
ˆ where, V d is the differential input voltage, V1 is the voltage at the non-inverting
terminal w.r.t ground and V2 is the voltage at the inverting terminal w.r.t ground.
Ad is the differential gain of an Op-Amp. It is given by
Vo
Ad =
Vd
ˆ In equation 1, output voltage V o is directly proportional to the difference between
the two input voltages. i.e., Op-Amp amplifies the difference between the two input
voltages. The polarity of Vo depends on the polarity of the difference voltage Vd
(open loop gain).
ˆ A graph of V verses V is plotted as shown in Figure 3.6 by keeping A as constant.
o d d

ˆ It can be seen that the output voltage V cannot exceed the positive and negative
o
saturation voltages +VCC and –VEE .
ˆ Hence, the output voltage V o is directly proportional to the difference input voltage
Vd until it reaches the saturation voltages and later it remains constant as shown
in the transfer characteristics of Op-Amp in Figure 3.6.

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Figure 3.6: Transfer characteristics

Since open loop gain Ad is very large, a small difference input voltage Vd will produce
a large swing as the output voltage that may reach ±Vsat (+VCC , −VEE ).

3.3 Op-Amp Parameters:

1. Common Mode Rejection Ratio (CMRR): CMRR is defined as the ratio of
the differential gain Ad to the common mode gain AC .
E Ad
CMRR, ρ =
Ac
TT

When the same input voltages are applied to both input terminals of a differential
amplifier, it is said to be operating in common mode configuration. Many distur-
bance signals, noise signals appear as a common input signal to both the input
terminals of the differential amplifier. Such a common signal should be rejected
NI

by the differential amplifier. The ability of a differential amplifier to reject a com-

mon mode signal is expressed by a ratio called Common Mode Rejection Ratio .

Figure 3.7: CMRR

[Note: Common mode gain(Ac ): When two input signals applied as inputs to
an Op-Amp are equal, then the output voltage VO =(V1 − V2 ) must be zero for an
ideal Op-Amp. But the output voltage of a practical differential amplifier not only
depends on difference voltage, but also depends on average common level of two
input voltages. Such an average level of two input voltages is called as common

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mode voltage VC .
V1 + V 2
VC =
2
The output voltage due to common mode voltage is VO =AC VC . The common mode
gain is given by
VO
AC =
VC
Hence, there exists some finite output for V1 =V2 due to common mode gain AC in
case of practical differential amplifiers.]

Ideally, the common mode voltage gain is zero, hence the ideal value of CMRR is
infinite. For a practical differential amplifier, Ad is large and Ac is small, hence the
value of CMRR is also very large. Since CMRR is very large, it can be expressed
in dB as
Ad
CMRR in dB = 20log10 dB
Ac

2. Input bias current (IB ): It is the average value of the current that flows into the
inverting and non-inverting input terminals of an Op-Amp as shown in Figure 3.8.
E
TT
NI

Figure 3.8: Input bias currents

Input bias current is given by,

IB1 + IB2
IB =
2
3. Input offset current (Iio ): It is the algebraic difference between the currents
flowing into inverting and non inverting terminals of an Op-Amp. It is given by
Iio = |IB1 − IB2 |

4. Input offset voltage (Vio ) : Whenever both the input terminals of the op-amp are
grounded, ideally, the output voltage should be zero. However, in this condition,
the practical op-amp shows a small non zero output voltage. To make this output
voltage zero, a small voltage in millivolts is required to be applied to one of the
input terminals. Such a voltage makes the output exactly zero. It is the voltage
that must be applied between the two input terminals such that the output voltage
becomes zero. This is shown in Figure 3.9

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Figure 3.9: Input offset voltage

5. Input impedance (Ri ): It is the equivalent resistance that can be measured at

either the inverting or non inverting terminal with the other terminal connected to
ground.

6. Output impedance (Ro ): It is the equivalent resistance that can be measured

between the output terminal of an op-amp and the ground.

7. Slew rate (S): It is defined as maximum rate of change of output voltage per unit
time. It is given by
dVo
Slew rate = V /µsec
dt
E
Slew rate indicates how fast the output of an OP-Amp can change in response to
changes in the input signal frequency.
TT

3.4 Ideal Op-Amp Characteristics

NI

1. Infinite voltage gain (AOL ): It is the differential open loop gain of an op-amp.
We know that,

Vo = A (V1 − V2 )
Vo
= (V1 − V2 ) ,
A
if, V1 = V2 ,
Vo
then, = 0,
A
Vo
this implies, = A = ∞ = AOL .
0

2. Infinite input impedance (Ri ): An ideal op-amp does not draw any current at
both input terminals.

i.e, I1 = I2 = 0
Vi Vi
Ri = = =∞
Ii 0
Thus, the ideal op-amp open-loop voltage gain is infinity. Thus, its input impedance
is infinity. This ensures that no current flows through the terminals of an ideal
op-amp.

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3. Zero Output impedance (RO ): In an ideal op-amp, the output voltage remains
constant regardless of the current drawn by the load. This is represented by a zero
output impedance.

4. Zero Input offset voltage (Vio ): The input offset voltage is the differential voltage
required between the input terminals to make the output voltage zero. For an ideal
op-amp, Vio is zero.

5. Zero Input offset current (Iio ): The input offset current is the difference between
the currents flowing into the inverting and non-inverting input terminals when the
output voltage is zero. For an ideal op-amp, this difference is zero.

If IB1 = IB2 = 0,
then, Iio = |IB1 − IB2 | = 0

6. Zero Input bias current (IB ): It is the small DC current that flows into or out
of the input terminals to bias the internal circuit. For an ideal op-amp it is zero.

if IB1 = IB2 = 0,
IB1 + IB2
then, IB = = 0.
E 2
TT
7. Bandwidth (BW): Bandwidth is the range of frequencies over which the output
of op-amp is constant. For an ideal op-amp bandwidth (BW) is infinity.

8. CMRR: The ratio of differential gain Ad to common mode gain AC is defined as

CMRR.
NI

Ad
i.e., CMRR =
Ac
if Ac = 0,
Ad
then, CMRR = =∞
0
This implies that an ideal op-amp ensures zero common mode gain (AC = 0)

9. Slew rate Higher the Slew rate, better is the performance of the OP-Amp. Ideally,
slew rate is ∞.

3.5 Practical values:

ˆ Voltage gain (A )=2 × 10
OL
5

ˆ Input impedance (R ) = 2 × 10 Ω
i
6

ˆ Output impedance (R ) = 75Ω

O

ˆ Input offset voltage (V ) = 2mV

io

ˆ Input offset current (I ) = 20nA

io

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ˆ Input bias current (I ) = 8µA

B

ˆ CMRR = 90dB
ˆ Slew rate (S) = 0.5V /µsec

3.6 Numerical on Op-Amp Characteristics

1. Determine the input bias current and input offset current IB and Iio for an op-amp
if the current into non-inverting terminal is 8.3 µA and inverting terminal is 7.9 µA.
Given:
IB1 =8.3 µA, IB2 =7.9 µA

IB1 + IB2 8.3 µA + 7.9 µA

IB = = = 8.1 µA
2 2

Iio = |IB1 − IB2 | = |8.3 µA − 7.9 µA| = 0.4 µA

E
2. A certain Op-amp has a differential voltage gain of 1, 00, 000 and common mode
gain of Ac = 0.25. Determine CMRR and express it in dB.
TT

Given:
Ad = 1, 00, 000, Ac = 0.25
NI

Common Mode Rejection Ratio (CMRR):

Ad 1, 00, 000
CMRR = = = 4, 00, 000
Ac 0.25

In decibels (dB):

CMRRdB = 20 log10 (4, 00, 000) = 112.04 dB

3. An Op-amp has a differential voltage gain of 2500 and a CMRR of 30, 000.

i) Determine the common mode gain Ac

ii) Express CMRR in dB

Given:
Ad = 2500, CMRR = 30, 000

i)
Ad Ad 2500
CMRR = ⇒ Ac = = = 0.0833
Ac CMRR 30000

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ii)
CMRRdB = 20 log10 (30000) = 89.54 dB

4. An Op-amp has a common mode input signal of 3.2 V to both the input terminals.
This results in an output signal of 26 mV. Determine the common mode gain Ac
and CMRR in dB. Given that the differential gain is 100.

Given:
Vc = 3.2 V, Vo = 26 mV, Ad = 100

Common Mode Gain:

Vo 26 mV
Ac = = = 0.0081
Vc 3.2 V
Common Mode Rejection Ratio:
Ad 100
CMRR = = = 12345.6
Ac 0.0081

CMRR in decibels:

CMRRdB = 20 log10 (12345.6) = 81.83 dB

E
3.7 Virtual Ground Concept
TT

Virtual ground means, the differential input voltage Vd between the non-inverting and
inverting terminal is zero.
Eg: If the output voltage is 10V and open loop gain AOL is 104 , then
NI

VO = AOL Vd
Vo 10
Vd = = 4 = 1mV
AOL 10

Hence, Vd is very small. It means that AOL is ∞ (large). The difference voltage Vd is
small and in practice, it is assumed to be zero. Therefore,
Vo
Vd =
AOL
Vo
⇒ (V1 − V2 ) = =0
∞
⇒ V1 = V2

i.e. There exists a virtual short circuit between the two input terminals, in the sense that
their voltages are the same. So if one terminal is at ground, other terminal is at virtual
ground. No current flows from the input terminals to the ground. The thick line in the
Figure 3.10 indicates the virtual short circuit between the input terminals.
If one terminal is at a particular voltage level, the other terminal is at the same voltage
level. This is the concept of Virtual Ground.

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Figure 3.10: Virtual Ground Concept in Op-amp

3.8 Saturable Property of an Op-Amp:

The property by which the output voltage of an Op-Amp saturates at two saturation
levels ±Vsat decided by the supply voltages is called as saturable property of OP-Amp.
Every OP-Amp has a property that its output can swing between two levels decided by
supply voltage i.e. +VCC and −VEE . Thus if the output tries to rise more than +VCC or
less than −VEE , then the output signal gets clipped off and shows that saturation limit
has reached. Output signal cannot be produced exceeding the saturation voltage levels.
E
TT
NI

Figure 3.11: Saturable property

For example: Let a sine wave of 1 mV-pp be applied as the input to op-amp with
gain AOL = 105 . Then the output voltage is obtained as a wave that is clipped at
+Vsat = ±15V
Solution:

Let the input be: Vin = Vd = 1mV

Therefore,

Vo = AOL · Vd = 105 × 1 mV = 105 × 1 × 10−3 = 100 Vp-p

This saturable property of Op-amp can be effectively used to obtain a device called
as a comparator.

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Waveforms:

Figure 3.12: Saturable property example

3.9 Op-Amp Applications

Main applications of the op-amp are:

ˆ Inverting amplifier
ˆ Non inverting amplifier
E
ˆ Inverting Summer
TT

ˆ Integrator
ˆ Differentiator
ˆ Comparator
NI

ˆ IC voltage regulator
3.9.1 Inverting Amplifier
An inverting amplifier is a basic configuration of an operational amplifier (op-amp) that
inverts and amplifies the input signal. Amplifier that has a phase shift of 1800 at the
output compared to that of input signal is known as inverting amplifier.

Figure 3.13: Inverting Amplifier

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In the circuit shown in Figure 3.13,the input signal Vin is applied to the inverting
input (-) of the op-amp through a resistor R1 . Hence it is called Inverting amplifier. The
non-inverting input (+) is grounded. A feedback resistor Rf is connected from the output
to the inverting input. Since the non-inverting terminal is grounded, potential at node
B, VB =0V.

According to virtual ground concept, node A is at virtual short with node B. There-
fore, the potential at node A, VA = 0V. That is VA = VB = 0V

Since the current flowing through the input terminals of the opamp is zero, the entire
current I1 through R1 also flows through Rf as If .

∴ I1 = If (1)

From the input side, by applying KVL, we have:

Vin − I1 R1 − VA = 0V
Vin − VA
I1 =
R1
Vin
I1 = ∵ VA = 0 (2)
R1
E
From the output side, by applying KVL,
TT

VA − If Rf − Vo = 0V
VA − Vo
If =
NI

Rf
Vo
If = − ∵ VA = 0 (3)
Rf

Substituting the (2) and (3) in (1) we have,

Vin Vo
=−
R1 Rf
VO Rf
=− = ACL
Vin R1

ACL is the closed loop gain of an inverting amplifier and it depends on the value of Rf
and R1 . The output voltage of the inverting amplifier is:
 
Rf
VO = − Vin (4)
R1

The negative sign indicates the presence of the phase shift of 180◦ between input and
output signal Vin and Vo .

Waveforms:

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Figure 3.14: Inverting Amplifier Waveform

3.9.2 Noninverting Amplifier

An amplifier that amplifies the input signal Vin without generating any phase shift be-
tween input and output is called as non-inverting amplifier.
That is the output signal is in phase with input signal.

E
TT
NI

Figure 3.15: Noninverting Amplifier

Vin is connected to the non-inverting terminal (+) of the op-amp. Feedback resistor
Rf connects the output to the inverting terminal (–). Resistor R1 connects the inverting
terminal (–) to ground. From the input side node B is connected to the non-inverting
terminal and also to the input signal Vin . Hence at node B, VB = Vin .
According to the virtual ground, potential at node A(VA ) is same as potential at node
B(VB ). That is,

VA = VB = Vin

Since the current flowing through the input terminals of the opamp is zero. Therefore
entire current If through Rf also flows through R1 as I1 .

∴ If = I1 (1)

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From the output side, by applying KVL, we have,

Vo − If Rf − VA = 0V
VO − VA
If =
Rf
VO − Vin
If = ∵ VA = Vin (2)
Rf
At the input side, we have,
VA − I1 R1 = 0
VA Vin
I1 = = ∵ VA = Vin (3)
R1 R1
Substituting (2) and (3) in (1), we have,
VO − Vin Vin
=
Rf R1

Vin Vin Vo
+ =
R1 Rf Rf

 
Rf + R1 Vo
E
Vin =
R1 Rf Rf
TT

Simplifying above equation, we get,

Vo Rf
=1+ = ACL
Vin R1
NI

ACL is the closed loop gain of the non-inverting amplifier. The output of the non-inverting
amplifier is:
 
Rf
Vo = Vin 1 + (4)
R1
Here there is no phase shift between input and output signal Vin and Vo .

Waveforms:

Figure 3.16: Noninverting Amplifier Waveform

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3.9.3 Inverting Summer (Adder)

In this circuit, all the input signals to be added are applied to the inverting input terminal
of the op-amp. The output signal Vo obtained is the sum of all the input signals, with
the negative sign indicating the 180◦ phase shift between the input and output signals.
Hence the name, inverting summer.
Circuit Diagram:

Figure 3.17: Inverting Summer

Input signals V1 , V2 , and V3 are applied to the inverting terminal through R1 , R2 , and
R3 , and the non-inverting terminal is connected to ground. Rf is the feedback (negative
E
feedback) resistor connected from the output terminal to the input terminal.
In the above circuit non-inverting terminal is grounded. Potential at node B, VB =0V.
TT
According to the virtual ground concept, the potential at node A(VA ) is same as potential
at node B(VB ). That is, VA =VB =0V.

In an circuit diagram, by applying KCL at inverting node,

NI

I1 + I2 + I3 = If
V1 − VA V2 − VA V3 − VA VA − Vo
+ + =
R1 R2 R3 Rf

Since VA =0 due to virtual ground concept. Therefore,

V1 V2 V3 Vo
+ + =−
R1 R2 R3 Rf
 
Vo V1 V2 V3
=− + +
Rf R1 R2 R3

If R1 = R2 = R3 = Rf then,

V0 = − (V1 + V2 + V3 )

Hence, the output voltage is an algebraic sum of all the applied input voltages V1 + V2 +
V3 . . . .VN and hence it is called summer or adder circuit. Negative sign indicates the
presence of a 180◦ phase shift between the input and the output.

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3.9.4 Integrator

Figure 3.18: Integrator

The output of an op-amp integrator is the time integral of the applied input voltage
Vin . In the given configuration, the non-inverting terminal is grounded. The inverting
terminal is connected to the input signal Vin through a resistor R1 , and a capacitor Cf is
connected from the output terminal back to the inverting terminal, forming a feedback
loop.
E
TT
Initially, when an input signal Vin is applied, the capacitor Cf is uncharged, and
maximum current flows through resistor R1 . The capacitor begins charging based on
the R1 Cf network during the positive half-cycle of Vin . During the negative half-cycle,
the capacitor discharges. Since Vin is applied to the inverting terminal, the output V0 is
°
NI

inverted, introducing a 180 phase shift.

Let the potential at node A be VA . Since node B is grounded, the potential at node
B, VB = 0V. By the virtual ground concept,

VA = VB = 0V

Due to the high input impedance of the op-amp, no current flows into its input terminals.
As input current I1 flows entirely through the feedback path:

I1 = If
Vin − VA d(VA − V0 )
= Cf
R1 dt
Since VA =0V due to virtual ground concept,
Vin dV0
= −Cf
R1 dt
Integrating on both the sides:
Z t
Vin
dt = −Cf V0
0 R1
Z t
1
V0 = − Vin dt
R1 Cf 0

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Hence, the output voltage V0 is the integration of the input voltage Vin . The negative
°
sign indicates a 180 phase shift between input Vin and output V0 .

Figure 3.19: Integrator Output

3.9.5 Differentiator
The circuit that generates the differentiation of the input voltage Vin at the output is
called as differentiator.
E
TT
NI

Figure 3.20: Differentiator

The input voltage Vin is applied to a capacitor. The capacitor blocks DC and allows
only AC signals to pass. The capacitor begins charging based on the C1 Rf network
during the positive half-cycle of Vin . It charges up to the peak value of the input voltage.
During the negative half-cycle, the capacitor discharges.
Let the potential at node A be VA . Since node B is grounded, the potential at node
B, VB = 0V. By the virtual ground concept,
VA = VB = 0V
The current into the input terminals of the op-amp is zero, so all current I1 flows
through Rf as If .
I1 = If
d(Vin − VA ) VA − V 0
C1 =
dt Rf

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Since VA =0V due to virtual ground concept,

dVin V0
C1 =−
dt Rf
dVin
V0 = −Rf C1
dt
Hence, the output voltage V0 is the differentiation of the input voltage Vin . The
°
negative sign indicates a 180 phase shift between input Vin and output signal V0 .

E
Figure 3.21: Differentiator Output
TT

3.9.6 Comparators
ˆ Comparator is a decision-making electronics circuit.
NI

ˆ Op-amp comparators compare the magnitude of two voltage levels at the input and
determines as which is the largest of the two.

Types of comparators:
1. Inverting Comparator

(a) With +ve reference voltage

(b) With -ve reference voltage

2. Noninverting Comparator

(a) With +ve reference voltage

(b) With -ve reference voltage

1. Inverting Comparator
Here, since Vin is applied to the inverting terminal of op-amp, it is called as Inverting
Comparator.

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(a) With +ve reference voltage (+Vref ):

Figure 3.22: Inverting Comparator with +Vref

Waveform:

E
TT
NI

Figure 3.23: Output of Inverting Comparator with +Vref

Working: A fixed DC reference voltage +Vref is connected to the non-

inverting terminal. R are the current limiting resistors.

When Vin < +Vref , output voltage V0 is at +Vsat . This is because +Vref volt-
age at non inverting terminal is more compared to the Vin voltage at inverting
terminal. Hence output voltage V0 is at +Vsat .

When Vin > +Vref , output voltage V0 swings to −Vsat from +Vsat . This is
because time varying signal Vin at inverting terminal is more compared to the

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+Vref voltage at the non-inverting terminal. Hence output voltage V0 is at

−Vsat . This process repeats for the next cycles as shown in the waveform.
Note: In short, when Vin < +Vref , V0 = +Vsat , and when Vin > +Vref , V0 =
−Vsat .

(b) With -ve reference voltage (−Vref ):

Figure 3.24: Inverting Comparator with −Vref

E
Waveform:
TT
NI

Figure 3.25: Output of Inverting Comparator with −Vref

Working: A fixed DC reference voltage −Vref is connected to the non-

inverting terminal. R are the current limiting resistors.

When Vin > −Vref , output voltage V0 is at −Vsat . This is because time varying
signal Vin at inverting terminal is more compared to the −Vref voltage at the

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non-inverting terminal. Hence output voltage V0 is at −Vsat .

When Vin < −Vref , output voltage V0 swings to +Vsat from −Vsat . This is
because −Vref voltage at non inverting terminal is more compared to the Vin
voltage at inverting terminal. Hence output voltage V0 is at +Vsat . This
process repeats for the next cycles as shown in the waveform.
Note: In short, When Vin > −Vref , V0 = −Vsat and when Vin < −Vref ,
V0 = +Vsat .
2. Noninverting Comparator
Here, since Vin is applied to the noninverting terminal of op-amp, it is called as
Noninverting Comparator.
(a) With +ve reference voltage (+Vref ):

E
TT

Figure 3.26: Noninverting Comparator with +Vref

NI

Waveform:

Figure 3.27: Output of NonInverting Comparator with +Vref

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Working: A fixed DC reference voltage +Vref is connected to the inverting

terminal. R are the current limiting resistors.

When Vin < +Vref , output voltage V0 is at −Vsat . This is because +Vref volt-
age at inverting terminal is more compared to the Vin voltage at non-inverting
terminal. Hence output voltage V0 is at −Vsat .

When Vin > +Vref , output voltage V0 swings to +Vsat from −Vsat . This is
because time varying signal Vin at non-inverting terminal is more compared
to the +Vref voltage at the inverting terminal. Hence output voltage V0 is at
+Vsat . This process repeats for the next cycles as shown in the waveform.
Note: In short, when Vin < +Vref , Vo = −Vsat , and when Vin > +Vref , Vo =
+Vsat .

(b) With -ve reference voltage (-Vref ):

E
TT

Figure 3.28: Non-inverting Comparator with -Vref

NI

Waveform:

Figure 3.29: Output of non-inverting Comparator with -Vref

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Working: A fixed DC reference voltage −Vref is connected to the inverting

terminal. R are the current limiting resistors.

When Vin > −Vref , output voltage V0 is at +Vsat . This is because time varying
signal Vin at non-inverting terminal is more compared to the −Vref voltage at
the inverting terminal. Hence output voltage V0 is at +Vsat .

When Vin < −Vref , output voltage V0 swings to −Vsat from +Vsat . This
is because −Vref voltage at inverting terminal is more compared to the Vin
voltage at non-inverting terminal. Hence output voltage V0 is at −Vsat . This
process repeats for the next cycles as shown in the waveform.
Note: In short, When Vin > −Vref , V0 = +Vsat and when Vin < −Vref ,
V0 = −Vsat .

3.10 IC Voltage Regulator

One of the important sources of DC supply are batteries. But using batteries in sensitive
electronic circuits is not a good idea, since batteries eventually drain out and loose their
potential over time. Hence for obtaining constant and steady output, voltage regulators
are implemented. The integrated circuits which are used for the regulation of voltage are
E
termed Voltage regulator ICs.
78XX family of linear voltage regulators produce a regulated output voltage. XX
TT
in 78XX series represents the value of the fixed output voltage that the particular IC
provides. E.g. : IC 7805 is a three terminal linear voltage regulator IC with a fixed
output voltage of 5V.
The functional diagram of 78XX series based fixed IC voltage regulator is shown be-
NI

low. (Note that XX can be 05,06,08,10,12,15,18 or 24V)

Figure 3.30: Block diagram of op-amp Series voltage regulator with feedback

IC voltage regulators can be used to regulate, the unregulated input volage and pro-
vide a constant regulated output voltage.

Advantages: Inexpensive, versatile, provides current/voltage boosting, internal short

circuit, current limiting and thermal shut down.

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Working: An unregulated input voltage Vin is applied to the series voltage regulator.
A regulated output voltage Vout is measured at the output terminal. A pass transistor
Q1 is connected as a control element in series with load between the input and output.

Figure 3.31: Circuit diagram of op-amp Series voltage regulator with feedback

A Zener diode reference voltage Vref drives the non-inverting terminal of a high-gain
amplifier. A voltage regulator network with the resistors R1 and R2 samples the output
voltage and returns a feedback voltage to the inverting input terminal of a high-gain
amplifier.
E
Where, the reference voltage Vref is equivalent to the Zener voltage Vz . R1 and R2
TT
are internal to the IC. They are already trimmed to get different output voltages (5V
to 15V) in 78XX series. The pass transistor enhances the regulator output current. It
can handle 1A of load current with the proper heat sinks. The output sample circuit
senses a change in the output voltage. The error detector compares the sample volage
with a fixed reference voltage Vref . The resulting difference voltage causes the transistor
NI

Q1 to control the conduction and to compensate the variation in the output voltage. The
output voltage Vout will be maintained at a constant value as in below equation.
 
R1
Vout = 1 + Vref
R2

 
R1
Vout = 1+ Vz
R2

3.11 Numerical on Op-Amp Applications

1. A sine wave of 0.5 V peak voltage is applied to an inverting amplifier using
R1 = 10 kΩ and Rf = 50 kΩ. It uses supply voltages of ±12 V. Determine the
output and sketch the waveform. If now the amplitude of the input sine wave is
increased to 5 V, what will be the output? Is it practically possible? Sketch the
waveform.

Solution:

For an inverting amplifier,

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Vo Rf 50
ACL = =− = − = −5
Vin R1 10
Now, for Vin = 0.5 V (input),

Vo = (Vin ) × ACL = 0.5 × (−5) = −2.5 V (peak)

The input and output waveforms are inverted with respect to each other and are
shown in Figure 3.32 (a).
Now, for Vin = 5 V (input),

Vo = (Vin ) × ACL = 5 × (−5) = −25 V (peak)

But op-amp output saturates at ±12 V, i.e., at the supply voltages used. So, the
portion above +12 V and below −12 V will be clipped off from the output. Hence,
25 V peak output is not practically possible. The input and output waveform are
shown in Figure 3.32(b).
E
TT
NI

Figure 3.32: Problem 1

2. For an inverting amplifier using an op-amp with R1 = 10 kΩ and Rf = 1 MΩ,

calculate the closed-loop voltage gain and the required input voltage to obtain an
output voltage of 3 V.

Solution:

The formula for the closed-loop voltage gain of an inverting amplifier is:
Rf
ACL = −
R1

Substituting the given values:

1 MΩ
ACL = − = −100
10 kΩ

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The formula for the input voltage Vin in an inverting amplifier is:
Vo
Vin =
ACL

3
Vin = = −0.03 V
−100
Therefore, the required input voltage is −0.03 V.

3. For the given op-amp configuration in the figure 3.33, determine the value of Rf
required to produce a closed-loop voltage gain of −100.

E
TT
NI

Figure 3.33: Problem 3

Solution:

The formula for the closed-loop voltage gain of an inverting amplifier is:
Rf
ACL = −
R1

Rearranging the formula to solve for Rf :

Rf = −ACL · R1

Given ACL = −100, R1 = 2.2 kΩ:

Rf = −(−100) × 2.2 kΩ = 220 kΩ

Therefore, the required value of Rf is 220 kΩ.

4. Determine the voltage gain of the op-amp circuit shown in Figure 3.34.

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Figure 3.34: Problem 4

Solution:

From Figure, we have:

R1 = 10 kΩ, Rf = 47 kΩ

The circuit is an inverting amplifier.

E
The voltage gain ACL of an inverting amplifier is given by:
TT
Rf
ACL = −
R1

Substituting the given values:

NI

47 kΩ
ACL = − = −4.7
10 kΩ

Therefore, the gain is 4.7 and the negative sign indicates a 180° phase
shift, i.e., the circuit operates in inverting mode.

5. The non-inverting amplifier circuit has a gain of 10 and a feedback resistor Rf =

90 kΩ. Calculate the value of the input resistance R1 .

Solution:

The gain ACL of a non-inverting amplifier is given by:

Rf
ACL = 1 +
R1

Rearranging the formula to solve for R1 :

Rf
R1 =
ACL − 1

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Substituting the given values:

90 kΩ 90 kΩ
R1 = = = 10 kΩ
10 − 1 9

Therefore, the value of input resistance R1 is 10 kΩ.

6. For a non-inverting amplifier using an op-amp, assume R1 = 470 Ω and Rf = 4.7 kΩ.
Calculate the closed-loop voltage gain of the amplifier.

Solution:

The voltage gain ACL of a non-inverting amplifier is given by:

Rf
ACL = 1 +
R1

Substituting the given values:

4.7 × 103
ACL =1+ = 1 + 10 = 11
470
Therefore, the closed-loop voltage gain of the amplifier is 11.
E
7. For the non-inverting amplifier circuit shown in the figure 3.35, find the peak-to-
TT
peak output voltage when Vin = 2 Vpp , and sketch the input and output waveforms.
NI

Figure 3.35: Problem 7

Solution:

The gain ACL of a non-inverting amplifier is given by:

Rf
ACL = 1 +
R1

Substituting the given values:

5 kΩ
ACL = 1 + =1+5=6
1 kΩ
The peak-to-peak output voltage is calculated as:

Vo(pp) = ACL × Vin(pp)

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Vo(pp) = 6 × 2 Vpp = 12 Vpp

Therefore, the peak-to-peak output voltage is 12 Vpp .

Waveforms:

8. An inverting adder has the following parameters: R1 = 2 kΩ, R2 = 4 kΩ, Rf = 8 kΩ.

If V1 = 1.5 V and V2 = 0.5 V, what is the output voltage?

Solution:
E
The output voltage Vo of an inverting adder is given by:
TT

 
V1 V2
Vo = −Rf +
R1 R2
NI

 
1.5 0.5
Vo = −8 kΩ + = −8 kΩ (0.75 + 0.125) = −8 kΩ × 0.875 = −7 V
2 kΩ 4 kΩ

Therefore, the output voltage is −7 V.

9. Design an inverting adder circuit using an op-amp to obtain the output voltage
given by:
Vo = 2V1 + 3V2 + 4V3
where V1 , V2 , and V3 are input voltages. Given: Rf = 20 kΩ. Draw the circuit
indicating all resistor values.

Solution:

The output voltage of an inverting adder is given by:

   
V1 V2 V3 Rf Rf Rf
Vo = −Rf + + =− V1 + V2 + V3
R1 R2 R3 R1 R2 R3

Given desired output:

Vo = 2V1 + 3V2 + 4V3

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Comparing coefficients:
Rf Rf 20 kΩ
= 2 ⇒ R1 = = = 10 kΩ
R1 2 2
Rf Rf 20 kΩ
= 3 ⇒ R2 = = ≈ 6.67 kΩ
R2 3 3
Rf Rf 20 kΩ
= 4 ⇒ R3 = = = 5 kΩ
R3 4 4
Therefore, the resistor values are:

R1 = 10 kΩ, R2 ≈ 6.67 kΩ, R3 = 5 kΩ

E
TT
Figure 3.36: Problem 9

10. Design a summer circuit using an op-amp for the output voltage:
NI

Vo = −2 (0.1V1 + 0.5V2 + 2V3 )

Given: Feedback resistor Rf = 10 kΩ. Draw the circuit diagram for the same.

Solution:

The general expression for the output voltage of an inverting adder is:
   
V1 V2 V3 Rf Rf Rf
Vo = −Rf + + =− V1 + V2 + V3
R1 R2 R3 R1 R2 R3

Given:
Vo = −2 (0.1V1 + 0.5V2 + 2V3 ) = − (0.2V1 + 1V2 + 4V3 )

Comparing coefficients:
Rf Rf 10 kΩ
= 0.2 ⇒ R1 = = = 50 kΩ
R1 0.2 0.2
Rf Rf
= 1 ⇒ R2 = = 10 kΩ
R2 1
Rf Rf 10 kΩ
= 4 ⇒ R3 = = = 2.5 kΩ
R3 4 4

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Therefore, the required resistor values are:

R1 = 50 kΩ, R2 = 10 kΩ, R3 = 2.5 kΩ, Rf = 10 kΩ

Figure 3.37: Problem 10

E
TT
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Chapter 4

Feedback and Oscillator Circuits

4.1 Introduction
ˆ Feedback plays an important role in electronic circuits. It is used in amplifiers to
improve its performance and make it more ideal.

ˆ In feedback amplifiers, a part of the output is sampled and feedback to the input
of the amplifier.

ˆ At the input, there will be two signals, input signal and a part of the output. Both
E
may be in phase or out of phase with each other.

ˆ Depending on the polarity of the signal fed back into the circuit, it can be negative
TT

or positive feedback.

ˆ When the input signal and the feedback signal are out of phase, it is negative
NI

feedback.

ˆ When the input signal and the feedback signal are in phase, it is positive feedback.
ˆ Negative feedback results in decreased voltage gain, for which a number of circuit
factors are improved.

ˆ Positive feedback drives the circuit into oscillations.

4.2 Negative Feedback Concepts
A typical feedback connection is shown in Figure 4.1. The input signal Vs is applied to
the mixer network, where it is combined with a feedback signal Vf . Vi is the difference
of these two signals. It is then applied as the input to the amplifier whose gain is A.
A portion of the amplifier output Vo is connected to the feedback network (β), which
provides a reduced portion of the output as feedback signal to the input mixer network.

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 Basic Electronics

Figure 4.1: Negative Feedback Concept

Advantages of negative feedback are:

1. Reduced overall voltage gain

2. Higher input impedance

3. Improved frequency response

4. Lower output impedance

5. Reduced noise
E
6. More linear operation
TT

4.3 Voltage series negative feedback amplifier

NI

Here the voltage refers to connecting the output voltage of the amplifier as input to the
feedback network. Series refers to connecting the feedback signal in series with the in-
put signal. Series negative feedback connection tends to increase the input impedance,
whereas voltage feedback tends to decrease the output impedance. Most of the cascade
amplifiers require higher input impedance and lower output impedance. Both of those
are provided using the voltage series feedback connection.

Figure 4.2: Voltage series negative feedback circuit

In the above figure, Vs is the overall input signal. The voltage Vi is the difference
signal connected to the amplifier. Without feedback, amplifier gain is ‘A’. The feedback

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network has the feedback factor is β. The overall gain with feedback of the above system
is Af . In the voltage series feedback connection, the part of the output voltage Vo , is fed
back in series with the input signal, that results in overall reduction in the gain. In a
circuit, if there is no feedback (i.e. Vf =0), the voltage gain of the amplifier stage is,
Vo
A=
Vi
Vo = AVi (1)
From the circuit,
Vf
β=
Vo
Vf = βVo (2)
If a feedback signal Vf is connected in series with the input, then,
Vi = Vs − Vf (3)
Substitute (3) in (1),

Vo = AVi = A(Vs − Vf ) (4)

Substitute (2) in (4),
E
TT
Vo = AVs − AβVo
Vo + AβVo = AVs
Vo (1 + Aβ) = AVs
NI

So that, the overall gain with feedback is:

Vo A
Af = =
Vs 1 + Aβ
Here, |Af | < |A|. The negative feedback reduces the gain of the amplifier by a factor
of (1 + Aβ).

4.4 Numerical on Voltage series feedback amplifier

1. Determine the voltage gain with feedback for a voltage series feedback system having:

A = −100, β = −0.1 and β = −0.5

Solution:
ˆ For β = −0.1,
−100 −100 −100
Af = = = ≈ −9.09
1 + (−100)(−0.1) 1 + 10 11

ˆ For β = −0.5,
−100 −100 −100
Af = = = ≈ −1.96
1 + (−100)(−0.5) 1 + 50 51

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4.5 Oscillator operation

When the input signal and feedback signals are in-phase with each other it is known as
positive feedback. Feedback amplifier circuit with positive feedback having closed loop or
overall gain |Af | > 1 will result in operation as an oscillator circuit. If the output signal
varies sinusoidally, it is referred to as sinusoidal oscillator.

Figure 4.3: Positive feedback concept

If the output signal rises quickly to one voltage level and later drops to another level,
it is referred to as a square wave oscillator. Here the oerall gain with feedback is:
E
Vo A
TT
Af = =
Vs 1 − Aβ
Both Vs and the feedback signal Vf are in-phase with each other. The gain with
feedback increases as the amount of positive feedback increases and becomes infinity.
Consider various values of the β and corresponding values of Af for constant amplifier
NI

gain, A=20.

Table 4.1: Feedback Gain for Different Values of β

A β Af
20 0.005 22.22
20 0.04 100
20 0.045 200
20 0.05 ∞

From the above table it is true that for a constant amplifier gain a small value of
increase in β the overall gain reaches infinity. This indicates that circuit can produce
output without external input (Vs = 0), just by feeding the part of the output as its own
input. Similarly, output cannot be infinite but gets driven into the oscillations. In other
words, the circuit stops amplifying and starts oscillating.
Thus without an input, the output will continue to oscillate whose frequency depends
upon the feedback network or the amplifier or both. Such a circuit is called as an oscil-
lator.

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4.5.1 Barkhausen criterion

Figure 4.4: Oscillator Block diagram

Consider the block diagram shown in Figure 4.4 with positive feedback. Assume a
fictitious voltage Vi at the amplifier input. This results in an output voltage:
Vo = AVi
E
after the amplifier stage, and a feedback voltage:
TT
Vf = βVo
after the feedback network. Substituting for Vo :

Vf = β(AVi ) = AβVi
NI

Here, the product Aβ is referred to as the loop gain. For the circuit to work as an
oscillator, the feedback voltage Vf must drive the amplifier. Hence, Vf must act as the
input voltage Vi .
When the fictitious input voltage Vi is removed, the circuit continues to operate
because the feedback voltage is sufficient to sustain the amplifier operation. The output
waveform will continue to exist if the following condition is satisfied:

Aβ = 1
To achieve sustained oscillations using an electronic circuit, it must meet Barkhausen’s
Criterion, proposed by Heinrich Georg Barkhausen (a German Physicist). The criterion
consists of two conditions:
1. Phase Shift Condition: The total phase shift around the loop, as the signal
proceeds from input through the amplifier, feedback network, and back to the input
again (amplifier-feedback network-amplifier circuit), should be:
0◦ or 360◦

2. Magnitude Condition: The magnitude of the product of the open-loop gain A

and the feedback factor β must be unity:
|Aβ| = 1

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By satisfying these two conditions, the circuit works as an oscillator, producing sus-
tained oscillations.
However, in practice, if Aβ > 1, the system can start oscillating by amplifying ambient
noise voltage. The oscillations are growing type. The amplitude of oscillations goes on
increasing as shown in Figure 4.5. The resulting waveform may not be a perfect sinusoid.
The closer the value of Aβ is to 1, the more sustained and sinusoidal the output waveform
becomes shown in Figure4.7. If Aβ < 1 then the oscillations are decaying type is shown
in Figure 4.6 . The oscillations’ amplitude decreases exponentially, and the oscillations
finally cease.

E
Figure 4.5: Growing Aβ > 1
TT
NI

Figure 4.6: Decaying, Aβ < 1

Figure 4.7: Suatainable, Aβ=1

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4.6 Types of Oscillators

1. RC Oscillator (Low frequency signal generator)

(a) RC Phase Shift Oscillator

2. LC Oscillator (High frequency signal generator)

(a) Hartley Oscillator

(b) Colpitts Oscillator

4.6.1 RC Phase Shift Oscillator

A RC Phase Shift Oscillator is an electronic circuit that generates a low frequency
sine wave signal. It is designed for the generation of low-frequency sinusoidal oscillations
with the audio frequencies typically ranging from 20 Hz to 20 kHz.

Circuit Operation
The circuit diagram of an RC phase shift oscillator is shown in Figure 4.8.
E
TT
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Figure 4.8: RC Phase Shift Oscillator

In this configuration:
ˆ An op-amp is used as an inverting amplifier, generating a phase shift of 180 . ◦

ˆ The feedback network consists of three RC sections connected in a ladder con-

figuration.

ˆ Each RC section contributes a phase shift of approximately 60 , giving a total of

◦

180◦ .
The impedance Z of the each RC circuit is given by:

Z = R − jXc
p
|Z| = R2 + Xc2 ,
 
−1 Xc
Φ = tan
R

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By choosing appropriate values of R and C, the phase angle ϕ can be adjusted to

equal 60◦ , as required by the RC phase shift oscillator.

No external input signal is required to start oscillations. The oscillations are self
starting and begin as soon as DC power is applied. Under the room temperature, free
electrons in the resistance generate a noise voltage, across the resistance. Such noise
voltages or fluctuations are amplified in the circuit, initiating a weak oscillation. The
output of the inverting amplifier is applied to the feedback network. This signal which is
fed back to the amplifier drives it further.
Thus, the total phase shift around the loop is:

180◦ (from amplifier) + 180◦ (from RC network) = 360◦

This satisfies the condition for positive feedback, allowing the circuit to oscillate in
accordance with Barkhausen criteria. The frequency of oscillation of the RC phase
shift oscillator is given by:
1
f= √
2πRC 6

4.6.2 Hartley Oscillator

E
A Hartley Oscillator is an electronic circuit that generates a high frequency sine wave
signal. It is designed for the generation of high-frequency sinusoidal oscillations with the
TT
radio frequencies typically ranging from 10 kHz to 100 MHz.
NI

Figure 4.9: Hartley Oscillator

A Hartley oscillator uses an operational amplifier (Op-Amp) configured as an

inverting amplifier, which introduces a phase shift of 180◦ . The feedback network of a
Hartley Oscillator consists of two inductors L1 and L2 , and a single capacitor C. The
LC tank circuit is formed by connecting two inductors L1 and L2 in series, and placing

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them in parallel with the capacitor C.

Even though there is no input signal, the small noise voltages are amplified by the
op-amp when the power supply is given to the circuit. At the same time, the capacitor
C1 starts charging. When the capacitor is fully charged, it starts discharging through
inductor L2. The electrostatic energy stored in the capacitor gets transferred to the
inductors as a magnetic flux when the capacitor is fully discharged. Once the energy
is transferred, the inductors start discharging and capacitor get charged again. This
transfer of energy between the capacitor and the inductors gives an oscillation across
L2. The oscillations from L2 are transferred to L1. The voltage across L1 is fed back to
the amplifier is in opposite phase to that of the voltage across L2, since the ground is
provided between L1 and L2.
This results in a total phase shift of:

180◦ (from amplifier) + 180◦ (from tank circuit) = 360◦

This satisfies the condition for positive feedback, allowing the circuit to oscillate in
accordance with Barkhausen criteria.
The frequency of oscillation is given by:
1
f= p
E 2π Leq C
where
TT

Leq = L1 + L2
If mutual inductance M exists between L1 and L2 , then:
NI

Leq = L1 + L2 + 2M
The feedback factor is given by:
L1
β=
L2
The condition for sustained oscillations is:

|Aβ| ≥ 1

1
⇒ |A| ≥
β
L2
⇒ |A| ≥
L1

4.6.3 Colpitts Oscillator

A Colpitts Oscillator is an electronic circuit that generates a high frequency sine wave
signal. It is designed for the generation of high-frequency sinusoidal oscillations with the
radio frequencies typically ranging from 20 kHz to 300 MHz.

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Figure 4.10: Colpitts Oscillator

A Colpitts oscillator uses an operational amplifier (Op-Amp) configured as an

E
inverting amplifier, which introduces a phase shift of 180◦ . The feedback network of a
Colpitts Oscillator consists of two capacitors C1 and C2 , and a single inductor L. The
TT

LC tank circuit is formed by connecting two capacitors C1 and C2 in series, and placing
them in parallel with the inductor L1 .

Even though there is no input signal, the small noise voltages are amplified by the
NI

op-amp when the power supply is given to the circuit. At the same time, the capacitors
C1 and C2 starts charging. Once the capacitors are fully charged, they start discharging
through the inductor L1 . The electrostatic energy stored in the capacitors gets trans-
ferred to the inductor as a magnetic flux when the capacitors are fully discharged. Once
the energy is transferred, the inductors start discharging, and the capacitors get charged
again. This transfer of energy between the capacitor and the inductor gives an oscilla-
tion. The voltage across C1 is fed back to the amplifier is in opposite phase to that of
the voltage across C2 , since the ground is provided between C1 and C2 .
This results in a total phase shift of:
180◦ (from amplifier) + 180◦ (from tank circuit) = 360◦
This satisfies the condition for positive feedback, allowing the circuit to oscillate in
accordance with Barkhausen criteria. The frequency of oscillations i given by,
1
f= p
2π LCeq
Where,
C1 C2
Ceq =
C1 + C 2
The feedback factor is:
C2
β=
C1

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The condition for sustained oscillations is:

|Aβ| > 1

1
⇒ |A| >
β
C1
⇒ |A| >
C2

4.7 Numerical on Oscillator

1. A RC phase shift oscillator uses three identical RC sections. Each resistor R =
10 kΩ and each capacitor C = 0.01 µF. Calculate the frequency of oscillation.
Solution:
The frequency of oscillation for a RC phase shift oscillator is given by:

1
f= √
2πRC 6
Substitute the values:
E
R = 10 kΩ = 10 × 103 Ω, C = 0.01 µF = 0.01 × 10−6 F
TT

1
f= √
2π × 10 × 103 × 0.01 × 10−6 × 6
NI

1 1
f= √ ≈ −4
2π × 10−4 × 6 2π × 10 × 2.45

1
f≈ ≈ 64.9 Hz
1.54 × 10−3
Answer: f ≈ 64.9 Hz
2. In an RC phase shift oscillator, R = 500 Ω and C = 0.1 µF. Calculate the frequency
of oscillations.

Given: R = 500 Ω, C = 0.1 µF

Frequency of oscillations is given by

1
f= √
2πRC 6

1
f= √
2π × 500 × 0.1 × 10−6 × 6

∴ f = 1.299 kHz

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3. In an RC phase shift oscillator, R = 1000 Ω. If the frequency of oscillations is 5 kHz,

calculate the value of C.

Given: R = 1000 Ω, f = 5 kHz

Frequency of oscillations is given by

1 1
f= √ or C = √
2πRC 6 2πRf 6

1
∴ C= √
2π × 1000 × 5000 × 6

C = 0.0129 µF

4. Design an RC phase shift oscillator to generate a frequency of 1 kHz. Use equal

resistor and capacitor values for simplicity.
Solution:
We are required to design an RC phase shift oscillator to generate a frequency of:
E
f = 1 kHz = 1000 Hz
TT
The frequency of oscillation for a 3-stage RC phase shift oscillator is given by:

1 1
f= √ ⇒ RC = √
2πRC 6 2πf 6
NI

Substituting the known values:

1
RC = √ ≈ 6.49 × 10−5
2π · 1000 · 6
Let us choose:

C = 0.01 µF = 10−8 F

Then, the required resistance is:

6.49 × 10−5
R= = 6.49 × 103 = 6.49 kΩ
10−8
Final Component Values:

ˆ R = 6.49 kΩ
ˆ C = 0.01 µF
ˆ Number of RC stages = 3

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Circuit:

Figure 4.11: RC Phase Shift Oscillator

5. In a Hartley oscillator, the value of the capacitor in the tuned circuit is 500 pF, and
the two sections of the coil have inductances 38 µH and 12 µH. Find the frequency
of oscillations and the feedback factor β.
E
Solution:
1
TT
fo = √
2π LC
Where,
L = L1 + L2 = 38 × 10−6 + 12 × 10−6 = 50 × 10−6 H
NI

C = 500 pF

1
∴ fo = √
2π 50 × 10−6 × 500 × 10−12

= 1 MHz

Feedback factor β:
L1 38 × 10−6
β= = = 3.166
L2 12 × 10−6
6. A Hartley oscillator uses two inductors L1 = 10 µH, L2 = 40 µH, and a capacitor
C = 100 pF . Calculate the frequency of oscillation.
Solution: The frequency of oscillation is given by:
1
f= p
2π (L1 + L2 )C

Substitute the values:

ˆL1 + L2 = 50 µH = 50 × 10−6 H

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ˆ C = 100 pF = 100 × 10 −12

F

1 1
f= p = √
−6 −12
2π (50 × 10 ) · (100 × 10 ) 2π 5 × 10−15

1 1
f= ≈ ≈ 2.25 MHz
2π · 7.07 × 10−8 4.44 × 10−7
7. Design a Hartley oscillator to operate at f = 1 MHz using a capacitor C = 100 pF.
Determine the total inductance L1 + L2 .
The frequency of oscillation for a Hartley oscillator is given by:
1
f= p
2π (L1 + L2 )C

Rearranging to solve for L1 + L2 :

1
L1 + L 2 =
(2πf )2 C

Substitute the known values:

E
ˆ f = 1 MHz = 1 × 10 Hz 6

ˆ C = 100 pF = 100 × 10
TT
−12
F

1
L1 + L2 =
(2π · 106 )2 · 100 × 10−12
NI

1 1
= −12
= 2
(4π 2 · 1012 ) · 100 × 10 4π · 100

1
≈ ≈ 2.53 × 10−4 H = 2.53 µH
394.78
Therefore, the total inductance should be:

L1 + L2 = 2.53 µH

8. A Colpitt’s oscillator uses an inductor L = 1 mH, and two capacitors: C1 = 100 pF,
C2 = 200 pF. Calculate the frequency of oscillation.
Solution: Given:

L = 1 mH = 1×10−3 H, C1 = 100 pF = 100×10−12 F, C2 = 200 pF = 200×10−12 F

The equivalent capacitance of C1 and C2 in series is given by:

C1 · C 2 100 × 10−12 · 200 × 10−12 2 × 10−20

Ceq = = −12 −12
= −10
= 6.67 × 10−11 F
C1 + C 2 100 × 10 + 200 × 10 3 × 10

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The frequency of oscillation is:

1 1 1
f= p = √ = √
2π L · Ceq 2π 1 × 10−3 · 6.67 × 10−11 2π · 6.67 × 10−14

1 1
f= −7
≈ ≈ 195 kHz
2π · 8.17 × 10 5.13 × 10−6

f ≈ 195 kHz

9. Design a Colpitt’s oscillator to operate at a frequency of f = 1 MHz using an

inductor of L = 10 µH. Choose the capacitors such that C1 = 2C2 . Find the values
of C1 and C2 .
Solution: The frequency of oscillation for a Colpitt’s oscillator is given by:
1
f= p
2π L · Ceq

where Ceq is the equivalent capacitance of C1 and C2 in series:

C1 · C 2
Ceq =
E
C1 + C 2
TT
Given that C1 = 2C2 , we substitute:

2C2 · C2 2C22 2
Ceq = = = C2
2C2 + C2 3C2 3
NI

Substitute into the frequency formula:

 2
1 3 1
f= q ⇒ C2 =
2π L · 23 C2 2L 2πf

Now, substituting the known values L = 10 × 10−6 H, and f = 1 × 106 Hz:

 2
3 1 3 1
C2 = −6
· 6
= −6
· 2
2 · 10 × 10 2π · 10 20 × 10 4π · 1012

3
C2 ≈ ≈ 0.38 × 10−9 = 380 pF
7895.68 × 106

C1 = 2C2 = 2 × 380 pF = 760 pF

C1 = 760 pF, C2 = 380 pF

Circuit:

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Figure 4.12: Colpitts Oscillator

10. In a Colpitts oscillator, C1 = 100 pF, C2 = 260 pF. Find the value of L if the
frequency of oscillations is 40 kHz.
E
Given:
TT
C1 = 100 pF, C2 = 260 pF, f = 40 kHz

Frequency of oscillation:
1
f= p
2π LCeq
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Where
C1 C2
Ceq =
C1 + C 2

100 × 10−12 × 260 × 10−12

Ceq = = 37.5 pF
100 × 10−12 + 260 × 10−12
To find L, square both sides:

1
f2 =
4π 2 LCeq

1
⇒L=
4π 2 f 2 C eq

1
L=
4π 2 (40 × 103 )2 (37.5 × 10−12 )

∴ L = 0.422 H

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11. In a colpitt’s oscillator, L = 5mH. Find the C1 and C2 if the frequency of oscillation
is f = 50 kHz. Assume a feedback factor of β = 10%.

L = 5 mH f = 50 kHz, β = 10% = 0.1

1
f= p
2π LCeq

C1 C2
Cequ =
C1 + C 2
Squaring f both sides,

1
f2 =
4π 2 LCeq

1 1
Cequ = =
4π 2 f 2 L 4π 2 × (50 × 103 )2 × 5 × 10−3

Cequ = 2 · 02nF
E
C1 C2 C2
TT
Cequ = , β = 0.1 =
C1 + C 2 C1

C2 = 0.1C1
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C1 C2 C1 × 0.1C1 0.1C1
Cequ = = =
C1 + C 2 1.1C1 1.1

0.1C1
2.02 nF =
1.1

∴ C1 = 22 · 22 nF

⇒ C2 = 0.1 × 22 · 22 nF = 2 · 22 nF

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Chapter 5

Fundamentals of Communication
and Embedded Systems

5.1 Introduction
Communication is the basic process of exchange of information or transmission of in-
formation from one point to another. Basically, the information is generated from the
thought process in the human mind and it is sent to the receiver in the form of speech,
sign or in any other understandable form.
E
Communication enters our daily life in many different ways – such as telephone, ra-
TT

dio, TV, computers. . . etc. Communication provides directions for ships, aircrafts, rockets
and satellites in space. A number of modern communication systems include mobile com-
munication, point to point communication, radio telemetry and so on. Communication
need not directly involve human beings always. For example communication between
NI

two or more computers, the human decision/intervention is required only while giving
commands or to monitor the results.

5.2 Basic Blocks of Communication Systems

Irrespective of the applications, basic blocks of electronic communication system is as
shown in figure 5.1. This involves transmitter, channel and receiver. The transmitter is
located in one point and the receiver is located somewhere else and the channel is the
medium that connects them.
The elements of communication system are as follows:

ˆ Information
ˆ Transmitter
ˆ Communication channel or medium
ˆ Noise
ˆ Receiver

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Figure 5.1: Block diagram of communication system

Information: Information or message to be communicated are generated from infor-

mation sources. Examples for main sources of information are human brain or changes
in the physical environment. Information may be the speech signal, image, data music,
video etc. The amount of information is measured in bits.

Transmitter: The information generated from a source is not in a suitable form

to be transmitted directly through the channel. The transmitter is an electronic circuit
designed to convert the information into a signal suitable to be transmitted over a given
communication channel. Signal in its original form will be non-electrical in nature, such
E
signal cannot be transmitted through the channel. Using suitable transducers the mes-
sages are converted to the electrical form and then they are processed and coded before
TT

the transmission. The signal processing techniques are also applied at this stage to make
the communication more effective. Transmitter includes – transducer, modulator, filters,
encoder and also amplifiers to ensure faithful signal transmission and reception.
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Communication channel: The communication channel is the medium through

which the electronic signal is transmitted. The channel connects the transmitter and
receiver either through wire or without wire.

In general the communication channel can be classified as:

ˆ Wired channel or line communication

ˆ Wireless channel or radio channel
Wired channel: The examples for a wired medium are: copper wire, coaxial cable,
fibre optic cable. For applications like telephony two physical wires or conductors are
connected between the transmitter and the receiver. Latest applications use optical fibre
cables, which are well known for their high capacity and immunity to noise. In optical
fibres the information will be transmitted in the form of light wave. Coaxial cables are
preferred over pair of wires as they have higher bandwidth and lower losses. Optical fibres
are logical extension of coaxial cables which can be operated at higher frequencies and
greater bandwidths. Optical fibres are also cheaper and are more immune to interference
and noise.

Wireless channel: most commonly known as radio channel or electromagnetic

medium. This type of channel connects the transmitter and receiver wirelessly. No

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physical wire is necessary to carry the information, signal is sent through air or free
space. Radio communication requires two antennas for the transmission and reception.
The signal received at the receiving antenna will be attenuated and hence its amplitude
will be smaller. With proper amplification, the signal will be processed further to get
back the original information. Radio communication allows the signal to be transmitted
to any longer distance – thousands of kilometres, perhaps even more.

Noise: Noise is basically any unwanted signal that disturbs the communication. Noise
enters the communication system normally in the medium or channel. Noise may also
be generated at the transmitter or receiver. Means noise can be internally generated in
a system or externally added to the signal.

Noises can also be classified as natural noise and man-made noise. Natural
noise includes – lightening during rainy season, radiations from the sun and cosmic
radiations. Man-made noise is the noise generated by the electric ignition systems,
industrial noise, fluorescent lights etc. Noise imposes serious problem on electronic com-
munication systems, if not controlled. Noise cannot be completely eliminated, but its
effect can be reduced using different methods.

Receiver: The receiver is a collection of electronic circuits designed to convert the

signal back to its original form. The process includes amplification, mixing, demodula-
E
tion and decoding etc. The receiver performs the task of operating on the received signal
to generate the estimation of the original signal. If the estimated signal is same as the
TT

original transmitted signal, then we say that the reception is proper.

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5.3 Modulation
The transmission of an information- bearing signal over a communication channel requires
a shift in the range of frequencies from the original to another frequency range suitable
for transmission. This is accomplished through the process of modulation. Modulation
is defined as the process by which some characteristic of a carrier signal is varied in
accordance with a modulating signal. The message signal is referred to as modulating
signal and the result of modulation is referred to as modulated signal. The carrier signal
is usually a high frequency signal than the message signal. The message signal modifies
the amplitude, frequency or phase of the carrier signal in the process of modulation.
Hence, the types of modulation are:

1. Amplitude modulation – amplitude of the carrier is varied in accordance with the

modulating signal, keeping the frequency and phase of the carrier constant

2. Frequency modulation – the frequency of the carrier signal is varied according to

the modulating signal

3. Phase modulation – phase of the carrier is varied in accordance with the modulating
signal.

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5.3.1 Need for modulation

The message signal cannot be transmitted in its direct form, over the communication
channel. It should be modulated suitably. The advantages of the modulation are:
1. Reduces the antenna height
2. The range(distance) of communication can be increased
3. Signals can be multiplexed
4. Bandwidth can be used efficiently
5. Quality of reception can be improved
6. Avoids mixing of the signals
Height of the antenna: Minimum height of the antenna for proper transmission
and reception is λ/4, where λ is the wavelength. We know that, λ = c/f, where c is
velocity of light and f is the frequency. At lower frequencies wavelength is high and an-
tenna height is also high. Hence by modulating the message signal using a high frequency
carrier, the height of the antenna can be decreased.

Range of communication: Since message signal frequency range is low (20 Hz to

E
20 kHz), the possibility of signal attenuation is more. Modulation increases the frequency
and hence the range of communication may be increased.
TT

Multiplexing: modulation allows the multiplexing of signals. Multiplexing means

two or more message signals are transmitted simultaneously over the same channel. Eg:
broadband data services, TV channels operating simultaneously, radio stations in MW
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and SW band simultaneously.

Bandwidth utilization: Bandwidth of the modulated signal can be made smaller

or larger than the original signal.

Quality of reception: by using specific types of modulation schemes such as FM,

noise performance of the receiver can be improved.

Avoids mixing: The message signal frequencies are located within the range from 20
Hz to 20 kHz. Simultaneous transmission of multiple message signals may lead to mixing
of the signals, which may cause interference in the reception. Instead, if each message
signal is modulated separately using different carrier frequencies, then each signal will
be located at different portions in the spectrum. The receiver tuned to particular carrier
will be able to receive the signal. Therefore modulation avoids mixing of signals.

5.4 Telecommunication
There are many applications of communication systems, but telecommunication is the
most widely used application as it connects the people around the globe. The communi-
cation device used for this communication device is ‘telephone’. If the wireless commu-
nication is taking place with the movement of the communication devices, it is referred

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to as mobile communication. Today the telephone is replaced by a mobile phone and

communication is still possible with the movement of the sending or receiving end devices
or both.

If the mobile communication involves mobile devices and a coordinator station called
base transceiver station or base station within a small geographical area, the commu-
nication is cellular communication. Each cellular base station is allocated a group
of radio channels to be used within a small geographic area called a cell. The scheme
started initially for voice transmission. But, today it has been providing internet service,
transmission of audio, image and video.

5.5 Cellular Communication System

Figure 5.2 shows the block diagram of a cellular communication system in which the
hexagon shaped cells are shown. The automobile (mobile user with the mobile device)
shown in the figure wirelessly communicate when it moves from one cell to another cell.
The base stations of the respective cell connect the mobile devices using Radio Frequency
(RF) link. The base stations are controlled by Mobile switching centres (MSC) which
are connected to the existing telephone system referred to as Public Switched Telephone
Network (PSTN). Base station is provided with a call/data communication handling pro-
cessor.
E
TT
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Figure 5.2: Cellular communication system

RF linkage using Base station and Mobile station: The entire radio frequency spec-
trum is divided into small frequency bands. The RF connectivity is established by the
MSC with the help of Base station when a call is to be established. It assigns an available
frequency band (channel), out of the entire bandwidth to the mobile unit temporarily till
the end of the call.
Hand-off process: Whenever a mobile user crosses one cell boundary and moves to
another cell with an active call, the call is softly handed over to a new frequency band.

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the MSC adjusts the transmitted power of the mobile phone and changes the channel
of the mobile unit and base stations in order to maintain call quality. This is called a
hand-off in mobile communication.

5.5.1 Different events between the mobile unit and a cellular

system while a phone number is entered
Before the MSC connects to an available frequency band, the initial handshaking is
achieved by 4 different frequency bands or channels. They are shown in Table 5.1.

Table 5.1: Channels for initiating the call and voice transmission

Type of Channels Name of the Channel Channels used for:

Forward Control Channel (FCC) Initiating mobile calls from
Control channels
the base station to mobiles.
Reverse Control Channel (RCC) Initiating mobile calls from
the mobiles to base station.
Forward Voice Channel (FVC) Voice transmission from the
Voice channels
base station to mobiles.
Reverse Voice Channel (RVC) Voice transmission from
mobiles to the base station.
E
When a mobile originates a call,
TT

1. A call initiation request is sent on the reverse control channel.

2. With this request the mobile unit transmits its telephone number- Mobile Identifi-
cation Number (MIN), Electronic Serial Number (ESN), and the telephone number
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of the called party.

3. The mobile also transmits a station class mark (SCM) which indicates what the
maximum transmitter power level is for the particular user.

4. The cell base station receives this data and sends it to the MSC.

5. The MSC validates the request, makes connection to the called party through the
PSTN,

6. Now, MSC instructs the base station and mobile user to move to an unused forward
and reverse voice channel pair to begin the for conversation. Explain

5.5.2 Frequency reuse

Cellular systems have grown Figure 3 illustrates the concept of cellular frequency reuse,
with the hexagon shaped cells. In the Figure 5.3, cells numbered from A – G forms a
group of cells called Cluster. There are 3 such clusters shown in the Figure, with the
frequency bands repeated. Cells with the same letter use the same set of frequencies. A
cell cluster is outlined in bold and replicated over the coverage area. The N cells which
collectively use the complete set of available frequencies is called a cluster.

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Figure 5.3: Frequency Reuse

From the Figure, it is clear that

1. A cluster uses frequency bands A – G is not repeated in the adjacent cells.

E
2. The frequency bands are repeated only in the next cluster.
TT
The number of cells in a cluster is cluster size, denoted as ‘N. Frequency reuse factor is
the reciprocal of cluster size. Frequency reuse factor = 1/N. In this example, the cluster
size, N, is equal to seven, and the frequency reuse factor is 1/7, since each cell contains
one-seventh of the total number of available channels.
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5.5.3 Why a cell is hexagon in shape?

A cell must be designed to serve the weakest mobiles located at the edge of the cell. The
hexagonal cell shape is conceptual. Thus, when considering geometric shapes, the entire
region is to be covered without overlap and with equal area, A circle may be thought of
to represent the coverage area of a base station, but adjacent circles cannot be overlaid
upon a map without leaving gaps creating overlapping regions.
There are three sensible choices:

1. A square;

2. An equilateral triangle;

3. A hexagon.

Theoretically, the radiation zone cannot be represented by a square or triangle. The

hexagon permits easy and manageable analysis of a cellular system. For a given distance
between the center of a polygon and its farthest perimeter points, the hexagon has the
largest area. The hexagon closely approximates a circular radiation pattern. Using this,
the fewest number of cells can cover a geographic region, which would occur for an omni-
directional base station antenna.

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5.6 Embedded Systems

An Electronic/Electro mechanical system which is designed to perform a specific function
and is a combination of both hardware and firmware (Software) e.g: Electronic Toys,
Mobile Handsets, Washing Machines, Air Conditioners, Automotive Control Units, Set
Top Box, DVD Player etc. Embedded Systems are:
ˆ Unique in character and behavior
ˆ With specialized hardware and software
5.6.1 Elements of Embedded Systems
An embedded system is a combination of 3 things, Hardware Software Mechanical Com-
ponents and it is supposed to do one specific task only. The main components of the
embedded systems are shown in Figure 5.4:

E
TT
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Figure 5.4: Elements of Embedded System

ˆ System core
ˆ Input ports
ˆ Output ports
ˆ Memory
ˆ Other devices
System core: A typical embedded system contains a single chip controller which acts
as the master brain of the system. The controller can be a Microprocessor or a microcon-
troller or a Field Programmable Gate Array (FPGA) device or a Digital Signal Processor
(DSP) or an Application Specific Integrated Circuit (ASIC)/ Application Specific Stan-
dard Product (ASSP).

Input and Output ports: Embedded hardware/software systems are basically de-
signed to regulate a physical variable or to manipulate the state of some devices by

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sending some control signals to the Actuators or devices connected to the o/p ports of
the system, in response to the input signals provided by the end users or Sensors which
are connected to the input ports.

Keyboards, push button switches, etc. are examples for common user interface input
devices whereas LEDs, liquid crystal displays, piezoelectric buzzers, etc. are examples
for common user interface output devices for a typical embedded system. For exam-
ple, if the embedded system is designed for any handheld application, such as a mobile
handset application, then the system should contain user interfaces like a keyboard for
performing input operations and display unit for providing users the status of various
activities in progress. The requirement of type of user interface changes from application
to application based on domain.

Some embedded systems do not require any manual intervention for their operation.
They automatically sense the input parameters from real world through sensors which
are connected at input port. The sensor information is passed to the processor after
signal conditioning and digitization. The core of the system performs some predefined
operations on input data with the help of embedded firmware in the system and sends
some actuating signals to the actuator connect connected to the output port of the system.

Memory: The memory of the system is responsible for holding the code (control al-
E
gorithm and other important configuration details). There are two types of memories are
used in any embedded system. Fixed memory (ROM) is used for storing code or program.
TT

The user cannot change the firmware in this type of memory. The most common types
of memories used in embedded systems for control algorithm storage are OTP, PROM,
UVEPROM, EEPROM and FLASH.
NI

Other devices: The other system components refer to the components which are
necessary for the proper functioning of the embedded system. Some of these circuits may
be essential for the proper functioning of the processor/controller and firmware execu-
tion. Watchdog timer, Reset IC (or passive circuit), brown-out protection IC (or passive
circuit), etc. are examples of circuits/ICs which are essential for the proper functioning
of the processor/controllers.

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5.6.2 Difference between Microprocessor and Microcontroller

Table 5.2: Microprocessor Vs Microcontroller

Microprocessor Microcontroller
It is a heart of computing system It is a heart of embedded system
Memory and I/O components have It has internal Memory and I/O
to be connected externally components
Due to the external components, Power consumption is less
power consumption is high
Relatively slower Fast
It has less number of registers, hence
It has more number of registers,
more operations are memory-based hence the progrma are easier to
write.
Program and data are stored in same Program and data are stored in sep-
memory arate memory
Mainly used in the personal comput- Mainly used in washing maschine,
ers MP3 players.
cost is high E cost is low

5.6.3 Sensors and Actuators

ˆ Embedded system is in constant interaction with the real world
TT

ˆ Controlling/monitoring functions executed by the embedded system is achieved in

accordance with the changes happening to the Real World.
ˆ The changes in the system environment or variables are detected by the sensors
NI

connected to the input port of the embedded system.

ˆ If the embedded system is designed for any controlling purpose, the system will
produce some changes in controlling variable to bring the controlled variable to the
desired value.
ˆ It is achieved through an actuator connected to the out port of the embedded
system.

Sensors:
ˆ A transducer device which converts energy from one form to another for any mea-
surement or control purpose. Sensors acts as input device.
ˆ Example: IR, humidity, PIR(passive infra red) , ultrasonic , piezoelectric , smoke
sensors.
Actuators:
ˆ A form of transducer device (mechanical or electrical) which converts signals to
corresponding physical action (motion). Actuator acts as an output device
ˆ Eg. Electric motor, sliding doors, Escalators, Adjusting the Car Seat.
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[3] “Op-Amps and Linear Integrated Circuits”, Ramakanth A Gayakwad, Pearson, 4th
Edition, [Link] Journal of Library Science, Vol. 3, No. 1, 2020.

[4] “Introduction to Analog and Digital Communications “Simon Haykin, Wiley Pub-
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[5] Wireless Communications: Principles and Practice”, Theodore Rappaport, Pearson,

2nd Edition, 2016.
E
[6] “Introduction to Embedded Systems”, Shibu K V,TATA Mc Graw Hill Edu,2nd Edi-
TT
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[7] Electronic Devices”Thomas L Floyd,Pearson,9th , 2012

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