8085 Interrupt Structure 4.1 Polling and Interrupts + Litenever more than one VO devices are connected to a microprocessor based system, any one of the I/O devices may ask service at any time. There are two methods in which the micsoprocessor can service these /O devices. One method is to use the polling routine, while the other method employs interrupt. + In the polling routine the microprocessor checks whether any of the V/O devices is requesting for service. + The polling routine is a simple program that keeps a check for the occurrences of interrupt. For e.g. : Let us assume that our polling routine is servicing /O ports 1, 2, 3,..-.seuee8 ‘The polling routine will check the status of the /O ports in a proper ; sequence. + The polling routine will first transfer the status of the /O port 1 to the accumulator. It then checks the contents of accunmulator to determine if the service request bit is set. If the bit is set then V/O port 1 service routine is called, otherwise the polling routine will move forward to check if port 2 is requesting service. On completion of the service to portl, the polling routine will test port2. The process is repeated till all the 8 ports are tested and all the /O ports those are demanding service are processed. On completion of the polling routine, the microprocessor will resume with the execution of the program Fig. 4.1.1 shows the sequence for polling routine \ ‘The polling routine has priorities assigned to the different 1/0 devices. Once the routine begins port] will always be checked first, then port? and so on. Another way that allows the microprocessor to stop the execution of the program and give service to the VO devices is interrupt. It is an external asynchronous input that informs the microprocessor to complete the instruction that it is currently executing and fetch a new routine in order to offer service to the I/O device. Once the VO device is serviced, the microprocessor will continue with the execution of its normal program.Fig 4.1.1 : Polling sequence .2 Basic Definitions of Interrupts 4 Definitions 1. Interrupt : ‘is a mechanism by which an VO device (Hardware i instruction vare interrupt) can suspend the normal : one and get itself servi i 2 Interrupt service (SR) :|A small c Interrupt ens the corresponding interrupting vous caled aa anT when lllMicroprocessors & Interfacing (MDU) 4-3 q 808, 3. _ Vectored/Non-vectored interrupt e, Q. What are vectored and non-vectored interrupts ? "i the ISR address of an interrupt is to be taken from the ings Tis called as a non-vectored interrupt; else it is a vectored in, | When interrupt request is activated the microprocessor control machine cytle. During this cycle, it generates starting address “8 Sing, routine. These addresses are fixed for different interrupts, Thig ™ ita interrupt service routine is called as vector location and interme") x, vector locations are called as vectored interrupts. TTupts Which 4. Maskable/Non-maskable interrupt Interrupt that ean be masked (disabled) or unmasked (enabled) by is called as maskable interrupt; else it is anon maskable interrupt, The maskable and nonmaskable interrupts are enabled and disableq rogram control IF the particular flip-flops are set/reset the inter 4” masked/unt b TMDL In cases where an interrupt is masked, the microprocessor will not resyy interrupt even if the interrupt is agtivated| The interrupts which ean under the software control are called as maskable interrupts, 5 The interrupts-which cannot be masked under the software control are « nonmaskable interrupts Q.__ What is the difference between Non-maskable and maskable interrupt ? & Non-maskable (NMI) Maskable 1. Iecannot be masked offor made pending. | It can be masked off « pending. - 2. | This interrupt does not disable non- This interrupt . disabl: maskable interrupts. maskable interrupts. 3. [It is used for emergency purpose, like | It is used to interface pen power failure, smoke detector etc. 4. _| Higher priority. Lower priority. 5. | Raspones tine lo ba Response time is high: 4.3 8085 Interrupt Structure * 8085 supports two types of, interrupts. They are : * Hardware interrupts. + Software interrupts 4.3.1 Hardware Interrupts ve pil * Peripheral device activates interrupt by activating the ie j * "Te fetbonge to the interrupt request: microprocessor COM grams i execution in main program and transfe interrupt service routine. a ainterfacing (MDU) 44 8085 Interrupt Structure i sors mioroproces ine, required task is completed. ‘Task ma - Seti the status, to update the counter ete. save completing the tak, the rogram contol transferred back to the main 5 After co bi of interrupts where the microprocessor pins are used to receive * Fiperupt reyuas are called hardware inverropte ‘The microprocessor 8085 has five hardware interrupts they are vy be to read data, to write « The interrupt structure is a 5 level structure. « Fig. 4.3.1 shows the interrupt structure. Input pinMicroprocessors & Interfacing (MOU) 48 8085 interrupt Structure 4.3.1(A) TRAP It is anon maskable edge and level triggered interrupt. @ ne unaffected. 7 ‘any mask or interrupt enable. e TRAP sign: t make a LOW to HIGH transition and remain HIGH acknowledged. This avoids false triggering due to noise or glitches = It has the highest priority among all interrupts. This interrupt transfers the microprocessor’s control to location 0024H. Application It is used for emergency purpose like power failure, parity error checker, smoke detector etc. 4.3.1(B) RST 7.5 qt is maskable, edge triggered interrupt request input line. This interrupt is triggered at the rising edge of the signal. 2 It has highest priority among all maskable interrupts and second priority among all 4 interrupts. ‘The interrupt vector location for this interrupt is 003C H. Action taken by microprocessor, when it receives RST 7.5. StepI : The peripheral activates RST 7.5 signal to set R7.5 flip-flop. Step II : When R7.5 flip-flop is set and if INTE flip-flop is set and M7.5 mask latch is reset, the logic activates an internal RST 7.5 request signal. Step III: In response to this signal, the microprocessor completes current instruction cycle and calculate starting address of ISR. It activates RST 7.5 acknowledge and any interrupt acknowledge signals to reset ‘> R 7.6 and INTE flip-flops respectively. Step IV: ‘The microprocessor executes two memory write cycles to save contents __ of program counter on the stack and then executes corresponding ISR. Using SIM instruction the M65 and M5.6 flip flop can be set or reset and hence enable or disable RST [Link] 5.5. ; DI clears the interrupt enable flip flop, while EI sets the interrupt enable flip flop. and DI are instructions). ; Mrs ‘and interrupt enable flip flop together decide whether RST 7.5 is enabled or disabled. 4.3.1(C) RST 6.5 and RST 5.5 an ‘These are level triggered, maskable interrupt request input lines. RST 65 transfers microprocessor’s control to location 0084 HL while RST 5.5 transfers microprocessor’s control to location 002C HL ‘Action taken by microprocessor, when it receives RST 6.5 interrupt. : ivates RST 6.5 signal. StepI : The peripheral acti oes aenak Step II: When RST 6.5 pin is at logic 1, INTE si latch in reset, the lpi activates an internal RST 65 request seme Step III: ‘The microprocessor completes current instruction cycle ani pacts starting address of ISR: It:activates any interrupt acknowledge cycle reset INTE flip-flops. .8085 Interrupt structure Micro} . “s panera cycles to save contents of sponding ISR. t and hence : i tes two memory write Step IV: The microprocessor att nd then executes COrre! rogram counter on ! rad «Using SIM instruction the M6.6 and M6.6 flip flop can be set or enable or disable RST6Sand 5.5. ng intorrupt enable fip flop. enabled or * DI clears the interrupt enable flip flop, (EI and DI are instructions). . 5 i0 M75 and interrupt enable flip flop together decide whether RST 7.5 i disabled. true for RST < 4.3.1(D) INTR , + It is level triggered, maskable interrupt request input line. ; © This interrupt works in conjunction with RST N or CALL instruction. INTR pin is * The INTR logic consists of INTE flip-flop, OR gate and inverter. The i a logically ANDed with the output of INTE flip-flop. To activate an LT ed 7 request signal, the INTR pin should be held at logic 1 and INTE flip-flop sho 7 set. This flip-flop is set by executing El instruction. It is reset by executing DI. instruction. It is also reset by RESET IN or any interrupt acknowledge signal. In response to any interrupt the microprocessor resets an INTE flip-flop that means it disables all maskable interrupts. * Using SIM instruction the M6.5 and M5.5 flip flop can be set or reset and hence enable or disable RST 6.5 and RST'5.5. : * Di clears the interrupt enable flip flop, while EI, sets the interrupt enable flip flop. GI and DI are instructions). * M6.5 and M5.5 and interrupt enable flip flop together decide whether RST 6.5 and RST 55 are enabled or disabled. Action taken by the microprocessor when it receives an INTR. : StepI : The 8085 microprocessor checks for the status of the INTR signal while it executes each instruction. Step II : Ifthe INTR signal is high, then the microprocessor completes the execution of the current of the current instruction’ and in response to the INTR signal i an active low INTA interrupt acknowledge signal, if the interrupt is Step III: In response to the INTA signal, the external logi dees bus. In case of multibyte instruction, aie ees i cycl are generated by the microprocessor, in order to tranafe iti bytes to the microprocessor. additional Step IV: The 8085 then saves the address of i i the received inet ng of the next instruction onto the stack and 4.3.2. Software interrupts : Q___ Write a short note on the utility of software | © In case of software interrupts the : instruction. cause of the intei 85 Interrupt Structure Microprocessors & Interfacing (MDU) 410° eo 4.4 Software Interrupts . Q. What are restart instructions ? The 8085 microprocessor has eight instructions (RST 0 to RST 7) These instructions allow transfer of program control from main program to predefined service routine addresses. Predefined service routine is also referred to as ISR. . After completing the ISR program control is transferred back to main program. 8085 microprocessor provides eight software interrupts RST 0 to RST 7. These instructions are used to call interrupt service routines. Format of RST N instruction OPCODE is as follows : Di De Ds Dy Ds Dy Dy Dy BEISIN[Nitit2 ‘The vector locations, for RST N instruction are as follows : Instruction| __Addrees of ISR. I§/4o RSTO 0000H (8 x 0) = 0000H 2 RsT1 | .0008H @ x 1) = 0008H / RST2 0010H (8 x 2) = 00108 RST3 0018H (8 x 3) = 0018H RST4 0020H (8 x 4) = 0020H. RSTS (0028H (8 x 5) = 0028H RST6 Q030H (8 x 6) = 0030H RST7 0038H (8 x 7) = 0038H The difference between two successive locations instruction must be stored into corresponding control to user defined ISR addrese, " ‘The execution of RST instruction is as follows : Consider instruction, When RST 2 instruction is ftehed and executed by gOser got SST 2 Cee eres the Program conto is transfered, the earn rete 12 Cie. retmm addres) are stored onto stack. ARar the ISR cf Roe wee contents Program control is transferred back to main program, 48 completed the Software inforrupts are not used to handle asyachronous call software routines like single step, break Pointete, Vets: They are used to 16 ue sf ‘is only 8 bytes. Hence ju mp location to transfer microprocessor's411 acing (MOU) 2085, Microprocessors & interfacing ( ee TS paring Hardware Interrupt and Software Inte, 4.4.1 Com " Tt is synchronous event. Itis an synchronous even, —~\ = tt. is requested by | This interrupt is Tequestaq Bl reesting batctioa, device on a pin, by en PC is incremented. PC is not incremented. The microprocessor does not execute The microprocessor executes any interrupt acknowledge cycle or | interrupt acknowledge cycle Res a idle machine cycle to acknowledge | machine cycle to acknowledg. | this interrupt. The microprocessor | interrupt. 4 execute normal instruction cycle. 5._| It cannot be ignored or masked. It can be masked except for TRAP. 6 | It has highest priority among all | The priority is lower than that of ai interrupts. interrupt. : 7. | It does not affect on interrupt control | It affects on interrupt control logic. logic. 8. | It is not used to interface peripherals | It is used to interface periphera! that means it does not improve interrupt driven VO. It ime throughput of system. It is used in throughput of the system. program debugging. 4.5 Masking / Unmasking of Interrupts Q Explain RIM ond SIM instruction. How these instructions can be u%! enable/disable interrupts and for serial I/O ? Explain. For masking / unmasking of interrupts there are four instructions. + H+ Die RM.» SM 1. El: Enable interrupt This instruction is toe, : RST 65, RST55 a Se araapable interrupts. ae 7 * Whenever an interrupt is acknowledged, the interrupt enable SP" eset and all the interrupts are disabled. ot {i the interrupts are to be enabled, then the EI instruction is within the ISR.ee tefaeng (MDU) 412 8085 Interrupt Structure Interrupt ‘ , pisable Fon resets the interrupt enable flip-lop i.e. it can be used to pie qhis instruct gs Oey 75, RST G5, RST. and INTR interrupt disable pt Mask Tain RIM and SIM instruction. How there instructions can be used to Orie disable interrupts ond for serial 1/0? Explain, ‘used to enable / disable the RST 7.5, RST 6.5 and RST 5.5 This instruction is interrupts sei nstraction doesnot affect on the TRAP and INTR inputs * , Yeean also be used for serial data transmission YY ‘transfers the control word from accumulator to the interrupt control logic, TC rerrrererial control logic. So it is essential to load the (SIM format) contrel word into the accumulator before the execution of SIM instruction. f_-Serial port fs — Inu control logic ——+| contol Dy Ds O_O ~~ D, Dg Os 1 = Mask or disable 1=Enable serial port = Disable serial port (0 = Unmask or enable Dont care Mask sot enable 1 = Masking is enabled (0 = Masking is disabled Fig. 4.5.1 : SIM format + Bits D, and Dg are serial port control. ‘The SDE is enable bit used to enable/disable serial output data. If D, bit is enabled, D; bit is transferred to SOD pin. * Bit D, is R 7.5 part of interrupt control logic. It is used to reset R 7.5 flip flop regardless of RST 7.5 masking. * Bits Dy to Dp are part of interrupt control logic. These bits are used to mask RST5.5, RST 65 and RST 7.5 interrupts. The MSE bit is master control over M 7.5, M 6.5 and M 5.5 bits. If MSE = 0, the M bits have no effect, but if Example MSE 1 the M bits decides mask or ‘unmask of respective interrupts. | rmqusts mle RST 6.5 and diable RST 7.5 and RST 66 the following SIM format is if f= SDE X R75 MSE M76 M65 M55 =0DH a oTojfoypo,i[i]Jo|[4} sig MODE: Load SIM format in accumulator . Set interrupt maskMicroprocessors & Interfacing (MOU) 413 8085 Interrupt 4, RIM: Read Interrupt Mask 6) ~ This instruction is used to check the status of all pending and maskable interrupts. Ten also transfer serial data bit from the serial input data line (SID) to the D, bit of the accumulator A This instruction transfers the contents of the interrupt control logic and serial control logic to the accurmulator. Hence, accumulator is loaded with the status format after execution of the RIM instruction. . ere can be more than one interrupt requests may occur. In such cases if the priority of interrupts is higher than they are serviced, if the interrupts are of lower priority then the 8085, stores the information about these interrupt requests. Such interrupts are called pending interrupt. The Programmer can monitor the ing i Sar —freee oj trtmypt _aj Dy De Dy Dy Dy “0, Oy [so[irs]res [rssh Jurs[uos]wss] Mask RST 5.5 ‘Mask RST 6.5 RST7.5 Mask RST 7.5 1 = Masked Setial input date aa 0= Unmasked RSTS.5 Interrupt enable 1 = INTE fip-op is set 11= Pending O=INTE filp-op is reset = Not active Fig. 45.2: RIM format + Bit D, is status of SID pin on serial port. When RIM instruction is executed the logic level of SID pin is copied at bit D;. « Bits Dg, Ds and D, are status of pending interrupts. If RST 7.5 and RST 5.5 inputs oceurs the 8085 will branch to ISR of RST 7.5. As the RST 5.5 is having less priority then RST 7.5 so it will be pending interrupt. When RIM instruction is executed the status of RST 7.5, RST 65 and RST 5.5 pending is copied at bits Ds, D, and D, respectively. * Bits D, to Dy are status of interrupt enable flip flop, mask 7.5, mask 6.5 and mask 5.5. When RIM instruction is executed the status of masking is loaded at bits D, to Dy. Example 7 (a) RIM i ion is executed and accumulator bit pattern is 0010 0000. The bit pattern i ites that RST 6.5 is pending interrupt. (bo) RIM ins is executed and accumulator bit pattern is 0000 1010. The bit pattern indi interrupt enable flip flop is set, RST 6.5 is masked while RST 7.5 masked. ts using the RIM