INTRODUCTION TO ARM CORTEX M3 PROCESSOR
The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The Cortex-M3 offers many new features,
including a Thumb- 2 instruction set, low interrupt latency, hardware divide,
interruptible / continuable multiple load and store instructions, automatic state save and restore for
interrupts, tightly integrated interrupt controller with Wake-up Interrupt Controller and multiple
core buses capable of simultaneous accesses. The processor has a Harvard architecture, which
means that it has a separate instruction bus and data bus. This allows instructions and data accesses
to take place at the same time, and as a result of this, the performance of the processor increases
because data accesses do not affect the instruction pipeline. This feature results in multiple bus
interfaces on Cortex-M3, each with optimized usage and the ability to be used simultaneously.
However, the instruction and data buses share the same memory space (a unified memory system).
In other words, you cannot get 8 GB of memory space just because you have separate bus
interfaces.
Figure 1: A Simplified View of the Cortex-M3
INTRODUCTION TO LPC1768
The LPC1768FBD100 is an ARM Cortex-M3 based micro controller for embedded
applications requiring a high level of integration and low power dissipation. The ARM Cortex-M3
is a next generation core that offers system enhancements such as modernized debug features and a
higher level of support block integration. LPC1768 operate up to 100 MHz CPU frequency. The
peripheral complement of the LPC1768 includes up to 512 kilo bytes of flash memory, up to 64KB
of data memory, Ethernet MAC, a USB interface that can be configured as either Host, Device, or
OTG, 8 channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers,
SPI interface, 3 I2C interfaces, 2-input plus 2- output I2S interface, 8 channel 12-bit ADC, 10-bit
DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output
general purpose PWM, ultra-low power RTC with separate battery supply, and up to 70 general
purpose I/O pins. The LPC1768 use a multi-layer AHB(Advanced High Performance Bus) matrix
to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that
optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be
accessed simultaneously by different bus masters.
On-chip flash memory system: The LPC1768 contains up to 512 KB of on-chip flash memory. A
flash memory accelerator maximizes performance for use with the two fast AHB Lite buses. This
memory may be used for both code and data storage. Programming of the flash memory may be
accomplished in several ways. It may be programmed In System via the serial port. The application
program may also erase and/or program the flash while the application is running, allowing a great
degree of flexibility for data storage field firmware upgrades, etc.
On-chip Static RAM: The LPC1768 contains up to 64 KB of on-chip static RAM memory. Up to
32 KB of SRAM, accessible by the CPU and all three DMA controllers are on a higher-speed bus.
Devices containing more than 32 KB SRAM have two additional 16 KB SRAM blocks, each
situated on separate slave ports on the AHB multilayer matrix. This architecture allows the
possibility for CPU and DMA accesses to be separated in such a way that there are few or no delays
for the bus masters.
SPECIFICATIONS OF ALS-SDA-ARMCTXM3-06
LPC1768 is ARM Cortex M3 based microcontroller with 512KB flash memory and 64KB
SRAM In-System Programming (ISP) and InApplication Programming (IAP) capabilities.
Single 3.3 V power supply (2.4 V to 3.6 V).
70 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open drain
mode, and repeater mode.
12-bit Analog-to-Digital Converter (ADC) and up to 8 analog channels. 10-bit Digital-to-
Analog Converter (DAC) with dedicated conversion timer.
Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs.
Four UART's with fractional baud rate generation, internal FIFO, IrDA.
SPI controller with synchronous, serial, full duplex communication.
Three enhanced I2C-bus interfaces
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power down.
Real-Time Clock (RTC) with a separate power domain.
Standard JTAG test/debug interface as well as Serial Wire Debug.
Four external interrupt inputs configurable as edge/level sensitive.
12MHz Crystal allows easy communication setup
One on board voltage regulator for generating 3.3V. Input to this will be from
External +5V DC Power supply through a 9-pin DSUB connector
Piggy Back module containing LPC1768 controller
Standard JTAG connector with ARM 2×10 pin layout for programming /debugging with
ARM-JTAG
Reset push-button for resetting the controller
One RS232 interface circuit with 9 pin DSUB connector: this is used by the Boot
loader program, to program LPC1768 Flash memory without external Programmer
DC motor interface with direction and speed control
Stepper motor interface with direction and speed control
16×2 alphanumeric LCD Display
On chip ADC interface circuit using AD0.5(P1.31)
8-bit DAC interface
4x4 Key-Matrix connected to the port lines of the controller
One External interrupt circuit with LED indication
Two-digit multiplexed 7-segment display interface
Interface circuit for on board Buzzer, Relay and Led indication controlled through
push button.
SPI Interface: 2 channel ADC IC with POT and Temperature sensor I2C Interface: NVROM
IC
Standard 26-pin FRC connectors to connect to on-board interface or some of ALS
standard External Interfaces.
A number of software examples in ‘C-language’ to illustrate the functioning of the
interfaces. The software examples are compiled using an evaluation version of KEIL4 ‘C’
compiler for ARM.
Compact elegant plastic enclosure
Optional USB to Serial interface (RS232) cable.
PLACEMENT DIAGRAM