HM6264A Series
8192-word × 8-bit High Speed CMOS Static RAM
Features Access
Type No. time Package
• Low-power standby
HM6264ASP-10 100 ns 300-mil, 28-pin
— 0.1 mW (typ)
plastic DIP
— 10 µW (typ) L-/LL-version HM6264ASP-12 120 ns (DP-28N)
• Low power operation
— 15 mW/MHz (typ) HM6264ASP-15 150 ns
• Fast access time
— l00/120/150 ns (max) HM6264ALSP-10 100 ns
• Single +5 V supply
• Completely static memory HM6264ALSP-12 120 ns
— No clock or timing strobe required
• Equal access and cycle time HM6264ALSP-15 150 ns
• Common data input and output, three-state
HM6264ALSP-10L 100 ns
output
• Directly TTL compatible HM6264ALSP-12L 120 ns
— All inputs and outputs
• Battery back up operation capability HM6264ALSP-15L 150 ns
(L-/LL-version)
HM6264AFP-10 100 ns 28-pin plastic
SOP *1
Ordering Information HM6264AFP-12 120 ns (FP-28D/DA)
Access HM6264AFP-15 150 ns
Type No. time Package
HM6264ALFP-10 100 ns
HM6264AP-10 100 ns 600-mil, 28-pin
plastic DIP HM6264ALFP-12 120 ns
HM6264AP-12 120 ns (DP-28)
HM6264ALFP-15 150 ns
HM6264AP-15 150 ns
HM6264ALFP-10L 100 ns
HM6264ALP-10 100 ns
HM6264ALFP-12L 120 ns
HM6264ALP-12 120 ns
HM6264ALFP-15L 150 ns
HM6264ALP-15 150 ns
Note: 1. T is added to the end of the type number
HM6264ALP-10L 100 ns for a SOP of 3.00 mm (max) thickness.
HM6264ALP-12L 120 ns
HM6264ALP-15L 150 ns
1
HM6264A Series HM6264A Series
Pin Arrangement
NC 1 28 VCC
A12 2 27 WE
A7 3 26 CS2
A6 4 25 A8
A5 5 24 A9
A4 6 23 A11
A3 7 22 OE
A2 8 21 A10
A1 9 20 CS1
A0 10 19 I/O8
I/O1 11 18 I/O7
I/O2 12 17 I/O6
I/O3 13 16 I/O5
VSS 14 15 I/O4
(Top view)
Block Diagram
A11
A8 VCC
A9 Row Memory array
A7 VSS
A12 decoder 256 × 256
A5
A6
A4
I/O1
Column I/O
Input Column decoder
data
control
I/O8
A1 A2A0A10 A3
CS2
Timing pulse generator
CS1
WE
OE
2
HM6264A Series HM6264A Series
Truth Table
WE CS1 CS2 OE Mode I/O pin VCC current Note
× H × × Not selected High Z ISB, ISB1
(power down)
× × L × High Z ISB, ISB1
H L H H Output disabled High Z ICC
H L H L Read Dout ICC Read cycle
L L H H Write Din ICC Write cycle 1
L L H L Write Din ICC Write cycle 2
Note: ×: Don’t care.
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Terminal voltage *1 VT –0.5 *2 to +7.0 V
Power dissipation PT 1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature (under bias) Tbias –10 to +85 °C
Notes: 1. With respect to VSS.
2. –3.0 V for pulse width ≤ 50 ns
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
VSS 0 0 0 V
Input voltage VIH 2.2 — 6.0 V
VIL –0.3 *1 — 0.8 V
Note: 1. –3.0 V for pulse width ≤ 50 ns
3
HM6264A Series HM6264A Series
DC and Operating Characteristics (VCC = 5 V ± 10%,VSS = 0 V, Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Test condition
Input leakage current |ILI| — — 2 µA Vin = VSS to VCC
Output leakage current |ILO| — — 2 µA CS1 = VIH or CS2 = VIL or OE = VIH or
WE = VIL, VI/O = VSS to VCC
Operating power ICCDC — 7 15 mA CS1 = VIL, CS2 = VIH, II/O = 0 mA
supply current
Average operating ICC1 — 30 45*5 mA Min. cycle, duty = 100%,
current — 30 55*6 CS1 = VIL, CS2 = VIH, II/O = 0 mA
ICC2 — 3 5 mA Cycle time = 1 µs, duty = 100%,
II/O = 0 mA, CS1 ≤ 0.2 V,
CS2 ≥ VCC – 0.2 V, VIH ≥ VCC – 0.2 V,
VIL ≤ 0.2 V
Standby power supply ISB — 1 3 mA CS1 = VIH or CS2 = VIL
current
ISB1 *2 — 0.02 2 mA CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or
————————————
— 2*3 100*3 µA 0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin
—————————
— 2*4 50*4
Output voltage VOL — — 0.4 V IOL = 2.1 mA
VOH 2.4 — — V IOH = –1.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = 25°C and not guaranteed.
2. VIL min = –0.3 V
3. These characteristics are guaranteed only for the L-version.
4. These characteristics are guaranteed only for the LL-version.
5. For 120 ns/150 ns version.
6. For 100 ns version.
Capacitance (f = 1 MHz, Ta = 25°C)*1
Parameter Symbol Typ Max Unit Test condition
Input capacitance Cin — 5 pF Vin = 0 V
Input/output capacitance CI/O — 7 pF VI/O = 0 V
Note: 1. This parameter is sampled and is not 100% tested.
4
HM6264A Series HM6264A Series
AC Characteristics (VCC = 5 V ± 10%, Ta = 0 to +70°C)
AC Test Conditions:
• Input pulse levels: 0.8 V/2.4 V
• Input rise and fall time: 10 ns
• Input timing reference level: 1.5 V
• Output timing reference level
— HM6264A-10: 1.5 V
— HM6264A-12/15: 0.8 V/2.0 V
• Output load: 1 TTL gate and CL (100 pF) (including scope and jig)
Read Cycle
HM6264A-10 HM6264A-12 HM6264A-15
——————— ——————— ———————
Parameter Symbol Min Max Min Max Min Max Unit
Read cycle time tRC 100 — 120 — 150 — ns
Address access time tAA — 100 — 120 — 150 ns
Chip selection to output CS1 tCO1 — 100 — 120 — 150 ns
CS2 tCO2 — 100 — 120 — 150 ns
Output enable to output valid tOE — 50 — 60 — 70 ns
Chip selection to output CS1 tLZ1 10 — 10 — 15 — ns
in low Z
CS2 tLZ2 10 — 10 — 15 — ns
Output enable to output in low Z tOLZ 5 — 5 — 5 — ns
Chip deselection to CS1 tHZ1 0 35 0 40 0 50 ns
output in high Z
CS2 tHZ2 0 35 0 40 0 50 ns
Output disable to output in high Z t 0 35 0 40 0 50 ns
OHZ
Output hold from address change t 10 — 10 — 10 — ns
OH
Notes 1. tHZ and tOHZ are defined as the time at which the outputs to achieve the open circuit
condition and are not referred to output voltage levels.
2. At any given temperature and voltage condition, tHZ maximum is less than tLZ minimum both for
a given device and from device to device.
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HM6264A Series HM6264A Series
Read Timing Waveform
tRC
Address
tAA
tCO1
CS1
tLZ1
tCO2 tHZ1
CS2 tLZ2
tOE tHZ2
tOLZ
OE
tOHZ
Dout Valid Data
tOH
Note: WE is high for read cycle.
Write Cycle
HM6264A-10 HM6264A-12 HM6264A-15
——————— ——————— ———————
Parameter Symbol Min Max Min Max Min Max Unit
Write cycle time tWC 100 — 120 — 150 — ns
Chip selection to end of write tCW 80 — 85 — 100 — ns
Address setup time tAS 0 — 0 — 0 — ns
Address valid to end of write tAW 80 — 85 — 100 — ns
Write pulse width tWP 60 — 70 — 90 — ns
Write recovery time tWR 0 — 0 — 0 — ns
Write to output in high Z tWHZ 0 35 0 40 0 50 ns
Data to write time overlap tDW 40 — 40 — 50 — ns
Data hold from write time tDH 0 — 0 — 0 — ns
Output enable to output in high Z tOHZ 0 35 0 40 0 50 ns
Output active from end of write tOW 5 — 5 —— 5 — ns
6
HM6264A Series HM6264A Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
OE tCW *2 tWR *4
CS1
*6
CS2
tAW
tAS *3 tWP *1
WE
tOHZ *5
Dout tDW tDH
Din Valid Data
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HM6264A Series HM6264A Series
Write Timing Waveform (2) (OE Low Fix)
tWC
Address
tAW
tWR *4
tCW *2
CS1 *6
tCW *2
CS2
tWP *1
WE tAS *3 tOH
*5 tWHZ tOW
*7 *8
Dout
tDW tDH
*9
Din Valid Data
Notes: 1. A write occurs during the overlap of a low CS1, a high CS2, and a low WE. A write begins
at the latest transition among CS1 going low, CS2 going high and WE going low. A write
ends at the earliest transition among CS1 going high, CS2 going low and WE going high.
Time tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end
of the write cycle.
5. During this period, I/O pins are in the output state, therefore the input signals of opposite
phase to the outputs must not be applied.
6. If CS1 goes low simultaneously with WE going low or after WE goes low, the outputs
remain in high impedance state.
7. Dout is the same phase of the latest written data in this write cycle.
8. Dout is the read data of the next address.
9. If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals
of opposite phase to the outputs must not be applied to I/O pins
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HM6264A Series HM6264A Series
Low VCC Data Retention
In data retention mode, CS2 controls the address, CS2 ≥ VCC – 0.2 V or CS2 ≤ 0.2 V. The other
WE, CS1, OE, and the Din buffer. If CS2 controls input levels (address, WE, OE, I/O) can be in the
data retention mode, Vin (for these inputs) can be high impedance state.
in the high impedance state. If CS1 controls the
data retention mode, CS2 must satisfy either
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only L/LL-version.
Parameter Symbol Min Typ Max Unit Test Condition
VCC for data retention VDR 2.0 — — V CS1 ≥ VCC – 0.2 V,
CS2 ≥ VCC– 0.2 V, or
CS2 ≤ 0.2 V
Data retention current ICCDR — 1*1 50*1 µA VCC = 3.0 V,
CS1 ≥ VCC – 0.2 V,
— 1*2 25*2 CS2 ≥ VCC – 0.2 V, or
0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin
Chip deselect to data t 0 — — ns See retention waveform
CDR
retention time
Operation recovery time tR t *3 — — ns See retention waveform
RC
Notes: 1. VIL min = –0.3 V, 20 µA max at Ta = 0 to 40°C. These characteristics are guaranteed only for
the L-version.
2. VIL min = –0.3 V, 10 µA max at Ta = 0 to 40°C. These characteristics are guaranteed only for
the LL-version.
3. tRC = Read cycle time.
Low VCC Data Retention Waveform (1) (CS1 Controlled)
tCDR Data retention mode tR
VCC
4.5 V
2.2 V
VDR
CS1
CS1 ≥ VCC – 0.2 V
0V
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HM6264A Series HM6264A Series
Low VCC Data Retention Waveform (2) (CS2 Controlled)
VCC Data retention mode
4.5 V
tCDR tR
CS2
VDR
0.4 V
CS2 ≤ 0.2 V
0V
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