Aditya (Slot 1: 0:00 - 2:00) - Slides 1 & 2

"Good morning, investors. Today, our team is pitching a research proposal

titled 'Temperature-Aware Ring Oscillator Based PUF for Reliable and Secure
IoT Systems'. We are here to solve a fundamental, expensive flaw in how the
world handles hardware security.

Here is the reality of modern cybersecurity: the weak link isn't the lock, and it
isn't the key. The mathematical algorithms we use to encrypt data are
virtually unbreakable. The real vulnerability is where we put the key. Right
now, smart devices and industrial sensors store their cryptographic keys in
Non-Volatile Memory. It is the equivalent of installing a billion-dollar titanium
vault, and then leaving the passcode written on a sticky note taped to the
front door. Hackers don't bother picking the mathematical lock; they use
physical attacks to just extract the memory and steal the sticky note.

The modern engineering solution is to throw away the sticky note entirely.
We use a 'PUF'—a Physical Unclonable Function. Think of it like a microscopic
biometric fingerprint born from the tiny manufacturing imperfections inside
the silicon chip itself. The chip doesn't store the password ; the chip is the
password.

We are focusing on a specific architecture called a Ring Oscillator PUF, which

works by racing two electrical signals against each other to generate a stable
'0' or '1' for that password. But there is a fatal flaw: when these chips get hot
or cold, their internal physics change. The race tracks expand and contract
differently. The speeds shift, the fingerprint changes, and the security
completely locks you out. A device that works perfectly at 20 C will generate
an entirely different key at 70 C."

(Switch!)

Ayush Script (Slot 1: ~2:00 - ~4:00)

Covers: Literature Review, Gaps, Objectives, & Questions

(Speaker 1 steps back. Speaker 2 steps up immediately without saying

"thank you".)

"That temperature failure is exactly where current engineering drops the ball.

If you look at the literature review table behind me, you'll see the industry's
two favorite, flawed band-aids. First, they use fixed, static pairings
established in the factory. But those absolutely cannot adapt to rapid
temperature spikes out in the real world. Second, when the passwords
inevitably flip, they try to patch the errors by burning massive amounts of
expensive hardware space on Error Correction Codes, or ECC.

Now, for context, the physical hardware board we are building this on is
called an FPGA—a Field Programmable Gate Array. Think of an FPGA as a
blank-slate microchip that we can physically rewire on the fly using code.
Current research wastes the valuable 'real estate' on these FPGA boards to
build bulky ECC padlocks. They are completely ignoring the free processors
already sitting on the board—like the ARM cores—that could handle this logic
efficiently.

That gap is our entry point. Our objectives are:

First, we engineer the physical hardware. Instead of letting standard software

auto-generate a messy layout, we are manually building perfectly
symmetrical logic blocks inside the chip. We call these Configurable Ring
Oscillators. Think of them as perfectly identical electrical race tracks.

Second, we develop the software brain. We are writing a custom firmware

algorithm that tests these tracks and pairs up the ones that expand and
contract at the exact same rate when exposed to heat. If they drift together,
the generated password stays perfectly stable.

Third, we validate it in the real world. We aren't just running computer

simulations. We are aiming to achieve over 98% native reliability while
physically testing these chips in extreme environments, spanning from 0°C
all the way to 80°C."

To pull this off, our research centers on answering two critical questions:
First: Can taking manual control of the FPGA's physical floorplan actually beat
automated software routing when it comes to thermal stability? And second:
Can we run an advanced statistical test—the SPRT algorithm—on the ARM
processor to completely eliminate the need for those bloated hardware ECC
blocks?

If we prove this, we make IoT security infinitely leaner."

Ayush steps back. Himanshu steps up immediately and gestures to

the messy graphic on the left.
"To answer that first question, we have to dive into our hardware
methodology. As we mentioned, our canvas is the FPGA board. FPGAs are
essentially blank grids made up of Configurable Logic Blocks, or CLBs.

Normally, engineers let standard design software—like Xilinx Vivado—route

the electrical signals automatically. But Vivado prioritizes general efficiency,
not cryptographic symmetry. It creates a messy, asymmetrical layout. It
makes the baseline electronic race completely unfair. If the physical tracks
aren't identical down to the nanometer, the microchip's fingerprint is
mathematically useless.

So, our methodology requires taking absolute manual control. First, we

isolate the security system. We define specific physical regions on the chip
called Pblocks. This quarantines our oscillators to a specific thermal region,
preventing random hotspots elsewhere on the chip from messing with our
data.

Next, instead of automated routing, we use strict location rules—known as

BEL and LOC constraints—to hand-draw perfectly symmetrical tracks. We
literally compress five logic gates into a single tiny unit called a Look-Up
Table, or LUT6. Compacting the logic this way drastically reduces the routing
delay between stages. Furthermore, we manually route the connections to
guarantee the interconnect delay between every single oscillator stage is
nominally identical.

By forcing the physical layout to be perfectly identical on the microscopic

level, we ensure the baseline race is mathematically exact before the
environmental heat even touches the device."

Inani steps back. Harsh steps up instantly and gestures to the 3-

step flowchart.

"But perfect hardware is only half the battle; the real magic of our proposal is
the software brain. Even with identical physical tracks, extreme heat still
alters the signal speed.

Our solution is the Temperature-Aware Cooperative algorithm, or TAC. During

setup, we test how these tracks react to heat at , , and . The software
calculates how fast they expand and contract. Then, it intentionally pairs up
tracks that speed up and slow down at the exact same rate. If two paired
signals drift together when heated, the relative distance between them stays
perfectly stable.
Once we have these perfect pairs, we need to read the actual password.
Instead of using bulky hardware gates, we run a statistical test called SPRT
on the chip's onboard ARM processor. Think of SPRT as an adaptive referee.
Instead of watching the race for a fixed, long amount of time, it samples the
signals dynamically. The millisecond it gathers enough mathematical
evidence to be certain of the winner, it stops. This completely bypasses the
need for bloated hardware error correction

(Clicks to Slide 7: Budget)

Because we shifted the heavy lifting from the hardware to the software, our
budget is incredibly lean and efficient. As you can see, we hit exactly the
₹1,00,000 maximum constraint required for this proposal. We allocated
roughly ₹50,000 for our primary Zybo development board, ₹30,000 for a
secondary validation board, and the remainder for edge testing and thermal
sensors. We are delivering higher security with zero wasted resources."

Himanshu (Slot 2: ~8:00 - 10:00)

Slide 8: Expected Outcomes & Impact

"So, what is the exact return on investment for that ₹1 Lakh budget? We are
looking at massive, measurable outcomes in three specific areas.

First, thermal stability. By implementing our TAC pairing algorithm, we expect

to crush the thermal drift coefficient of these microchips. We project a
reduction from a highly volatile 2400 parts-per-million per degree Celsius,
down to a highly stable 80 parts-per-million.

Second, native reliability and uniqueness. That massive stabilization is

exactly what drives our hardware’s reliability score above 98%. Furthermore,
we aim for a perfect 50% uniqueness score, meaning every single chip we
produce is mathematically distinguishable from the next one off the
assembly line.

Finally, resilience against modern algorithmic threats. We aren't just

protecting against heat; we are protecting against Artificial Intelligence.
Because our logic mapping uses complex, multi-bit responses, we project
that advanced Machine Learning hacking attempts—specifically Support
Vector Machines and Logistic Regression attacks—will be kept below a 60%
predictive accuracy threshold. We are mathematically starving the AI of the
data it needs to guess the password.
Harsh (Slot 2: ~10:00 - 12:00)

Slide 9: Scope & Limitations

"However, rigorous engineering requires defining strict boundaries. We must

be entirely transparent about the limitations and scope of this proposal.

Regarding our scope, this architecture is highly optimized specifically for the
internal logic structures of Xilinx 7-Series FPGAs. The manual routing
constraints we apply—compressing those logic gates into LUTs—are specific
to this hardware ecosystem to ensure maximum efficiency. If we moved to an
Intel FPGA, the physical layout strategy would need to be rebuilt.

More importantly, regarding our limitations, this specific proposal is hyper-

focused on solving immediate environmental instability—specifically the
thermal range of to . We are intentionally excluding the effects of long-term
silicon aging. Over five to ten years, phenomena like Negative Bias
Temperature Instability, or NBTI, slowly degrade the chip's physical
performance. Analyzing decade-long physical wear and tear is a
fundamentally different challenge that falls outside the boundaries of this
immediate, 1-year project cycle."

Ayush (Slot 2: ~12:00 - 14:00)

Slide 10: 1-Year Action Plan

"To execute within those boundaries, here is our strict, 12-month action plan,
broken down into two-month sprints.

Phase one is the foundation. In January and February, we finalize the

required oscillator stages and our floorplan strategy. In March and April, we
move into HDL design, completing the initial RTL coding and functional
verification.

Phase two is the heavy lifting. May and June are dedicated exclusively to
manual physical implementation—executing those strict BEL and LOC
placement constraints on the silicon. July and August are when we write the
smart statistical firmware and port it directly to the ARM processor via the
AXI bus.

Finally, Phase three is the gauntlet. In September and October, we aren't

doing simple software simulations; we will physically place these edge nodes
into thermal climate chambers, cycling them from to . November and
December are reserved for final validation against strict NIST SP 800-22
security standards before we submit the final report. It is a lean, aggressive,
and highly feasible timeline."

Aditya(Slot 2: ~14:00 - 15:00)

Slide 11: Conclusion & Future Outlook

"To conclude, this proposal represents a fundamental paradigm shift in

hardware security. We are moving the burden of environmental
compensation away from rigid, expensive hardware gates, and moving it into
intelligent, adaptive firmware. By combining manual silicon layout for
physical symmetry with statistical software for real-time adaptation, we
provide low-power IoT devices with an unbreakable Root of Trust that actually
survives the unpredictable real world.

Looking ahead, we recommend two clear paths for scaling this technology.
First, conducting that long-term physical aging analysis to ensure these
silicon keys survive for decades of continuous use. Second, there is massive
economic potential in taking these stable fingerprints and integrating them
into a Blockchain network. This would create a decentralized 'PUF-as-a-
Service' authentication model—a PaaS system that could independently
verify millions of IoT devices across the globe without central servers.

Our core references are listed on the screen. That concludes our technical
briefing. We stand by our methodology, our budget, and our architecture. We
would now like to open the floor to your questions."