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CMOS Lab2

This document outlines a lab focused on CMOS simulation using SPICE with the ASU PTM 65 nm process, aiming to measure propagation delays and optimize PMOS sizing. It includes simulations of simple RC circuits, MOSFET IV characteristics, and inverter testbenches, as well as an analysis of PMOS width optimization for performance. Key results indicate optimal PMOS scaling factors for achieving symmetric delays and minimum propagation delay.

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Yasser Shoker
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4 views4 pages

CMOS Lab2

This document outlines a lab focused on CMOS simulation using SPICE with the ASU PTM 65 nm process, aiming to measure propagation delays and optimize PMOS sizing. It includes simulations of simple RC circuits, MOSFET IV characteristics, and inverter testbenches, as well as an analysis of PMOS width optimization for performance. Key results indicate optimal PMOS scaling factors for achieving symmetric delays and minimum propagation delay.

Uploaded by

Yasser Shoker
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Digital IC Design – Cadence Tools

Lab 02: CMOS Simulation Using SPICE

January 15, 2026

1 Introduction and Objectives


This lab focuses on characterising CMOS logic using SPICE simulations with the ASU PTM 65 nm
process. Key objectives include measuring propagation delays, extracting logical effort parameters
(g, p), and optimizing PMOS sizing for symmetric switching.

2 Simple RC Circuit (Figure 8.2)


The transient response of the RC circuit was simulated using a 2 kΩ resistor and a 100 fF capacitor,
resulting in a time constant (τ ) of 200 ps.

Figure 1: Output waveform of the simple RC circuit simulation.

3 MOSFET IV Characteristics (Figure 8.6)


In this section, the DC characteristics of a unit NMOS transistor were simulated. The simulation
performs a nested sweep: the Drain-to-Source voltage (VDS ) is swept from 0 V to 1.0 V, while the
Gate-to-Source voltage (VGS ) is stepped to produce a family of curves.

1
Figure 2: MOSFET Ids vs Vds characteristics.

4 Simple Inverter Testbench (Figure 8.8)


An unloaded unit inverter was simulated to measure propagation delays (tpd ). The textbook netlist
was modified to remove the .scale option, using absolute dimensions as required by the lab instruc-
tions.

Figure 3: Inverter transient response (Input vs Output).

2
5 Inverter Static (DC) Characteristics
The Voltage Transfer Curve (VTC) was obtained via a DC sweep of Vin .

Figure 4: VTC: Vout vs Vin .

6 Fanout-of-H Inverter Testbench (Figure 8.10)


To characterize the logical effort and parasitic delay, a chain of inverters was simulated with a varying
fanout H.

Figure 5: Fanout-of-4 inverters

3
Figure 6: Normalized delay vs. Fanout (H).

7 PMOS Width Optimization (Figure 8.11)


This section explores the effect of the PMOS/NMOS width ratio on inverter performance. While a 2:1
ratio is a common starting point, the lower mobility of holes in the 65 nm process typically requires
a larger PMOS to equalize rise and fall times.

Figure 7: Parametric sweep of PMOS scaling factor (P ) showing the crossover point for symmetric
delay.

Optimization Results:
• Optimal P for Symmetry (tpdr = tpdf ): 31
• Optimal P for Minimum Delay (tpd ): 360ps

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