Universidad
Carlos III de Madrid
Introduction to digital
integrated circuits
INTEGRATED CIRCUITS AND MICROELECTRONICS
Outline
1.1 Integrated Circuits. Advantages and
disadvantages over non integrated circuits.
Digital Circuits Implementation
Advantages of ICs
Moore’s Law
1.2 Design process of an integrated circuit.
Abstraction Levels.
Bottom-up and bottom-down methodologies.
Design process: steps and tools.
Abstraction levels
INTRODUCCIÓN 2
Digital Circuits Implementation (I)
Discrete components (standard)
74xx, 54xx
Integrated Circuits
ASIC: Application Specific Integrated circuit
Programmable circuits
PLD, SPLD: (Simple) Programmable Logic Devices
CPLD: Complex Programmable Logic Devices
FPGA: Field Programmable Gate Array
INTRODUCCIÓN 3
Digital Circuits Implementation (II)
Microprocessor systems
Microprocessor and additional components (standard
components)
SoC: System on Chip (ASIC)
SoPC: System on Programmable Chip (FPGA)
Soft core
Hard core
Design:
Board Level Hardware Design Not in this
course
Software Design
Tools: compilers
INTRODUCCIÓN 4
Digital Circuits Implementation (III)
Discrete CPLD FPGA ASIC
components
Integration (Number Very low Medium High Very High
of logic gates)
Speed Low Medium Medium Very High
< 100 MHz <200 MHz <500 MHz <4 GHz
Power consumption High Medium Medium Low
Initial cost High Medium Medium Very High
(design+prototype)
Cost per unit High Medium Medium Very Low
INTRODUCCIÓN 5
Moore’s Law (Intel co-founder)
The maximum number of transistors that can be
integrated in a I.C. will double about every 2
years (20 months)
INTRODUCCIÓN 6
Abstraction Levels
Levels:
System Synthesis
Algorithm
Register Transfer Level (RTL)
Logic: logic gates Analysis
Physical: transistors
INTRODUCCIÓN 7
Design Process
Bottom-up Methodology Top-down Methodology
Specification Specification
Block partition Architectural design
Logic gates design Detailed design
(schematic) Physical design
Block assembly Automatic
Physical design
Use of Hardware Description
Languages (HDL)
Obsolete
Intensive use of simulation
and automatic synthesis
INTRODUCCIÓN 8
Design process of integrated circuits
Functional specification
System description, chronograms
Architectural design
RTL design (registers, buses, state machines...)
Detailed design Automatic Tools
Automatic Synthesis
Logic Design (gates, flip-flops, ...)
Physical design
Transistors, place & route
Manufacturing and test, or programming
Operation
INTRODUCCIÓN 9
Design tools
Simulation
Functional description
RTL description (synthesizable)
List of gates (netlist)
With or without delays
Synthesis
Transform RTL descriptions into logic gates
Optimize logic for area and/or speed
Determine gate delays
Place & Route/Implementation
Place and interconnect logic gates
Extract delays of interconnections
INTRODUCCIÓN 10
Hardware Description Languages (HDLs)
HDLs allow us to:
Design at a higher abstraction level -> Increase productivity
Simulate designs for operation validation
Simulation is more efficient when performed at a higher abstraction level
Synthesize designs to obtain an optimal implementation,
depending on the target:
Area
Speed
Increase portability and reuse
Essential for modern design for:
Complex designs(>10K gates)
ASIC or CPLD/FPGA technologies
INTRODUCCIÓN 11
Goals
Basic digital circuits
Combinational circuits:
Logic gates, multiplexers, decoders, arithmetic circuits…
Sequential circuits:
Flip-flops, registers, counters, finite state machines, memories
VHDL
Functional description
Hierarchy: blocks and components
Simulation: testbenches
Synthesis
Circuit Design
Datapath, control
INTRODUCCIÓN 12