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DLX Instruction Cycle Overview

The document discusses the phases of the instruction cycle in a DLX pipeline, including instruction fetch, instruction decode/register fetch, execution/effective address calculation, memory access/branch completion, and write-back. It also covers pipeline hazards like structural hazards, data hazards that require stalls, and control hazards from branches. Forwarding techniques are described to minimize stalls from read-after-write hazards, and compiler scheduling and branch prediction are discussed as ways to reduce stalls from control hazards.

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syma masood
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44 views12 pages

DLX Instruction Cycle Overview

The document discusses the phases of the instruction cycle in a DLX pipeline, including instruction fetch, instruction decode/register fetch, execution/effective address calculation, memory access/branch completion, and write-back. It also covers pipeline hazards like structural hazards, data hazards that require stalls, and control hazards from branches. Forwarding techniques are described to minimize stalls from read-after-write hazards, and compiler scheduling and branch prediction are discussed as ways to reduce stalls from control hazards.

Uploaded by

syma masood
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd

DLX- Phases of Instruction Cycle Instruction Fetch Cycle (IF) IR Mem[PC] NPC PC + 4 Execution / effective address cycle (EX)

X) Memory reference ALUOutput A + IMM R-R ALU Instruction ALUOutput A func B R-Imm ALU Instruction ALUOutput A op Imm Branch ALUOutput NPC + Imm Cond (A op 0) Write-Back cycle (WB) R-R ALU Instruction Regs[IR16..20] ALUOutput R-Imm ALU Instruction Regs[IR11..15] ALUOutput Load Instruction Regs[IR11..15] LMD Instruction Decode/Register Fetch Cycle (ID) A Regs[IR6..10] B Regs[IR11..15] IMM ((IR16)16 ## IR16..31) Memory access / branch completion cycle (MEM) Memory reference (load) LMD Mem[ALUOutput] or (store) Mem[ALUOutput] B Branch If (cond) PC ALUOutput else PC NPC

Simple DLX Pipeline

Pipeline data paths

Pipeline Latches

Pipeline letch registers

Major Hurdles in Pipelining Structural Hazards Data Hazards Control Hazards

Structural Hazards

Inserting Bubbles/Stall

Data Hazards ADD SUB AND OR XOR R1 , R2 , R3 R4 , R1 , R5 R6 , R1 , R5 R8 , R1 , R9 R10,R1 ,R11

Need To Stall Pipeline

Minimizing Stalls by Forwarding (Bypassing / Short-Circuiting)

Three types of Data Hazards RAW (Read-After-Write) Instruction J tries to read a Source before I writes it WAW (Write-After-Write) (only is WRITE needs more than 1 pipe stages) J tries to write an operand before it is written by I LW R1, 0(R2) ADD R1,R2,R3 IF ID EX Mem1 Mem2 WB IF ID EX WB

WAR (Write-After-Read) J tries to write a destination before it is read by I SW 0(R2),R2 IF ID EX Mem1 Mem2 WB ADD R2,R3,R4 IF ID EX WB RAR (Read-AfterRead) ---- ??????

Data Hazards Requiring Stalls LW R1 , 0(R2) SUB R4 , R1 , R5 AND R6 , R1 , R7 OR R8 , R1 , R9

Load Interlock causes a stall to be inserted at clock cycle 4

Compiler Scheduling a=b+c d=ef LW Rb , b LW Rc , c ADD Ra, Rb, Rc SW a , Ra LW LW SUB SW Re , e Rf , f Rd, Re, Rf d , Rd LW Rb , b LW Rc , c Stall ADD Ra, Rb, Rc SW a , Ra LW LW Stall SUB SW Re , e Rf , f Rd, Re, Rf d , Rd LW Rb , b LW Rc , c LW Re , e ADD Ra, Rb, Rc LW Rf , f SW a , Ra SUB Rd, Re, Rf SW d , Rd

Control Hazards

Branch causes Three Cycle Stall

Reducing Stalls by moving logic of Zero Test and Branch Target Calculation

Reducing Branch Penalties Flush/Freeze the pipeline Predict-Not-Taken

Predict-Taken

Scheduling of Branch Delay Slot

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