Synchronous Sequential Circuit Design with PLA

This document discusses the design of synchronous sequential circuits using Programmable Logic Arrays (PLA). It provides the design procedure for sequential circuits using PLA, which involves deriving the state table and transition table then realizing the flip-flop input and output equations. An example of a BCD excess-3 code truth table is given. The document also compares PLA to ROM, noting advantages of PLA like reduced cost and chip size. It concludes by listing references used.

Uploaded by

Jasper Jeny

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PPT, PDF, TXT or read online on Scribd

100% found this document useful (1 vote)

323 views15 pages

Synchronous Sequential Circuit Design with PLA

Uploaded by

Jasper Jeny

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PPT, PDF, TXT or read online on Scribd

Introduction to PLAs
Design Procedure for Sequential Circuits
Implementation using PLA
References

DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUITS USING PLA

J JASPER BEUSAN JENY P REKHA SHARON

Programmable Logic Arrays (PLA) PLA is a integrated circuit that can be programmed to implement specific logic functions ie in sum of product [Link] And and OR array are [Link] it is flexible. Comparision with ROM: ROM is implemented in canonical form. PLA uses SOP form. Hence replaces many circuits. Hence reduced cost and chip size. Reduced no of minterms used.

Design Procedure for Sequential Circuits

[Link] the problem statement, determine the relationship between input and output Derive a state table(graph). [Link] the table to a minimum number of states. [Link] a unique combination of flip-flop states to correspond to each state in the reduced table. [Link] the transition table. [Link] next-state maps and input maps for each flip-flop. Derive the flip-flop input equations. Derive the output equations. [Link] the flip-flop input equations and the output equations. [Link] your design by signal tracing, computer simulation, or laboratory testing.

Truth table BCD

t3 0 t2 0 t1 0 t0 0 t3 0

EXCESS 3
t2 0 t1 1 t0 1

0
0 0 0 0 0 0 1 1

0
0 0 1 1 1 1 0 0

0
1 1 0 0 1 1 0 0

1
0 1 0 1 0 1 0 1

0
0 0 0 1 1 1 1 1

1
1 1 1 0 0 0 0 1

0
0 1 1 0 0 1 1 0

0
1 0 1 0 1 0 1 0

Implemented using PLA

Reference
[Link] [Link] [Link] /chap16_p1_4up.pdf Logic design by Roth.(pg: 235) Digital logic by yarbrough.(pg:496) Digital circuits and design by salivahanan. (pg:432)

THANK YOU!!!

DESIGN OF SYNCHRONOUS
SEQUENTIAL CIRCUITS USING
PLA
J JASPER BEUSAN JENY
P REKHA SHARON

Programmable Logic Arrays (PLA)
• PLA is a integrated circuit that can be
programmed to implement specific logic
functions

Design Procedure for Sequential
Circuits

• 1.Given the problem statement, determine the relationship
between input and

• Truth table
BCD EXCESS 3
t3
t2
t1
t0
t3
t2
t1
t0
0
0
0
0
0
0

VLSI Semi-Custom Design Training
No ratings yet
VLSI Semi-Custom Design Training
25 pages
VLSI Subsystem Design and Adders
No ratings yet
VLSI Subsystem Design and Adders
33 pages
Verilog HDL Programming Course Syllabus
No ratings yet
Verilog HDL Programming Course Syllabus
62 pages
Path Sensitization in VLSI Testing
100% (1)
Path Sensitization in VLSI Testing
34 pages
Switch-Level Modeling in Verilog
No ratings yet
Switch-Level Modeling in Verilog
21 pages
VLSI Design Flow and Y-Chart Overview
0% (1)
VLSI Design Flow and Y-Chart Overview
124 pages
Introduction To Actel FPGA Architecture PDF
50% (2)
Introduction To Actel FPGA Architecture PDF
8 pages
Iteration Bound in VLSI Design
No ratings yet
Iteration Bound in VLSI Design
12 pages
Designing Counters with Flip-Flops
100% (1)
Designing Counters with Flip-Flops
3 pages
ASIC Design: Transistors & Capacitance
100% (2)
ASIC Design: Transistors & Capacitance
32 pages
Adiabatic Logic for Low Power VLSI
No ratings yet
Adiabatic Logic for Low Power VLSI
16 pages
Pseudo-nMOS Logic Design Overview
No ratings yet
Pseudo-nMOS Logic Design Overview
31 pages
VLSI Design Exam Question Papers 2020-2021
No ratings yet
VLSI Design Exam Question Papers 2020-2021
11 pages
Low Power Design Methodologies in VLSI
No ratings yet
Low Power Design Methodologies in VLSI
20 pages
Overview of Programmable Logic Devices
No ratings yet
Overview of Programmable Logic Devices
36 pages
FPGA Design Flow Overview
No ratings yet
FPGA Design Flow Overview
2 pages
VLSI Subsystem Design Techniques
No ratings yet
VLSI Subsystem Design Techniques
53 pages
State Machine Design and Implementation
100% (22)
State Machine Design and Implementation
29 pages
4-Bit Manchester Carry Chain Adder
100% (1)
4-Bit Manchester Carry Chain Adder
3 pages
Gate-Level Modeling in Verilog Basics
No ratings yet
Gate-Level Modeling in Verilog Basics
25 pages
4-Bit Barrel Shifter Design in VLSI
No ratings yet
4-Bit Barrel Shifter Design in VLSI
56 pages
Advanced Digital System Design Notes
100% (1)
Advanced Digital System Design Notes
21 pages
CMOS Full Adder Circuit Designs
No ratings yet
CMOS Full Adder Circuit Designs
9 pages
Overview of Programmable Logic Devices
No ratings yet
Overview of Programmable Logic Devices
19 pages
VLSI Memory Architecture and Adders
No ratings yet
VLSI Memory Architecture and Adders
91 pages
CMOS Adder Architectures Overview
No ratings yet
CMOS Adder Architectures Overview
6 pages
VLSI Design Automation Techniques
No ratings yet
VLSI Design Automation Techniques
2 pages
CEC370 Low Power IC Design Lab Guide
No ratings yet
CEC370 Low Power IC Design Lab Guide
60 pages
VLSI Lab: NMOS and PMOS Analysis
100% (1)
VLSI Lab: NMOS and PMOS Analysis
24 pages
DFTS Question Bank for ECE II Semester
100% (1)
DFTS Question Bank for ECE II Semester
4 pages
Comparison of PROM, PAL, and PLA
100% (1)
Comparison of PROM, PAL, and PLA
31 pages
8-Bit Carry Bypass Adder Design
No ratings yet
8-Bit Carry Bypass Adder Design
8 pages
Testing Combinational Logic Circuits
No ratings yet
Testing Combinational Logic Circuits
39 pages
Cook-Toom Algorithm for Fast Convolution
No ratings yet
Cook-Toom Algorithm for Fast Convolution
27 pages
Elmore Delay in VLSI Design
No ratings yet
Elmore Delay in VLSI Design
11 pages
Static vs Dynamic CMOS Circuits Explained
100% (1)
Static vs Dynamic CMOS Circuits Explained
19 pages
Logic-Level Power Optimization Techniques
No ratings yet
Logic-Level Power Optimization Techniques
5 pages
VLSI Design Concepts and Techniques
No ratings yet
VLSI Design Concepts and Techniques
10 pages
Path Sensitization in Fault Detection
100% (2)
Path Sensitization in Fault Detection
4 pages
4-Bit Ripple Carry Counter Verilog
No ratings yet
4-Bit Ripple Carry Counter Verilog
14 pages
VLSI CAD Model Question Paper
No ratings yet
VLSI CAD Model Question Paper
2 pages
Folding in VLSI DSP Architectures
No ratings yet
Folding in VLSI DSP Architectures
35 pages
CMOS Digital IC Design Questions
No ratings yet
CMOS Digital IC Design Questions
2 pages
Verilog Sequential Logic Design Guide
No ratings yet
Verilog Sequential Logic Design Guide
26 pages
M.E. Advanced Digital System Design Exam
No ratings yet
M.E. Advanced Digital System Design Exam
2 pages
ASIC Cell Library Design Insights
No ratings yet
ASIC Cell Library Design Insights
12 pages
CMOS Half Adder Design and Analysis
100% (1)
CMOS Half Adder Design and Analysis
11 pages
VLSI Assignment Questions and Concepts
No ratings yet
VLSI Assignment Questions and Concepts
6 pages
FPGA Logic Design and Programming Guide
No ratings yet
FPGA Logic Design and Programming Guide
8 pages
CMOS Inverter Layout Design Rules
No ratings yet
CMOS Inverter Layout Design Rules
21 pages
VLSI Design Methodologies Overview
No ratings yet
VLSI Design Methodologies Overview
51 pages
Synchronous Sequential Circuit Analysis
No ratings yet
Synchronous Sequential Circuit Analysis
28 pages
Digital Circuit Design Fundamentals
No ratings yet
Digital Circuit Design Fundamentals
50 pages
Digital Design with ROMs, PALs, PLAs
No ratings yet
Digital Design with ROMs, PALs, PLAs
50 pages
Digital System Design Syllabus EC-PE501-D
No ratings yet
Digital System Design Syllabus EC-PE501-D
3 pages
ASIC Design and Automation Course Overview
No ratings yet
ASIC Design and Automation Course Overview
226 pages
Logic Design Syllabus Overview
0% (1)
Logic Design Syllabus Overview
80 pages
PLA and PAL in Digital Design
100% (1)
PLA and PAL in Digital Design
14 pages
Digital Logic Design Essentials
No ratings yet
Digital Logic Design Essentials
10 pages
Combinational Logic Design Timing
No ratings yet
Combinational Logic Design Timing
35 pages