54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control

June 1989

54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control
General Description
This circuit is a synchronous reversible up down counter The 191 is a 4-bit binary counter Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously when so instructed by the steering logic This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters The outputs of the four master-slave flip-flops are triggered on a low-to-high level transition of the clock input if the enable input is low A high at the enable input inhibits counting Level changes at either the enable input or the down up input should be made only when the clock input is high The direction of the count is determined by the level of the down up input When low the counter counts up and when high it counts down This counter is fully programmable that is the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs The output will change independent of the level of the clock input This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs The clock down up and load inputs are buffered to lower the drive requirement which significantly reduces the number of clock drivers etc required for long parallel words Two outputs have been made available to perform the cascading function ripple clock and maximum minimum count The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used or to the clock input if parallel enabling is used The maximum minimum count output can be used to accomplish look-ahead for high-speed operation

Features
Y Y Y Y Y Y Y

Single down up count control line Count enable control input Ripple clock output for cascading Asynchronously presettable with load control Parallel outputs Cascadable for n-bit applications Alternate Military Aerospace device (54191) is available Contact a National Semiconductor Sales Office Distributor for specifications

Connection Diagram
Dual-In-Line Package

TL F 6562 1

Order Number 54191DMQB 54191FMQB DM54191J DM54191W or DM74191N See NS Package Number J16A N16E or W16A

C1995 National Semiconductor Corporation

TL F 6562

RRD-B30M105 Printed in U S A

Absolute Maximum Ratings

(Note) Note The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings The Recommended Operating Conditions table will define the conditions for actual device operation

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 5 5V Operating Free Air Temperature Range b 55 C to a 125 C DM54 and 54 DM74 0 C to a 70 C Storage Temperature Range
b 65 C to a 150 C

Recommended Operating Conditions

Parameter Min 45 2

DM54191 Nom 5 Max 55 Min 4 75 2 08

DM74191 Nom 5 Max 5 25

Units V V 08
b0 8

V mA mA MHz ns ns ns ns

16 20 0 25 35 28 0 30 125 0

16 20

tSU tH tREL TA

70

Electrical Characteristics
Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Input Voltage Max

over recommended operating free air temperature range (unless otherwise noted) Conditions VCC e Min II e b12 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIH e Min VIL e Max VCC e Max VI e 5 5V VCC e Max VI e 2 4V VCC e Max VI e 0 4V VCC e Max (Note 2) VCC e Max (Note 3) Enable Others Enable Others DM54 DM74 DM54 DM74
b 20 b 18

Min

Typ (Note 1)

Max
b1 5

Units V V

24

34 02 04 1 120 40
b4 8 b1 6 b 65 b 65

V mA mA

High Level Input Current Low Level Input Current Short Circuit Output Current Supply Current

IIL

mA

IOS

mA

ICC

65 65

99 105

mA

Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time Note 3 ICC is measured with all inputs grounded and all outputs open Note 4 TA e 25 C and VCC e 5V

Switching Characteristics
Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter

at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) From (Input) To (Output) Min 20 Load to Any Q Load to Any Q Data to Any Q Data to Any Q Clock to Ripple Carry Clock to Ripple Carry Clock to Any Q Clock to Any Q Clock to Max Min Clock to Max Min Down Up to Ripple Carry Down Up to Ripple Carry Down Up to Max Min Down Up to Max Min Enable G to Ripple Carry Enable G to Ripple Carry 33 70 22 70 20 24 24 36 42 52 45 45 33 33 24 24 RL e 400X CL e 15 pF Max Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output

Logic Diagram
191 Binary Counter

TL F 6562 2

Pin (16) e VCC Pin (8) e GND

Timing Diagrams
191 Decade Counter Typical Load Count and Inhibit Sequences

TL F 6562 3

Physical Dimensions inches (millimeters)

16-Lead Ceramic Dual-In-Line Package (J) Order Number 54191DMQB or DM54191J NS Package Number J16A

54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control

Physical Dimensions inches (millimeters) (Continued)

16-Lead Molded Dual-In-Line Package (N) Order Number DM74191N NS Package Number N16E

16-Lead Ceramic Flat Package (W) Order Number 54191FMQB or DM54191W NS Package Number W16A LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user
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