EECS 105 Spring 2004, Lecture 15

Lecture 15: MOS Transistor models: Body effects, SPICE models

Prof. J. S. Smith

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Context
In the last lecture, we discussed the modes of operation of a MOS FET:

Voltage controlled resistor model I-V curve (Square-Law Model) Saturation model add a correction due to the changing depletion region, called the body effect Produce small signal models for the FET and look at how MOS Transistors are modeled in SPICE
University of California, Berkeley

In this lecture, we will:

Department of EECS

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Reading
Today, and Friday we will finish the material from chapter 4. Then we look at the analog characteristics of simple digital devices, 5.25.4 And following the midterm, we will cover PN diodes again in forward bias, and develop small signal models: Chapter 6 we will then take a week on bipolar junction transistor (BJT): Chapter 7 Then go on to design of transistor amplifiers: chapter 8
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

MOS operation
An inversion mode MOS transistor operates by producing a sheet carriers just under the oxide The names source and drain are picked so that the inversion charge is larger at the source end Approximate inversion charge QN(y): drain is higher than the source less charge at drain end of channel

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Gradual channel approximation

We have played pretty fast and loose, using the average charge and average velocity, etc. A more accurate model of the physics includes the fact that the charge density under the gate and the velocity vary along the channel length The current at each point along the length of the device must be independent of position in steady state (no buildup of charge)

I D = Wv y ( y )QN ( y )
Where ID is the drain current, y is the distance in the direction from the source to the drain, vy is the component of velocity in the sourcedrain direction, and QN(y) is the charge density of the electrons under the gate
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Gradual channel approximation -2

For most FETs the distances in y, the SourceDrain direction, are significantly larger than the distances in the x direction, (perpendicular to the oxide). If this assumption is not true, its called a short channel device. This means that the fields in the x direction are much stronger than the fields in the y direction. This is in the text, section 4.3, with the main difference from the simple approximation being the back gate effect, due to the variation in the depletion width to the body (substrate).
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Effect of substrate voltage

What is the effect of different substrate voltages?

Depletion width W changes Need to account for different depletion region charge

(VSB = 0): (VSB 0):

QB 0 = 2qN A S 2 P QB = 2qN A S 2 P + VSB

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Threshold voltage: general

General form (with substrate bias):

VT = VFB 2 P

QB 0 Qox Cox Cox

Substituting the capacitance as a function of voltage:

VT = VT 0 +
Where:

2 P + VSB 2 P
+ for NMOS - for PMOS

2qN A S Cox

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Threshold voltage, summary

If VSB = 0 (no substrate bias):
VT 0 = VFB 2 F QB Qox Cox Cox

If VSB 0 (non-zero substrate bias)

VT = VT 0 +

2 P + VSB

2 P

Body effect (substrate-bias) coefficient: 2qN A S = Cox (NMOS) Threshold voltage increases as VSB increases. The threshold voltage will also vary along the gate. This is called the body effect, or back gate effect.

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Threshold Voltage (NMOS vs. PMOS)

NMOS
(p-substrate)

PMOS
(n-substrate)

Substrate Fermi potential Depletion charge density Substrate bias coefficient Substrate bias voltage Threshold voltage
(enhancement devices)

p < 0 QB < 0 >0 VSB > 0 VT0 > 0

n > 0 QB > 0 <0 VSB < 0 VT0 < 0

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Body effect
Voltage VSB changes the threshold voltage of transistor

For NMOS, Body normally connected to ground for PMOS, body normally connected to Vcc Raising source voltage increases VT of transistor
G B p+ S n+ D n+ B S p+ G D p+

xj

n+

xj

N well NMOS PMOS

p-type substrate
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Threshold voltage adjustment

Threshold voltage can be changed by doping the channel region with donor or acceptor ions For NMOS:

The threshold voltage is increased by adding acceptor ions The threshold voltage is decreased by adding donor ions The threshold voltage is increased by adding donor ions The threshold voltage is decreased by adding acceptor ions Density of implanted ions = NI [cm-2]

For PMOS:

Approximate change in threshold voltage:

VT 0 =
Department of EECS

qN I Cox
University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Channel Length Modulation

As VDS is increased, the pinch-off point moves closer to source, shortening the channel length The drain current increases due to shorter channel

L' = L L I D = 1 nCox 2 W (VGS VTN )2 (1 + VDS ) L

= channel length modulation coefficient

Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Review
VGS < VTN ID = 0 VGS < VTP

Cutoff

Linear
VGS VTN , VDS < VGS VTN W 2 (VGS VT )VDS 1 VDS I D = Cox 2 VGS VTP , VDS > VGS VTP L

Saturation
VGS VTN , VDS VGS VTN W 2 I D = 1 Cox (VGS VT ) (1 + VDS ) 2 VGS VTP , VDS VGS VTP L
Note: if VSB 0, need to calculate VT
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

NMOS
i
VDS = VGS VT
Slope due to Channel length modulation

VGS Steps

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

PMOS

Slope due to Channel length modulation

VDS = VGS VT
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

We now have reasonable mathematical models for NMOS and PMOS field effect transistors. We will now develop small signal models, allowing us to make equivalent circuits. The whole idea will be to make models that you can manipulate easily, and analyze and design circuits with FETs. We will also look at how SPICE models FETs for both small signal models and large signal models

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Small signal models: two terminals

The current into a device depends on the history of voltages which have been applied to it

I (t ) = F{V ( < t )}
Lets say this can be written as a function of the voltage, and its derivative with respect to time

I (t ) =

f V (t ), dV (t )
dt
University of California, Berkeley

But that it is a nonlinear function

Department of EECS

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Often we will be interested in running devices at a particular steady voltage or operating point, and then have the time varying signal be small compared to the DC voltage. We write this:

V (t ) = V0 + v(t )
If we plug this back into our equation: dV (t ) dv(t ) I (t ) = f V (t ), = f V0 + v(t ), dt dt Lets assume that v(t) is very small, so we can do a Taylor expansion around 0
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

linearization
Taylor expansion about the first argument:
df ( x) f ( x) f ( x0 ) + x +L dx x = x0
I (t )

f V , dv(t ) + v(t )

dt

dv(t ) f (V , ), dt V =V0 V

Doing the same about the second argument: dv(t ) + I (t ) f (V0 ,0 ) + v(t ) f (V ,0) f (0, ) dt V V =V =0 We can then write:
0

I (t ) I 0 + v(t )

1 dv(t ) + C R dt

Where

I0 =

f (V ,0)
0

1 = f (V ,0) R V V =V0

C=

dv(t ) f (0, ) dt =0
University of California, Berkeley

Department of EECS

10

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

From math to equivalent circuit

We can then take:
I (t ) = I 0 + i (t )

Where i(t) is the small signal current. Then:

i (t ) v(t ) 1 dv(t ) + C R dt

But this mathematical formula relating the small signal voltage to the small signal currents can be i (t ) represented as a circuit again: +
v(t )
Which is why we picked R and C, of course!
Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Since a small change to a voltage or current into a device with other voltages or currents held constant generally results in a small, proportionate change, we can often model a device for small changes with linear equations. The linear equations can often be translated back into a circuit which would have the equivalent set of linear equations. Why would we do this? Because we can develop and use intuition about linear circuit elements, like resistors and capacitors, in series or parallel
Department of EECS University of California, Berkeley

11

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Constructing by inspection
Many times, rather than going through a process of deriving a mathematical formula and then translating it back into a circuit model, you can look at a device and create a equivalent circuit Charge storage is modeled as a capacitor Currents proportional to voltages are modeled by resistors. No model is perfect, build a simple model first, and then add to it as necessary Remember: Parallel: current gets a choice Series: current must go through both
Department of EECS University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

VLSI resistor
Lets construct a small signal model for a VLSI resistor:

Department of EECS

University of California, Berkeley

12

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Back to the FET

The current from the drain of our FET can be modeled for small signals:

iDS (t ) = I DS + ids
For a given operating point voltage for Vgs and Vds, we get:

ids =
Which we will then label:

iDS i vgs + DS vds vgs vds

ids = g m vgs +

1 vds ro

Transconductance

Conductance

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Substrate potential
Lets look at the back gate effect in a small signal model Effect: changes threshold voltage, which changes the drain current substrate acts like a backgate i i g mb = D = D v BS Q v BS Q
Q = (VGS, VDS, VBS) are all held constant

Department of EECS

University of California, Berkeley

13

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Backgate Transconductance
VT = VT 0 +

VSB 2 p 2 p

Result:
Department of EECS

g mb =

iD vBS

=
Q

iD VTn

VTn vBS

=
Q

gm
2 VBS 2 p
University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Notice that we have terms in our equations which give the small signal current into one terminal in as a constant times the small signal voltage into another terminal. In order to translate that into an equivalent circuit, we will use variable current sources
+ v1
i2 = gv1

Where g is called the transconductance

Department of EECS University of California, Berkeley

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EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Combining terms: Small-Signal Model

We now have three small singnal contributions to the current into the drain terminal for our FET, from changes in Vgs, Vbs, and Vds

ids = g m vgs + g mb vbs +

Department of EECS

1 vds ro
University of California, Berkeley

Notice that the change in the small signal current into the drain from A small signal change in Vds can be modeled as a resistor.

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Capacitances
While adequate for some purposes, the model so far implies that the current into the gate is zero. This is a good approximation for low frequencies, for high frequencies we need to account for the current necessary to charge up the gate to supply the field across the oxide. There are also stray capacitances to the drain and source contacts

Department of EECS

University of California, Berkeley

15

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

MOSFET Capacitances in Saturation

The gate-drain capacitance is only the fringe capacitance when in saturation, because it is pinched off from the charge in the channel. Gate-source capacitance: There is fringing charge between the edge of the gate and the source, but also to the channel

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Gate-Source Capacitance Cgs

Wedge-shaped charge in saturation (see H&S 4.5.4 for details) effective area is (2/3)WL

C gs = (2 / 3)WLCox + Cov
Overlap capacitance along source edge of gate

Cov = LDWCox
(This is an underestimate, fringing fields will make The overlap capacitance larger)

Department of EECS

University of California, Berkeley

16

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Gate-Drain Capacitance Cgd

There is no contribution due to change in inversion charge in channel, just overlap capacitance between drain and source

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Junction Capacitances

Prof. J. S. Smith

The source, gate, and drain will also have capacitances between them and the well or substrate. Capacitances to the drain and source will be junction capacitances, and since VSB and VDB = VSB + VDS reverse biases are different, the capacitances will be different

Department of EECS

University of California, Berkeley

17

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Seeking perfection
Remember that all of the capacitances, resistances and transimpedances will change as the operating point changes There is no such thing as a perfect small signal model, use the simplest one that is sufficient. Sometimes a small signal model is used well outside of where it is accurate, because it is the main way we can deal intuitively with these devices!

Department of EECS

University of California, Berkeley

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