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FSM and Clock Control VHDL Design

This document describes the design of a finite state machine (FSM) for sorting objects. It includes 6 sections that define different components of the sorting system: 1. The main FSM (fsm_mesinsortir) that controls the sorting process and outputs control signals. 2. A clock divider that generates 1 second and 0.5 second clock signals from the main clock. 3. A 7-segment display driver to display the count of objects sorted. 4. A counter timer used to time sorting processes. 5. An FSM for holding timer signals. 6. A frequency divider to generate signals for the 7-segment display and timers. Together, these components implement the control logic

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Muhammad Faiz
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6 views11 pages

FSM and Clock Control VHDL Design

This document describes the design of a finite state machine (FSM) for sorting objects. It includes 6 sections that define different components of the sorting system: 1. The main FSM (fsm_mesinsortir) that controls the sorting process and outputs control signals. 2. A clock divider that generates 1 second and 0.5 second clock signals from the main clock. 3. A 7-segment display driver to display the count of objects sorted. 4. A counter timer used to time sorting processes. 5. An FSM for holding timer signals. 6. A frequency divider to generate signals for the 7-segment display and timers. Together, these components implement the control logic

Uploaded by

Muhammad Faiz
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

B.

1 FSM (Finite State Machine) sortir benda


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fsm_mesinsortir is

port
( clk: in std_logic;
t_start, t_reset
: in std_logic;
s_utama
: in std_logic;
s_kabin
: in std_logic;
stoper_low, stoper_med, stoper_high : in std_logic;
TIMER
: in std_logic;
s_limit
: in std_logic_vector (2 downto 0);
m_konveutama
: out std_logic_vector (1 downto
m_konvelow
: out std_logic_vector (1 downto
m_konvemed
: out std_logic_vector (1 downto
m_konvehigh
: out std_logic_vector (1 downto
m_lifter
: out std_logic_vector (1 downto
m_kabin
: out std_logic_vector (1 downto
);
end fsm_mesinsortir;

0);
0);
0);
0);
0);
0)

architecture behavioral of fsm_mesinsortir is


type state is ( state_0 , state_1, state_2, state_3, state_4, state_5, state_6, state_7, state_8, state_9,
state_10, state_11, state_12 );
signal current_state, next_state : state;
begin
process (clk) is
begin
if ( clk'event and clk = '1' ) then
current_state <= next_state ;
end if ;
end process ;
process (current_state, t_start, s_utama, s_limit, s_kabin, stoper_low, stoper_med, stoper_high, TIMER)
is
begin
case (current_state) is
when state_0 =>
m_konveutama <="00";
m_kabin <="00";
m_lifter <="00";
m_konvelow <="00";
m_konvemed <="00";
m_konvehigh <="00";
if stoper_low = '0' then
next_state <= state_2;
elsif stoper_low = '1' then
next_state <= state_1;
else

next_state <= state_0;


end if;
when state_1 => if stoper_low = '0' then
next_state <= state_0;
else
next_state <= state_1;
end if;
m_lifter <="01"; -- lift turun
when state_2 => if (t_start = '0' and s_utama = '0') then
next_state <= state_3;
elsif t_reset = '0' then
next_state <= state_1;
else
next_state <= state_2;
end if;
m_lifter <="00";
when state_3 => if s_limit = "000" then --110 ( limit high = 1 , limit med = 1, limit low = 0)
next_state <= state_4; -- benda high
elsif s_limit = "100" then --100 ( limit high = 1, limit med = 0, limit low = 0)
next_state <= state_5; -- benda medium
elsif s_limit = "110" then -- 000 ( semua limit sensor nyala)
next_state <= state_6; -- benda low
else
next_state <= state_3;
end if;
m_konveutama<="10";
-------------------------------------------------- ( state_3 = proses sortir berlangsung)
when state_4 => if s_kabin = '0' then -- benda high
next_state <= state_7;
else
next_state <= state_4;
end if;
m_konveutama<="10";
m_kabin<="10";
when state_5 => m_kabin<="10";
if s_kabin = '0' then -- benda medium
next_state <= state_8;
else
next_state <= state_5;
end if;
m_konveutama<="10";
when state_6 => m_kabin<="10";
if s_kabin = '0' then -- benda low
next_state <= state_10;
else
next_state <= state_6;
end if;
m_konveutama<="10";
when state_7 => if TIMER = '1' then
next_state <= state_12; -- benda high
else
next_state <= state_7;
end if;

m_kabin<="10";
m_konvelow<="10";
m_konveutama<="00";
when state_8 => if stoper_med = '0' then
next_state <= state_9; -- benda medium
else
next_state <= state_8;
end if;
m_lifter<="10"; -- lift naik ke lt 2
m_konveutama<="00";
m_kabin<="00";
when state_9 => m_lifter<="00"; -- lift berhenti
if TIMER = '1' then -- benda medium
next_state<= state_12;
else
next_state<= state_9;
end if;
m_kabin<="10";
m_konvemed<="10";
when state_10 => if stoper_high = '0' then
next_state<= state_11; -- benda high
else
next_state<= state_10;
end if;
m_lifter<="10"; -- lift naik ke lt 3
m_konveutama<="00"
m_kabin<="00";
when state_11 => m_lifter<="00";
if TIMER = '1' then -- benda high
next_state <= state_12;
else
next_state <= state_11;
end if;
m_kabin<="10";
m_konvehigh<="10";
when state_12 => next_state <=state_0; -- end of the line
end case ;
end process ;
end behavioral ;

B.2 Clock Divider


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clock_divider is
port ( clockin
clockout_1s

: in std_logic;
: out std_logic;

clockout_setengah_s
);
end clock_divider;

: out std_logic

architecture behavioral of clock_divider is


signal clk1, clk2: std_logic;
signal satu_detik :std_logic_vector(25 downto 0);
signal setengah_detik :std_logic_vector(15 downto 0);
begin
process(clockin, satu_detik, setengah_detik )
begin
if clockin'event and clockin='1' then
satu_detik <= satu_detik + 1;
setengah_detik <= setengah_detik + 1;
end if;
clk1 <= satu_detik(25);
clk2 <= setengah_detik(15);
clockout_1s <= clk1;
clockout_setengah_s <= clk2;
end process;
end behavioral;

B.3 Seven Segment


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity seven_segm is
port (
clock,clk7, t_reset, s_utama_rst
: in std_logic;
S_COUNT_LOW, S_COUNT_MED, S_COUNT_HIGH : in std_logic;
D_out_A
: out std_logic_vector(3 downto 0)
D_out_B
: out std_logic_vector(3 downto 0);
D_out_C
: out std_logic_vector(3 downto 0);
com
: out std_logic_vector(2 downto 0)
);
end seven_segm;
architecture behavioral of seven_segm is
signal cnt1 : integer range 0 to 2;
signal satuan, puluhan, ratusan : integer range 0 to 9;
begin
process (clock, S_COUNT_LOW, S_COUNT_MED, S_COUNT_HIGH, t_reset )is
begin

if(clock' event and clock = '1') then


if(S_COUNT_LOW = '0') then
if satuan = 9
then
satuan <= 9;
else
satuan <= satuan+1;
end if;
elsif(S_COUNT_MED = '0') then
if puluhan = 9
then
puluhan <= 9;
else
puluhan <= puluhan+1;
end if;

elsif(S_COUNT_HIGH = '0') then


if ratusan = 9
then
ratusan <= 9;
else
ratusan <= ratusan+1;
end if;
elsif (satuan = 9 and s_utama_rst
satuan <= 0;
elsif (puluhan = 9 and s_utama_rst
puluhan <= 0;
elsif (ratusan = 9 and s_utama_rst
ratusan <= 0;
elsif(t_reset ='0') then
satuan <= 0;
puluhan <= 0;
ratusan <= 0;
end if;
end if;
end process;
process(clk7)
begin
if clk7 'event and clk7 = '1' then
if cnt1 = 2 then cnt1 <= 0;
else cnt1 <= cnt1 + 1;
end if;
end if;
end process;
process(cnt1)
begin
if cnt1 = 0 then
com <= "011";
if
satuan = 0 then D_out_A <= "0000";
elsif
satuan = 1 then D_out_A <= "0001";

='0') then
='0') then
='0') then

elsif
elsif
elsif
elsif
elsif
elsif
elsif
elsif
end if;

satuan
satuan
satuan
satuan
satuan
satuan
satuan
satuan

=
=
=
=
=
=
=
=

elsif cnt1 = 1 then


com <= "101";
if
puluhan
elsif
puluhan
elsif
puluhan
elsif
puluhan
elsif
puluhan
elsif
puluhan
elsif
puluhan
elsif
puluhan
elsif
puluhan
elsif
puluhan
end if;
elsif cnt1 = 2 then
com <= "110";
if
ratusan
elsif
ratusan
elsif
ratusan
elsif
ratusan
elsif
ratusan
elsif
ratusan
elsif
ratusan
elsif
ratusan
elsif
ratusan
elsif
ratusan
end if;

2
3
4
5
6
7
8
9

then
then
then
then
then
then
then
then

D_out_A
D_out_A
D_out_A
D_out_A
D_out_A
D_out_A
D_out_A
D_out_A

<=
<=
<=
<=
<=
<=
<=
<=

"0010";
"0011";
"0100";
"0101";
"0110";
"0111";
"1000";
"1001";

=
=
=
=
=
=
=
=
=
=

0
1
2
3
4
5
6
7
8
9

then
then
then
then
then
then
then
then
then
then

D_out_B
D_out_B
D_out_B
D_out_B
D_out_B
D_out_B
D_out_B
D_out_B
D_out_B
D_out_B

<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

"0000";
"0001";
"0010";
"0011";
"0100";
"0101";
"0110";
"0111";
"1000";
"1001";

=
=
=
=
=
=
=
=
=
=

0
1
2
3
4
5
6
7
8
9

then
then
then
then
then
then
then
then
then
then

D_out_C
D_out_C
D_out_C
D_out_C
D_out_C
D_out_C
D_out_C
D_out_C
D_out_C
D_out_C

<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

"0000";
"0001";
"0010";
"0011";
"0100";
"0101";
"0110";
"0111";
"1000";
"1001";

end if;
end process;
end behavioral;

B.4 Counter Timer


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity CNT_TIMER is
port ( clk,input_2s
output_2s
);
end CNT_TIMER;

: in std_logic;
: out std_logic

architecture behavioral of CNT_TIMER is

signal count_2s : integer range 0 to 2;


begin
process (input_2s, clk, count_2s) is
begin
if (input_2s = '1') then
if (clk' event and clk = '1') then
if (count_2s = 2)then
count_2s <= 0;
output_2s <= '1';
else
count_2s <= count_2s+1;
output_2s <= '0';
end if;
end if;
else
output_2s <= '0';
end if;
end process;
end behavioral;

B.5 FSM Holding


library ieee ;
use ieee.std_logic_1164.all ;
entity FSM_HOLDING is
port
( CLK, RESET
: IN STD_LOGIC;
S_COUNT_LOW, S_COUNT_MED, S_COUNT_HIGH : IN STD_LOGIC;
OUT_TIMER1, OUT_TIMER2, OUT_TIMER3
: OUT STD_LOGIC
);
end FSM_HOLDING ;
architecture behavioral of FSM_HOLDING is
type state1 is ( state1_0 , state1_1 );
type state2 is ( state2_0 , state2_1 );
type state3 is ( state3_0 , state3_1 );
signal present_state1 , next_state1 : state1 ;
signal present_state2 , next_state2 : state2 ;
signal present_state3 , next_state3 : state3 ;
begin
process ( CLK, present_state1, present_state2, present_state3 ) is
begin
if ( CLK 'event and CLK = '1' ) then
present_state1 <= next_state1 ;
present_state2 <= next_state2 ;
present_state3 <= next_state3 ;
end if ;
end process ;

process (present_state1 , S_COUNT_LOW, RESET) is


begin
case (present_state1) is
when state1_0 =>
OUT_TIMER1 <= '0';
if S_COUNT_LOW = '0' then
next_state1 <= state1_1 ;
else
next_state1 <= state1_0 ;
end if ;
when state1_1 =>
OUT_TIMER1 <= '1';
if RESET ='1' then
next_state1 <= state1_0 ;
else
next_state1 <= state1_1 ;
end if ;
end case ;
end process ;
process (present_state2, S_COUNT_MED, RESET) is
begin
case (present_state2) is
when state2_0 => OUT_TIMER2 <= '0';
if S_COUNT_MED = '0' then
next_state2 <= state2_1 ;
else
next_state2 <= state2_0 ;
end if ;
when state2_1 => OUT_TIMER2 <= '1';
if RESET ='1' then
next_state2 <= state2_0 ;
else
next_state2 <= state2_1 ;
end if ;
end case ;
end process ;
process (present_state3 , S_COUNT_HIGH, RESET) is
begin
case (present_state3) is
when state3_0 => OUT_TIMER3 <= '0';
if S_COUNT_HIGH = '0' then
next_state3 <= state3_1 ;
else
next_state3 <= state3_0 ;
end if ;
when state3_1 => OUT_TIMER3 <= '1';
if RESET ='1' then
next_state3 <= state3_0 ;
else
next_state3 <= state3_1 ;

end if ;
end case ;
end process ;
end behavioral ;

B.6 F_DIF
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity F_DIF is
port ( clk
perdetik
Clk7seg

: in std_logic;
: out std_logic;
: out STD_LOGIC;

);
end F_DIF;
architecture behavioral of F_DIF is
signal clk1, clk2: std_logic;
signal satu_detik :std_logic_vector(24 downto 0);
signal setengah_detik :std_logic_vector(15 downto 0);
begin
process(clk, satu_detik, setengah_detik )
begin
if clk'event and clk ='1' then
satu_detik <= satu_detik + 1;
setengah_detik <= setengah_detik + 1;
end if;
clk1 <= satu_detik(24);
clk2 <= setengah_detik(15);
perdetik <= clk1;
Clk7seg <= clk2;
end process;
end behavioral;

B.7 BCD A
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
entity BCD_A is
port (
D_in_A : in std_logic_vector(3 downto 0);
D_out_A
: out std_logic_vector(6 downto 0)
);
end BCD_A;
architecture behavioral of BCD_A is
begin
Process (D_in_A)
begin

if
elsif
elsif
elsif
elsif
elsif
elsif
elsif
elsif
elsif

D_in_A
D_in_A
D_in_A
D_in_A
D_in_A
D_in_A
D_in_A
D_in_A
D_in_A
D_in_A

=
=
=
=
=
=
=
=
=
=

"0000"
"0001"
"0010"
"0011"
"0100"
"0101"
"0110"
"0111"
"1000"
"1001"

then
then
then
then
then
then
then
then
then
then

D_out_A
D_out_A
D_out_A
D_out_A
D_out_A
D_out_A
D_out_A
D_out_A
D_out_A
D_out_A

<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

"0000001";
"0110111";
"1000010";
"0010010";
"0110100";
"0011000";
"0001000";
"0110011";
"0000000";
"0010000";

-----------

0
1
2
3
4
5
6
7
8
9

else D_out_A <= "1111111";


end if;
end process;
end behavioral;

B.8 BCD B
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
entity BCD_B is
port (
D_in_B : in std_logic_vector(3 downto 0);
D_out_B
: out std_logic_vector(6 downto 0)
);
end BCD_B;
architecture behavioral of BCD_B is
begin
Process (D_in_B)
begin
if
elsif
elsif
elsif
elsif
elsif
elsif
elsif
elsif
elsif

D_in_B
D_in_B
D_in_B
D_in_B
D_in_B
D_in_B
D_in_B
D_in_B
D_in_B
D_in_B

=
=
=
=
=
=
=
=
=
=

"0000"
"0001"
"0010"
"0011"
"0100"
"0101"
"0110"
"0111"
"1000"
"1001"

then
then
then
then
then
then
then
then
then
then

D_out_B
D_out_B
D_out_B
D_out_B
D_out_B
D_out_B
D_out_B
D_out_B
D_out_B
D_out_B

else D_out_B <= "1111111";


end if;
end process;
end behavioral;

B.9 BCD C
library ieee;
use IEEE.STD_LOGIC_1164.ALL;

<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

"0000001";
"0110111";
"1000010";
"0010010";
"0110100";
"0011000";
"0001000";
"0110011";
"0000000";
"0010000";

-----------

0
1
2
3
4
5
6
7
8
9

entity BCD_C is
port (
D_in_C : in std_logic_vector(3 downto 0);
D_out_C
: out std_logic_vector(6 downto 0)
);
end BCD_C;
architecture behavioral of BCD_C is
begin
Process (D_in_C)
begin
if
elsif
elsif
elsif
elsif
elsif
elsif
elsif
elsif
elsif

D_in_C
D_in_C
D_in_C
D_in_C
D_in_C
D_in_C
D_in_C
D_in_C
D_in_C
D_in_C

else

D_out_C <= "1111111";

end if;
end process;
end behavioral;

=
=
=
=
=
=
=
=
=
=

"0000"
"0001"
"0010"
"0011"
"0100"
"0101"
"0110"
"0111"
"1000"
"1001"

then
then
then
then
then
then
then
then
then
then

D_out_C
D_out_C
D_out_C
D_out_C
D_out_C
D_out_C
D_out_C
D_out_C
D_out_C
D_out_C

<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

"0000001";
"0110111";
"1000010";
"0010010";
"0110100";
"0011000";
"0001000";
"0110011";
"0000000";
"0010000";

-----------

0
1
2
3
4
5
6
7
8
9

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