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Memory Interface Design Overview

The document contains a user requirement for an embedded system with 5kB of data ROM, 5kB of data RAM, and 3 I/O ports. It determines that two chips each are needed for the ROM and RAM to accommodate the memory requirements, and one chip is needed for the I/O ports. It then divides the memory space into 8 divisions and maps the memory addresses for the two ROM chips, two RAM chips, and one I/O chip.

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Shamsul Arefin
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13 views1 page

Memory Interface Design Overview

The document contains a user requirement for an embedded system with 5kB of data ROM, 5kB of data RAM, and 3 I/O ports. It determines that two chips each are needed for the ROM and RAM to accommodate the memory requirements, and one chip is needed for the I/O ports. It then divides the memory space into 8 divisions and maps the memory addresses for the two ROM chips, two RAM chips, and one I/O chip.

Uploaded by

Shamsul Arefin
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

NAME : SHAMSUL AREFIN MIAH

ID: 021 131 023


SECTION : B

User requirement:

ASSIGNMENT : 4

ID: 021 131 023


Data ROM: 5kB
Data RAM: 5kB
I/O ports: 3

Calculating no. of chips required:


Data ROM: 4kB + 1kB (2 chips) , Data RAM: : 4kB + 1kB (2 chips), I/O ports: 3 (1
chip)
Memory space division:

= 8 divisions (Each division can hold a chip of maximum

size 8kB)

Memory Address:
Memory Map:
Data ROM:

4kB ROM (0000 1FFF)


1kB ROM (2000 3FFF)
Data RAM:

I/O
4kB RAM (4000 4FFF)
1kB RAM (6000 6FFF)

I/O chip:

8001, 8002, 8003

Circuit Diagram:

1kB RAM
4kB RAM
1kB ROM
4kB ROM

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