ASIC Design Flow
TS. Hoang Trang
ThS. Pham Dang Lam
12/2012
Cell Base Design Flow
Support Tools
(Languages)
Design flow
<file>.docx/xls/ppt
Specifications
System Level
Design
RTL Design
NG
Output
NG
SystemC (C++ with
Sysem C class)
Flatform / Model
VI, NotePath++
(Verilog/VHDL)
<file>.v
VCS/ModelSim,
etc(Verilog/ VHDL)
RTL Verification
Report file,
wave form
DC compiler
<file>.v (netlist),
<file>.sdf,
Reports
Netlist Verification
Formality
Report file
DFT
FastScan/Tmax/
Report file, Netlist
Prime Time
Report file, Netlist
ICC compiler
<file>.gds
Synthesis
Front
End
NG
STA
Place&Route
12/2012
Back
End
Cell Base Design Flow
Design flow
Support Tools
(Languages)
Output
<file>.docx/xls/ppt
Specifications
Design the one bit adder:
+ Three inputs (A, B, Cin)
+ Two output (S, Cout)
12/2012
How to start specification ?
Specifications
DSP
Data
Core
IPs
Bus
Control
Interface
12/2012
How to start specification ?
Specifications
DSP
Data
Core
IPs
Bus
Control
Interface
12/2012
How to start specification ?
Specifications
DSP
Data
Core
IPs
Bus
Control
Interface
12/2012
How to start specification ?
Specifications
DSP
Data
Core
IPs
Bus
Control
Interface
12/2012
How to start specification ?
Specifications
DSP
Data
Core
IPs
Bus
Control
Interface
???
12/2012
How to start specification ?
12/2012
Specifications
How to start specification ?
12/2012
Specifications
10
How to start specification ?
12/2012
Specifications
11
How to start specification ?
12/2012
Specifications
12
How to start specification ?
Specifications
Controller
12/2012
13
Cell Base Design Flow
12/2012
Specifications
14
How to start specification ?
12/2012
Specifications
15
How to start specification ?
12/2012
Specifications
16
Cell Base Design Flow
Specifications
DataPath
12/2012
17
How to start specification ?
Specifications
ALU - Controller
Sel_1
Sel_2
Sel_6
W
K
ALU - Data Path
f
12/2012
18
How to start specification ?
Specifications
Network-On-Chip (NoC) has been proposed as replacing
traditional bus architectures to solve complexity issues
such as synchronous frequency, infrastructure
interconnect and connective protocols when integrating
hundreds IP core or systems
[Link]
12/2012
19
How to start specification ?
Header
flit
Body flit
BW
Specifications
RC
VA
SA
ST
LT
BW
RC
VA
SA
ST
LT
BW: Buffer write
RC: Router computation
VA: Virtual allocation
SA: Switch allocation
ST: Switch traversal
LT : Link traversal
Amit Kumar Li-Shiuan Peh, Parth Kundu, Niraij [Link], Toward Ideal On-Chip
Communication Using Express Virtual Channels, [Link] 2008,
Princeton University.
12/2012
20
How to start specification ?
Specifications
NORTH
WEST
EAST
IP
SOUTH
12/2012
21
How to start specification ?
12/2012
Specifications
22
How to start specification ?
DataPath
Specifications
Controller
[Link]
12/2012
23
How to start specification ?
DataPath
Specifications
Controller
12/2012
24
How to start specification ?
DataPath
Specifications
Controller
12/2012
25
How to start specification ?
Specifications
How to model a behavior of one traffic light ?
Red
Green : 30 s
Green Yellow : 27s
Yellow Red
:3s
12/2012
26
How to start specification ?
Specifications
How to model a behavior of traffic light system?
Red
Green : 30 s
Green Yellow : 27s
Yellow Red
:3s
12/2012
27
ASSIGNMENT
Try to detail one of design in hardware
structure
Note that use many graphic and true table
instead of using behavior sentences
12/2012
28
Pipeline Concept
Pipe line not using state machine
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29
CPU & Proccessing
30
12/2012
Proccessing
IFetch
Reg/Dec
Exec
Mem
Wr
31
12/2012
Pileline Process
32
12/2012
Hazard &Solution
Structure Hazard
Data Hazard
Control Hazard
33
12/2012
Structure Hazard
34
12/2012
Structure Hazard
35
12/2012
Structure Hazard
36
12/2012
Structure Hazard
37
12/2012
Structure Hazard
38
12/2012
Structure Hazard
39
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Hazard &Solution
Structure Hazard
Data Hazard
Control Hazard
40
12/2012
Data Hazard
41
12/2012
Data Hazard
42
12/2012
Data Hazard
43
12/2012
Hazard &Solution
Structure Hazard
Data Hazard
Control Hazard
44
12/2012
Control Hazard
Jump
Jump for condition
Others
45
12/2012
Control Hazard
Using Noop
Moving the jump points to the other
places
Guessing
46
12/2012
Control Hazard
47
12/2012
Control Hazard
48
12/2012
Solution
49
12/2012
State Machine - Pipeline
Specifications
Write Mem
DataPath
Write Mem
GCU
Write Mem
GCU
Unit 02
Unit 01
12/2012
Viterbi
Unit 03
50
Thc Hin Ti
C Ch ng
ng
Write Mem
GCU
c T - Viterbi
Viterbi
Tun T
51
12/2012
Thc Hin Ti
Write Mem
GCU
Viterbi
Tun T
V
C Ch ng
ng
c T - Viterbi
ng ng
52
12/2012
Thc Hin Ti
Write Mem
GCU
Viterbi
Tun T
V
C Ch ng
ng
c T - Viterbi
ng ng
Write Mem
Write Mem
GCU
Write Mem
GCU
Viterbi
Write Mem
GCU
Viterbi
GCU
Viterbi
12/2012
Viterbi
53
Thc Hin Ti
C Ch ng
ng
Write Mem
GCU
c T - Viterbi
Viterbi
Tun T
V
ng ng
State 1
Write Mem
State 2
Write Mem
GCU
State 3
Write Mem
GCU
Viterbi
State 3
Write Mem
GCU
Viterbi
GCU
Viterbi
State 4
State 5
12/2012
Viterbi
54
Thc Hin Ti
C Ch ng
ng
Write Mem
GCU
c T - Viterbi
Viterbi
Tun T
V
ng ng
State 1
Write Mem
State 2
Write Mem
GCU
State 3
Write Mem
GCU
Viterbi
State 3
Write Mem
GCU
Viterbi
GCU
Viterbi
Loop
State 4
State 5
12/2012
Viterbi
55
State Machine - Pipeline
X cycles
Y cycles
Specifications
Z Cycles
Cycle Delay = max {X, Y, Z}
Cnt = cnt + 1 cnt == cycle_delay state_ena = 1
12/2012
56
Handshake- Pipeline
Write Mem
Viterbi
GCU
Notify
Confirm/Finish
12/2012
Specifications
Handshake- Pipeline
Notify
Confirm/Finish
How to cat the notify and confirm Prototype ?
Many to solve notify tasks ?
How to control and store the output data ?
How to improve the design ?
12/2012
Specifications