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Overview of Programmable Array Logic

Programmable Array Logic (PAL) is a programmable logic device with a fixed OR array and a programmable AND array, making it easier to program than a PLA but less flexible. A typical PAL has four inputs and four outputs. It consists of four sections, each with three programmable AND gates and one fixed OR gate. The AND gates have 10 programmable connections and one output is fed back to two AND gate inputs. An example shows four Boolean functions implemented using a PAL device.

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Julius Erick Evangelista
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16 views10 pages

Overview of Programmable Array Logic

Programmable Array Logic (PAL) is a programmable logic device with a fixed OR array and a programmable AND array, making it easier to program than a PLA but less flexible. A typical PAL has four inputs and four outputs. It consists of four sections, each with three programmable AND gates and one fixed OR gate. The AND gates have 10 programmable connections and one output is fed back to two AND gate inputs. An example shows four Boolean functions implemented using a PAL device.

Uploaded by

Julius Erick Evangelista
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Programmabl

e Array Logic
(PAL)

Programmable Array
Logic
The PAL is a programmable logic
device with a fixed OR array and a
programmable AND array. Because
only the AND gates are
programmable, the PAL is easier to
program than, but is not as flexible
as, the PLA.

Figure 7.16 shows the logic configuration of a


typical PAL with four inputs and four outputs.
Each input has a bufferinverter gate, and each
output is generated by a fixed OR gate. There are
four sections in the unit, each composed of an
ANDOR array that is three wide, the term used
to indicate that there are three programmable
AND gates in each section and one fixed OR gate.
Each AND gate has 10 programmable input
connections, shown in the diagram by 10 vertical
lines intersecting each horizontal line. The
horizontal line symbolizes the multipleinput
configuration of the AND gate. One of the outputs
is connected to a bufferinverter gate and then
fed back into two inputs of the AND gates.

As an example of using a PAL in the


design of a combinational circuit,
consider the following Boolean
functions, given in sumof
minterms form:
w(A, B, C, D) = (2, 12, 13)
x(A, B, C, D) = (7, 8, 9, 10, 11, 12,
13, 14, 15)
y(A, B, C, D) = (0, 2, 3, 4, 5, 6, 7,
8, 10, 11, 15)
z(A, B, C, D) = (1, 2, 8, 12, 13)

Simplifying the four functions to a


minimum number of terms results
in the following Boolean functions:
w = ABC + ABCD
x = A + BCD
y = AB + CD + BD
z = ABC + ABCD + ACD +
ABCD
= w + ACD + ABCD

Sequential
Programmabl
e Devices

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